Mapping Circuit Design To Programmable Logic Devices (plds) Patents (Class 716/116)
  • Patent number: 11176296
    Abstract: A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 16, 2021
    Assignee: Xilinx, Inc.
    Inventors: Pradip Jha, Brendan Matthew O'Higgins, Dinesh K. Monga, Bart Reynolds, Ryan Linderman
  • Patent number: 11062070
    Abstract: Systems or methods of the present disclosure may facilitate meeting connectivity demands between the dies of the modularized integrated circuits. Such an integrated circuit system may include a first die of programmable fabric circuitry that is communicatively coupled to a second die of modular periphery intellectual property (IP) tile via a modular interface. The modular interface may enable communication between a first microbump of the first die and a second microbump of the second die using a time-division multiplexing (TDM) technique. The modular interface may also enable communication between the first microbump and the second microbump using a wire-to-wire connection that does not comprise the TDM technique.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Chee Hak Teh
  • Patent number: 11036909
    Abstract: A method, system and computer program product, the method comprising: obtaining information of a circuit to be designed comprising two blocks, the information comprising: block components of the two blocks, information of connectors connecting the two blocks, information of a plurality of internal nets, each internal net connecting components within a same block, information of a plurality of external nets, each external net connecting a component to a connector; automatically generating a design of a merged block, the design comprising: a plurality of circuit components, comprising circuit components of the first block and the second block, each circuit component having a unique designator and an association to an original component; a plurality of internal circuit nets comprising a plurality of internal nets, each internal net associated with a unique designator and an association to a respective internal net designator, and a plurality of combined circuit nets based on the plurality of external nets, each
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 15, 2021
    Assignee: BQR RELIABILITY ENGINEERING LTD.
    Inventors: Yizhak Bot, Alex Gonorovsky, Isaac Rosenstein
  • Patent number: 11002790
    Abstract: A power gating system may include a logic circuit area configured to block a supply voltage from being supplied to a plurality of logic gates, when a test power-down mode is enabled; and a plurality of error detection circuits configured to detect logic gates whose output nodes float, among the plurality of logic gates, when the test power-down mode is activated.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10986005
    Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Rahul Khanna, Sujoy Sen, Karthik Kumar
  • Patent number: 10878154
    Abstract: The disclosed approaches involve evaluating by a design tool executing on a computer system, a plurality of nets of a circuit design for individual levels of suitability for cutting each net into a cut net that crosses a partition boundary between a plurality of partitions of an integrated circuit (IC) device. The design tool partitions the circuit design. The partitioning includes cutting one or more of the nets into cut nets and favoring the cutting of ones of the plurality of nets having a greater level of suitability over others of the plurality of nets having a lesser level of suitability. The design tool assigns each cut net to one group of a plurality of groups and inserts respective time-division multiplexing circuitry on each group of cut nets. The design toon then places the circuit design on the IC device.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 29, 2020
    Assignee: Xilinx, Inc.
    Inventors: Raoul Badaoui, Xiaojian Yang
  • Patent number: 10853554
    Abstract: Systems and methods for determining a configuration for a microarchitecture are described herein. An example system includes a proposal generator to generate a first candidate configuration of parameters for the microarchitecture, a machine learning model to process the first candidate configuration of parameters to output estimated performance indicators for the microarchitecture, an uncertainty checker to determine whether the estimated performance indicators are reliable, and a performance checker. In response to a determination that the estimated performance indicators are reliable, the performance checker is to determine whether the estimated performance indicators have improved toward a target. Further, if the estimated performance indicators have improved, the performance checker is to store the first candidate configuration of parameters in a memory as a potential solution for a microarchitecture without performing a full simulation on the first candidate configuration of parameters.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Javier Sebastian Turek, Javier Felip Leon, Alexander Heinecke, Evangelos Georganas, Luis Carlos Maria Remis, Ignacio Javier Alvarez, David Israel Gonzalez Aguirre, Shengtian Zhou, Justin Gottschlich
  • Patent number: 10839121
    Abstract: An example method for compiling by a processor-based system includes obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; generating a global mapping of the program nodes based on a representation of the array of data processing engines; generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning input/outputs of programmable logic (PLIOs) of the device to channels in an interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and translating the detailed mapping to a file.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 17, 2020
    Assignee: XILINX, INC.
    Inventors: Abhishek Joshi, Grigor S. Gasparyan
  • Patent number: 10817353
    Abstract: Creating an adaptable dynamic region for hardware acceleration can include receiving a first kernel for inclusion in a circuit design for an integrated circuit of an accelerator platform. The circuit design includes a dynamic design corresponding to a dynamic region of programmable circuitry in the integrated circuit that couples to a static region of the programmable circuitry. The first kernel can be included in the within the dynamic design. A global resource used by the first kernel can be determined. An interconnect architecture for the dynamic design can be constructed based on the global resource used by the first kernel.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 27, 2020
    Assignee: Xilinx, Inc.
    Inventors: Julian M. Kain, Adam P. Donlin
  • Patent number: 10817555
    Abstract: An invention is disclosed for systems, methods, processes, and products, including but not limited to, one that provides for user communication and interaction with as well as access to resources available on or via a computing device. An embodiment of the invention includes providing a digital resource gathering and dissemination system, method, or process that can accommodate digital resources of interest for heterogeneous groups and communities of online users for the same topic, demographic, or some other categories as provided by a particular classification scheme. Such a system, method, or process also provides a more reliable or otherwise representative selection of digital resources of interest to the population as a whole.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 27, 2020
    Inventor: Edmond K. Chow
  • Patent number: 10797078
    Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-An Lai, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen
  • Patent number: 10762264
    Abstract: Provided is for reducing access latency. A high-level synthesis device includes feature quantity obtaining unit and implementation determination unit. Feature quantity obtaining unit obtains an access feature quantity including a feature quantity relating to communication between a plurality of modules by analyzing an access pattern in communication between the plurality of modules. Implementation determination unit determines an implementation method for communicating between the plurality of modules based on the obtained access feature quantity.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 1, 2020
    Assignee: NEC CORPORATION
    Inventors: Seiya Shibata, Takashi Takenaka
  • Patent number: 10678979
    Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 9, 2020
    Assignee: Altera Corporation
    Inventors: Michael David Hutton, Herman Henry Schmit
  • Patent number: 10642630
    Abstract: In an embodiment, a method is disclosed providing an improvement in speed and efficiency of programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having a plurality of reconfigurable partitions and a plurality of primitive variations configurable in each of the reconfigurable partitions, the method comprising: before writing configuration bitstreams to the particular FPGA, compiling and storing, using digital storage, a plurality of primitive bitstreams for a plurality of different primitive functions that can be written to and implemented on the particular FPGA; receiving input in a graphical user interface to select and connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: LIQUID INSTRUMENTS PTY. LTD.
    Inventors: Daniel Anthony Shaddock, Max Andrew Gordon Schwenke, Danielle Marie Rawles Wuchenich, Benjamin Paul Coughlan, Timothy Tien-Yue Lam, Paul Anthony Altin
  • Patent number: 10614181
    Abstract: A method for circuit design automation includes appending a non-synthesizable input having a unique identifier to HDL code that specifies a physical input of the circuit. For the physical components in the circuit to which a signal from the physical input is to propagate, corresponding non-synthesizable components are appended, having respective identifiers assigned responsively to the unique identifier of the non-synthesizable input, to the HDL code that specifies the physical components. The design is verified by simulating operation of the circuit using the HDL code, including both the physical and non-synthesizable inputs and components. After verifying the design, a netlist synthesis tool automatically generates a netlist of the circuit including the physical inputs and components while omitting the non-synthesizable inputs and components.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 7, 2020
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Moshe Noah, Itamar Rabenstein, Irit Granovsky
  • Patent number: 10515165
    Abstract: In a first mode, a control circuit can implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during execution of the implemented circuit design with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an interface circuit and interconnect resources that are allocated to the circuit design implementation. Typical applications for performing access operations at the storage circuits include fault injection and observation, statistical monitoring of the circuit design, initialization and the distribution of certain signals such as reset signals, event sampling, just to name a few.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 24, 2019
    Assignee: Altera Corporation
    Inventors: Michael Hutton, Sean Atsatt
  • Patent number: 10430539
    Abstract: Methods and apparatus relating generally to synthesis are described. In such a method, a directed graph for a circuit design is generated. A cascaded chain is identified in the directed graph with a timing violation. A pipeline register stage of the cascaded chain is moved (or added) to remove the timing violation. The circuit design is transformed to provide a netlist including the pipeline register stage.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 1, 2019
    Assignee: XILINX, INC.
    Inventors: Chaithanya Dudha, Zhao Ma, Krishna Garlapati, Ashish Sirasao
  • Patent number: 10331833
    Abstract: The present disclosure relates to a method for generating an overall netlist (50) comprising the following steps: providing a first PLD code (24) as first netlist (26), wherein the first PLD code (24) has at least one first functional block (28), providing a second PLD code (30), wherein the second PLD code (30) has at least one second functional block (32) for alternative use instead of a corresponding first functional block (28), providing a switch PLD code (40) having at least one switch (42) assigned to the at least one first functional block (28) for connecting the first functional block (28) assigned to the switch (42), connecting the at least one second functional block (32) to one switch from the at least one switch (42) as an alternative to the corresponding first functional block (28), implementing at least one switch driving signal (44) for the at least one second functional block (32), wherein the at least one switch driving signal (44) is assigned to the corresponding switch (42) for connecting t
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: June 25, 2019
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventor: Matthias Bockelkamp
  • Patent number: 10289394
    Abstract: Utilities for use in generation of a single executable (e.g., single set of machine code) compatible with processors of multiple different architectures and/or versions with reduced levels of code bloating, no or limited changes to the source code, no or limited special code and/or data sections in the executable, and the like. Specifically, a compiler can selectively generate machine code for each of one or more particular C++ functions for each of a plurality of different processor versions and/or architectures in a “multi-version mode” or “multi-architecture mode” to allow such functions to perform better under different processor versions or architectures, avoid the need to maintain multiple entire object code sets for different processor versions or architectures, and allow for maintenance of a substantially complete C++ code mechanism.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 14, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Alfred Huang, William Y. Chen
  • Patent number: 10248746
    Abstract: A method for determining power consumed by a circuit is described that includes identifying a redundant frame including one of a clock toggle or a data toggle that is not propagated to an output pin of the circuit and identifying a non-redundant frame comprising a clock toggle and a data toggle that are propagated to the output pin of the circuit. Further, the method includes determining an ideal power consumed by the circuit during the non-redundant frame and providing a feedback to the user, the feedback including the redundant frame, a source of the redundant frame, and the ideal power consumed by the circuit during the non-redundant frame.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 2, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ajay Singh Bisht, Jayanta Roy, Kamlesh Kumar Madheshiya, Kunwar Prashant
  • Patent number: 10210914
    Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 19, 2019
    Inventor: Hare Krishna Verma
  • Patent number: 10204188
    Abstract: A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing a technology computer aided design data set corresponding to nominal performance of the semiconductor device, identifying a plurality of process variation sources that correspond to process variations that occur during the manufacturing of the semiconductor device, generating a nominal value look-up table of electrical parameters of the semiconductor device using nominal values of each of the plurality of process variation sources, and generating a plurality of process variation look-up tables of electrical parameters of the semiconductor device using variation values corresponding to each of the plurality of process variation sources that are identified as corresponding to the semiconductor device.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jing Wang, Nuo Xu, Woosung Choi
  • Patent number: 9984193
    Abstract: This application discloses a computing system implementing tools and mechanisms that can incorporate a security co-processor into a circuit design modeling an electronic device. The tools and mechanisms can configure the security co-processor to monitor at least a portion of the electronic device. The tools and mechanisms can generate at least one security action for the security co-processor to initiate when the security co-processor monitors the electronic device failing to conform to rules in a rules database.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 29, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Serge Leef, Ahmed Badran, Sudhir Kadkade
  • Patent number: 9767247
    Abstract: A method of circuit design may include identifying, using a processor, a timing critical path within a first look-up table structure in a circuit design and restructuring, using the processor, the first look-up table structure into a functionally equivalent second look-up table structure. The second look-up table structure may include fewer look-up tables serially coupled in the timing critical path than the first look-up table structure. The method may include placing, using the processor, the second look-up table structure and routing, using the processor, the second look-up table structure.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: September 19, 2017
    Assignee: XILINX, INC.
    Inventors: Ruibing Lu, Sabyasachi Das
  • Patent number: 9754065
    Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: September 5, 2017
    Assignee: Altera Corporation
    Inventors: Terry Borer, Gabriel Quan, Stephen D. Brown, Deshanand P. Singh, Chris Sanford, Vaughn Betz, Caroline Pantofaru, Jordan Swartz
  • Patent number: 9696991
    Abstract: Systems and methods for enhancing fixed-point operations, floating-point operations, or a combination thereof for programs implemented on an integrated circuit (IC) are provided. Portions of these operations may be shared among the operations. Accordingly, the embodiments described herein enhance these fixed-point operations, floating-point operations, or a combination thereof based upon these portions of the operations that may be shared.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 4, 2017
    Assignee: Altera Corporation
    Inventors: Martin Langhammer, Tomasz S. Czajkowski
  • Patent number: 9652581
    Abstract: Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA (directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 16, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Fedor Pikus, Juan Andres Torres Robles, Joydeep Mitra
  • Patent number: 9600356
    Abstract: A system for allocating field programmable gate array (FPGA) resources, comprises a plurality of FPGAs operable to implement one or more pipeline circuits; and one or more processors operable to determine the size of a set of data to be processed, determine an amount of time available to process the data set, determine an operational clock speed for the plurality of FPGAs, determine, based at least in part on the determined size of the set of data, the determined amount of time, and the determined operational clock speed, a number of FPGAs to allocate to process the set of data within the determined amount of time, and allocate at least the determined number of the plurality of FPGAs to process the set of data.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 21, 2017
    Assignee: Bank of America Corporation
    Inventor: Steven A. Guccione
  • Patent number: 9589091
    Abstract: A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 7, 2017
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Daryl Fox, Jonathan R. Quandt, Scott T. Becker
  • Patent number: 9581643
    Abstract: Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: February 28, 2017
    Assignee: XILINX, INC.
    Inventors: Graham F. Schelle, Yi-Hua E. Yang, Paul R. Schumacher, Patrick Lysaght
  • Patent number: 9230047
    Abstract: A method for designing a system on a target device is disclosed. A partition in the system with a plurality of instances from an extraction netlist is identified. Synthesis optimizations are performed on the partition to generate a synthesis optimization solution. The synthesis optimization solution is applied to the plurality of instances in the system.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: January 5, 2016
    Assignee: Altera Corporation
    Inventors: Babette Van Antwerpen, Gregg William Baeckler
  • Patent number: 9043739
    Abstract: Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventor: Steve Casselman
  • Patent number: 9026967
    Abstract: A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 5, 2015
    Assignee: Altera Corporation
    Inventor: Steven Perry
  • Publication number: 20150109024
    Abstract: An enhanced field programmable gate-array (FPGA) incorporates one or more programmable networks-on-chip (NoCs) or NoC components integrated within the FPGA fabric. This NoC interconnect augments the existing FPGA interconnect. In one embodiment, the NoC is used as system-level interconnect to connect compute and communication modules to one another and integrate large systems on the FPGA. The NoC components include a “fabric port”, which is a configurable interface that bridges both data width and frequency between the embedded NoC routers and the FPGA fabric components such as logic blocks, block memory, multipliers, processors or I/Os. Finally, the FPGA design flow is modified to target the embedded NoC components either manually through designer intervention, or automatically.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicants: Vaughn Timothy Betz, Mohamed Saied Abdelfatah
    Inventors: Mohamed Saied Abdelfattah, Vaughn Timothy Betz
  • Patent number: 9009646
    Abstract: A method for routing a design may comprise receiving a design for implementing in a target device, wherein the design includes an input/output (I/O) signal of a functional block, and wherein the functional block is assigned to a physical component of the target device; based on the design and on a routing resource graph representing the target device, calculating a route including the physical component and a physical pin of the target device; and assigning the physical pin of the target device to the I/O signal based on the calculated route.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Haneef Mohammed, Kyle Kearney
  • Patent number: 9009707
    Abstract: One or more physical RCDs (PRCDs) are shared between one or more workloads in one or more virtual computing environments. Example PRCD sharing operations may include: (1) providing a virtual RCD (VRCD) for one of the workloads, the VRCD being programmed with an IC design representing a hardware implementation of a software hotspot in the workload, (2) allocating one of the PRCDs to the workload by scheduling the programmed VRCD on the PRCD, (3) burning the PRCD with the IC design of the programmed VRCD so that the PRCD becomes a programmed PRCD that is capable of implementing the workload's hotspot in hardware, and (4) invoking the programmed VRCD instead of executing the hotspot as software in order to cause the programmed PRCD to implement the hotspot in hardware.
    Type: Grant
    Filed: November 30, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul Chandrakar, Anjil R. Chinnapatlolla, Manjunath N. Shanbhag, Venkatesh N. Sripathirao
  • Patent number: 9009703
    Abstract: One or more physical RCDs (PRCDs) are shared between one or more workloads in one or more virtual computing environments. Example PRCD sharing operations may include: (1) providing a virtual RCD (VRCD) for one of the workloads, the VRCD being programmed with an IC design representing a hardware implementation of a software hotspot in the workload, (2) allocating one of the PRCDs to the workload by scheduling the programmed VRCD on the PRCD, (3) burning the PRCD with the IC design of the programmed VRCD so that the PRCD becomes a programmed PRCD that is capable of implementing the workload's hotspot in hardware, and (4) invoking the programmed VRCD instead of executing the hotspot as software in order to cause the programmed PRCD to implement the hotspot in hardware.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul Chandrakar, Anjil R. Chinnapatlolla, Manjunath N. Shanbhag, Venkatesh N. Sripathirao
  • Patent number: 8997033
    Abstract: Techniques for compiling an integrated circuit (IC) design with a computer-aided design tool are provided. The IC design may include multiple dynamic configuration regions that may be updated during runtime without affecting other regions on the IC device. When an IC design is compiled for an IC device, dynamic configuration regions in the IC design are identified. The computer-aided design tool may generate a partial configuration file for each identified dynamic configuration region. Two or more partial reconfiguration files may be combined to obtain a single partial configuration file that may then be used to configure respective dynamic configuration regions on the IC device.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 31, 2015
    Assignee: Altera Corporation
    Inventor: Yin Chong Hew
  • Patent number: 8996348
    Abstract: An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the circuit design with a fault in the analog portion of the circuit design, simulating the circuit design with the fault for a fault interval time period, and determining whether the fault is detectable.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 31, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Victor Zhuk
  • Patent number: 8970250
    Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: March 3, 2015
    Assignee: Tabula, Inc.
    Inventors: Martin Voogel, Jason Redgrave, Trevis Chandler
  • Patent number: 8966420
    Abstract: A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Jae-Joon Kim, Rahul M. Rao
  • Patent number: 8949759
    Abstract: In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 8935645
    Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 13, 2015
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Gary Lai, Lu Zhou, Bruce B Pedersen
  • Patent number: 8935640
    Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: January 13, 2015
    Assignee: Tabula, Inc.
    Inventors: Brad Hutchings, Andrew Caldwell, Steven Teig
  • Patent number: 8924898
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
  • Patent number: 8924907
    Abstract: Various embodiments of the present disclosure provide techniques for verifying compatibility between a configuration image file bitstream for a programmable logic device (PLD) and an electrical circuit incorporating the PLD. The circuit includes an embedded processor, at least one memory device, and at least one input/output (I/O) device. A computer processing arrangement receives a user selection of the target image file, a first identifier of a first set of electrical circuit designs with which the target image file is compatible; and makes a determination whether or not the first circuit has a design included in the first set by comparing the first identifier with a second identifier, the second identifier corresponding to a design definition of the circuit.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Steve Jahnke, Yves Vandervennet
  • Patent number: 8910102
    Abstract: Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Altera Corporation
    Inventor: Kok Heng Choe
  • Patent number: 8910103
    Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Campi, Claudio Mucci, Stefano Pucillo, Luca Ciccarelli, Valentina Nardone
  • Patent number: 8896344
    Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: November 25, 2014
    Assignee: Altera Corporation
    Inventors: David Lewis, Valavan Manohararajah, David Galloway
  • Patent number: 8881082
    Abstract: A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace, within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity; and output a new logic gate design based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, producing a same output as the application specific integrated circuit with the logic gate design, based on same inputs.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Infinera Corporation
    Inventor: Vinay Adavani