Configuring Plds (including Data File, Bitstream Generation, Etc.) Patents (Class 716/117)
  • Patent number: 10657292
    Abstract: An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 19, 2020
    Assignee: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Patent number: 10657060
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing a partial reconfiguration of a partially reconfigurable programmable logic device. One of the methods includes providing, to an external memory device storing partial reconfiguration data, a first modified buffer offset. Before receiving partial reconfiguration data at the first modified buffer offset from the external memory, a first portion of prefetched data stored in local buffer memory is written to a configuration space of the partially reconfigurable device. When a first portion of data at the first modified buffer offset is received from the external memory device, the first portion of data at the first modified buffer offset is written to the configuration space of the partially reconfigurable device.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 19, 2020
    Assignee: XILINX, INC.
    Inventor: David Robinson
  • Patent number: 10623504
    Abstract: A relay module (30) for use in a lightweight machine to machine (LWM2M) communication network comprises a first interface module (31) for interfacing with one or more server devices, and a second interface module (33) for interfacing with a plurality of client devices. A processing unit (35) is adapted to establish at least one group object instance, wherein each group object instance is used to control communication between a server device and a group of client devices.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: April 14, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Oscar Novo Diaz, Nicklas Beijar, Domenico D'Ambrosio, Jaime Jiménez, Miika Komu, Mert Ocak, Patrik Salmela
  • Patent number: 10599404
    Abstract: A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: March 24, 2020
    Assignee: Altera Corporation
    Inventors: David Neto, Deshanand Singh, Tomasz Czajkowski, John Stuart Freeman, Tian Yi David Han
  • Patent number: 10572417
    Abstract: A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the controller unit and a network and having a first medium access controller for connection to the network and a second medium access controller coupled to the data port of the controller unit, the accelerator module being configured to: on behalf of the software entity, process incoming data packets received from the network in one or more streams associated with a first set of one or more network endpoints; encapsulate data resulting from said processing in network data packets directed to the software entity; and deliver the network
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: February 25, 2020
    Assignee: XILINX, INC.
    Inventor: Steven L. Pope
  • Patent number: 10558932
    Abstract: A system comprises a network of computers comprising a master computer and slave computers. For a machine learning problem that is partitioned into a number of correlated sub-problems, each master computer is configured to store tasks associated with the machine learning problem, and each of the slave computers is assigned one of the correlated sub-problems. Each slave computer is configured to store variables or parameters or both associated with the assigned one of the correlated sub-problems; obtain information about one or more tasks stored by the master computer without causing conflict with other slave computers with regard to the information; perform computations to update the obtained information and the variables or parameters or both of the assigned sub-problem; send the updated information to the master computer to update the information stored at the master computer; and store the updated variables or parameters or both of the assigned sub-problem.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 11, 2020
    Assignee: Google LLC
    Inventors: Hartmut Neven, Nan Ding, Vasil S. Denchev
  • Patent number: 10534621
    Abstract: An information processing apparatus has a processor and a programmable logic circuit device (PLD) that includes a reconfiguration region to configure a logic circuit requested by a configuration request from the processor. The processor compares a first execution time of a plurality of the logic circuits for a case when a degree of parallelism adjustment is performed by decreasing a degree of parallelism of a first logic circuit and increasing a degree of parallelism of a second logic circuit and a second execution time of the plurality of logic circuits for a case when the degree of parallelism adjustment is not performed, and requests the degree of parallelism adjustment to the PLD when the first execution time is shorter than the second execution time, and does not request the degree of parallelism adjustment to the PLD when the first execution time is not shorter than the second execution time.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: January 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: David Thach, Hisanori Fujisawa
  • Patent number: 10536336
    Abstract: Improved techniques for controlling operation of a portable electronic device are disclosed. Portable electronic devices which interact with a host electronic device can have their operational settings (e.g., configurations or preferences) remotely controlled. As a result, a host electronic device can offer a more sophisticated user interface and portable electronic devices need less local user interface features because these operational settings can be remotely controlled. The remotely-controlled (i.e., host controlled) operational settings are transferred to the portable electronic devices, whereby the portable electronic devices can thereafter operate in accordance with such settings.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 14, 2020
    Assignee: Apple Inc.
    Inventors: Greg Marriott, Andrew Bert Hodge
  • Patent number: 10250572
    Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 2, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Islam Mohamed Hatem Abdulfattah Mohamed Atta, Christopher Joseph Pettey, Nafea Bshara, Asif Khan, Mark Bradley Davis, Prateek Tandon
  • Patent number: 10181002
    Abstract: Circuitry for an efficient configuration data management is presented. The circuitry includes an encoding circuit that compares configuration data of a circuit design with base configuration data of a base circuit design. The encoding circuit compresses a difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data can be stored in a storage circuit. For a purpose of implementing the circuit design in an integrated circuit, a decoding circuit can retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare a result of the decompression operation with the base configuration data to restore the configuration data. The restored configuration data can serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 15, 2019
    Assignee: Altera Corporation
    Inventors: Junaid Asim Khan, Scott James Brissenden
  • Patent number: 10127341
    Abstract: Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 13, 2018
    Assignee: Altera Corporation
    Inventors: Jakob Raymond Jones, Prasanna Padmanabhan
  • Patent number: 10031732
    Abstract: High level synthesis can include detecting, using a processor, an enumerated operation within an instruction of a loop construct of an application, determining, using the processor, whether the loop construct meets a modification condition, and responsive to determining that the loop construct meets the modification condition, modifying, using the processor, the loop construct to calculate the enumerated operation as a compile time constant, wherein the modified loop construct is functionally equivalent to the loop construct.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: July 24, 2018
    Assignee: XILINX, INC.
    Inventors: Dong Li, Sheng Zhou, Stephen A. Neuendorffer
  • Patent number: 9985884
    Abstract: The present invention provides a data transmission method, apparatus and device, and a base station, and relates to the field of communications technologies. The method of the present invention includes: receiving data sent by a radio unit; acquiring a standard identity of the data, where the standard identity is used to identify a standard type of the data; routing the data according to the standard identity of the data; and sending the routed data to a digital unit corresponding to the standard identity of the routed data.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 29, 2018
    Assignee: Huawei Technologies Co., Ltd
    Inventors: Jueping Wang, Peng Lan, Si Zhang
  • Patent number: 9928199
    Abstract: A communication apparatus comprising a plurality of signal processing units configured to perform a set of pre-determined signal processing functions according to a set of parameters, a plurality of programmable crossbars coupled to the plurality of signal processing units, and a plurality of control processors coupled to the plurality of programmable crossbars and configured to adjust the plurality of programmable crossbars to interconnect the signal processing units to implement a selected communication protocol, wherein at least one of the programmable crossbars routes data from a first of the plurality of signal processing units to a second of the plurality of signal processing units forming a data path without interception from the plurality of control processors.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: March 27, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tomas Motos, Eivind Syvertsen, Marius Moe
  • Patent number: 9829537
    Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: November 28, 2017
    Assignee: SK hynix Inc.
    Inventors: Ji Hwan Kim, Jong Chern Lee
  • Patent number: 9811361
    Abstract: A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: November 7, 2017
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Stefan Merten, Marc Schlenger, Holger Ross, Frank Mertens
  • Patent number: 9747092
    Abstract: A substrate processing system includes a main controller, a module controller connected to the main controller, the module controller controlling a device on the basis of a command from the main controller, and a programmable logic controller connected to the module controller, wherein the module controller automatically downloads, from the main controller, module controller software to be used for control of the module controller, PLC software to be used for control of the programmable logic controller, and an automatic transfer software for automatically transferring the PLC software to the programmable logic controller.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: August 29, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventor: Taku Omori
  • Patent number: 9740809
    Abstract: Circuitry for efficient configuration data management is presented. The circuitry includes an encoding circuit that compares configuration data of a circuit design with base configuration data of a base circuit design. The encoding circuit compresses the difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data can be stored in a storage circuit. For a purpose of implementing the circuit design in an integrated circuit, a decoding circuit can retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare the result of a decompression operation with the base configuration data to restore the configuration data. The restored configuration data can serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 22, 2017
    Assignee: Altera Corporation
    Inventors: Junaid Asim Khan, Scott James Brissenden
  • Patent number: 9720805
    Abstract: Target device monitoring systems and methods are presented. In one embodiment, a host emulation target device control method includes receiving high level express interface direction to change a design element value. The design element values are associated with an operating target device. Design element values corresponding to the direction are created. The design element values are also forwarded to the operating target device in real time.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenneth Ogami, Andrew Best, Marat Zhaksilikov
  • Patent number: 9639454
    Abstract: A computer-readable recording medium storing therein a test data generating program to be executed by a computer, the program causing the computer to: generate, for each of a plurality of path conditions obtained by repeatedly performing symbolic execution, a simplified path condition by substituting a fixed value for a first symbolic variable included in the path condition; calculate, for each the simplified path condition, a value of the symbolic variable that satisfies the simplified path condition; generate test data including the values of the symbolic variable, the fixed values, and path conditions not subjected to simplification; and remove duplicative data from the test data that corresponds to a same path condition.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 2, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shoichiro Fujiwara, Tadahiro Uehara, Kazuki Munakata, Yoshiharu Maeda, Susumu Tokumoto, Asako Katayama, Supasit Monpratarnchai
  • Patent number: 9537973
    Abstract: CND load balancing in the cloud. Server resources are allocated at an edge data center of a content delivery network to properties that are being serviced by edge data center. Based on near real-time data, properties are sorted by trending traffic at the edge data center. Server resources are allocated for at least one property of the sorted properties at the edge data center. The server resources are allocated based on rules developed from long-term trends. The resource allocation includes calculating server needs for the property in a partition at the edge data center, and allocating the server needs for the property to available servers in the partition.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 3, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Marwan Batrouni, Jason Drew Zions, Octavian Homiou
  • Patent number: 9384010
    Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Brian V. Belmont, Animesh Mishra, James P. Kardach
  • Patent number: 9361421
    Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: June 7, 2016
    Assignee: Altera Corporation
    Inventors: David Samuel Goldman, Mark Bourgeault, Vaughn Betz, Alan Louis Herrmann
  • Patent number: 9298871
    Abstract: Disclosed is a method and system for translating parameterized cells (pcells) that are created using different programming languages. The pcell source code created in a first programming language undergoes a translation process to translate that source code to a second programming language. A validation process is also provided to ensure the correctness of the translations.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 29, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventor: Elias L. Fallon
  • Patent number: 9246928
    Abstract: A technique for determining scan lanes is provided. For a set of patterns, a number of scan lanes is estimated to be utilized on an accelerator. The number of the scan lanes estimated for the set of patterns is iteratively incremented to optimize a throughput of the accelerator. The set of patterns is distributed to the number of the scan lanes as a distribution, and each one of the scan lanes has a predetermined number of engines. A size of a memory space is evaluated that is needed for the distribution to distribute the set of patterns onto the number of scan lanes.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kubilay Atasu, Florian Dorfler, Christoph Hagleitner, Jan Van Lunteren
  • Patent number: 9183344
    Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 10, 2015
    Assignee: Altera Corporation
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 9152753
    Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The computer-implemented method also includes synthesizing the design into a plurality of PLD components. In the computer-implemented method, the synthesizing includes detecting an incrementer-multiplier operation in the design and merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 6, 2015
    Assignee: Lattice Semiconductor Corporation
    Inventors: Sunil Kumar Sharma, Amit Singh
  • Patent number: 9116751
    Abstract: According to the present invention, in changing the circuit configuration of a reconfigurable device, a circuit configuration change period is shortened while avoiding a dependency on processing contents without increasing the size of a circuit due to addition of a mechanism. Considering an execution order relation between a plurality of data flows, a setting change count necessary for changing the circuit configuration in changing processing is decreased within a constraint range, thereby shortening the circuit configuration change period.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 25, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yusuke Yachide
  • Patent number: 9111060
    Abstract: This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: August 18, 2015
    Assignee: Altera Corporation
    Inventors: Adam Titley, David Samuel Goldman
  • Patent number: 9043739
    Abstract: Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventor: Steve Casselman
  • Publication number: 20150135155
    Abstract: According to an embodiment, a semiconductor device switches circuit forms and circuit configurations of a plurality of analog functional circuits by rearranging a command execution order according to the command execution order set in advance irrespectively of a command execution order specified by a user and executing the commands.
    Type: Application
    Filed: October 20, 2014
    Publication date: May 14, 2015
    Inventor: Yutaka YOSHIZAWA
  • Patent number: 9030231
    Abstract: A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventors: David Lewis, Valavan Manohararajah, David Galloway
  • Publication number: 20150106776
    Abstract: A method and apparatus for configuring a programmable device, wherein a user may select from pre-defined user modules to select a configuration and corresponding function, representations of which are each displayed to the user, and instructions, based on the selected module, are automatically generated and used by the programmable device to implement the selected configuration and corresponding function.
    Type: Application
    Filed: July 29, 2014
    Publication date: April 16, 2015
    Inventors: Kenneth Y. Ogami, Douglas H. Anderson, Matthew A. Pleis, Frederick Redding Hood
  • Patent number: 9009707
    Abstract: One or more physical RCDs (PRCDs) are shared between one or more workloads in one or more virtual computing environments. Example PRCD sharing operations may include: (1) providing a virtual RCD (VRCD) for one of the workloads, the VRCD being programmed with an IC design representing a hardware implementation of a software hotspot in the workload, (2) allocating one of the PRCDs to the workload by scheduling the programmed VRCD on the PRCD, (3) burning the PRCD with the IC design of the programmed VRCD so that the PRCD becomes a programmed PRCD that is capable of implementing the workload's hotspot in hardware, and (4) invoking the programmed VRCD instead of executing the hotspot as software in order to cause the programmed PRCD to implement the hotspot in hardware.
    Type: Grant
    Filed: November 30, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul Chandrakar, Anjil R. Chinnapatlolla, Manjunath N. Shanbhag, Venkatesh N. Sripathirao
  • Patent number: 9009703
    Abstract: One or more physical RCDs (PRCDs) are shared between one or more workloads in one or more virtual computing environments. Example PRCD sharing operations may include: (1) providing a virtual RCD (VRCD) for one of the workloads, the VRCD being programmed with an IC design representing a hardware implementation of a software hotspot in the workload, (2) allocating one of the PRCDs to the workload by scheduling the programmed VRCD on the PRCD, (3) burning the PRCD with the IC design of the programmed VRCD so that the PRCD becomes a programmed PRCD that is capable of implementing the workload's hotspot in hardware, and (4) invoking the programmed VRCD instead of executing the hotspot as software in order to cause the programmed PRCD to implement the hotspot in hardware.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rahul Chandrakar, Anjil R. Chinnapatlolla, Manjunath N. Shanbhag, Venkatesh N. Sripathirao
  • Publication number: 20150095866
    Abstract: An embedded agent (104) of an integrated circuit (102) includes a collector (220) configured to receive from a tested target circuit a plurality of single bit lines of signals and a signal canceller (322) configured to receive an indication of lines that are not to be exported, for a given time period, and to set the indicated lines to a constant value. A linear combination calculation circuit (402) configured to generate a plurality of different linear combinations of the values of the single bit lines, for the clock cycles of the given time period, is also included in the embedded agent. A transmitter (216) exports from the chip a sub-group of the linear combinations calculated by the linear combination calculation circuit for the clock cycles of the given time period, the sub-group including a number of linear combinations selected responsively to the number of lines set to a constant value.
    Type: Application
    Filed: March 11, 2013
    Publication date: April 2, 2015
    Inventors: Gilad Cohen, Avi Rabinovich, Nadav Cohen, Tomer Labin, Noam Petrank
  • Patent number: 8997033
    Abstract: Techniques for compiling an integrated circuit (IC) design with a computer-aided design tool are provided. The IC design may include multiple dynamic configuration regions that may be updated during runtime without affecting other regions on the IC device. When an IC design is compiled for an IC device, dynamic configuration regions in the IC design are identified. The computer-aided design tool may generate a partial configuration file for each identified dynamic configuration region. Two or more partial reconfiguration files may be combined to obtain a single partial configuration file that may then be used to configure respective dynamic configuration regions on the IC device.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 31, 2015
    Assignee: Altera Corporation
    Inventor: Yin Chong Hew
  • Publication number: 20150088948
    Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Steven Perry, Martin Langhammer, Richard Maiden
  • Patent number: 8972923
    Abstract: Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: March 3, 2015
    Assignee: Maxeler Technologies Ltd.
    Inventor: Robert Gwilym Dimond
  • Patent number: 8959469
    Abstract: A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Altera Corporation
    Inventors: Doris Tzu-Lang Chen, Deshanand Singh
  • Patent number: 8949759
    Abstract: In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Clinton W. Kelly
  • Patent number: 8938704
    Abstract: An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 20, 2015
    Assignee: Xilinx, Inc.
    Inventors: Siddharth Rele, David A. Knol, Sumit Nagpal, Avdhesh Palliwal, Brendan M. O'Higgins
  • Patent number: 8935645
    Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 13, 2015
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Gary Lai, Lu Zhou, Bruce B Pedersen
  • Patent number: 8930876
    Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 6, 2015
    Assignee: Maxeler Technologies, Ltd.
    Inventors: Oliver Pell, Itay Greenspon, James Barry Spooner, Robert Gwilym Dimond
  • Patent number: 8924898
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 30, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
  • Patent number: 8924907
    Abstract: Various embodiments of the present disclosure provide techniques for verifying compatibility between a configuration image file bitstream for a programmable logic device (PLD) and an electrical circuit incorporating the PLD. The circuit includes an embedded processor, at least one memory device, and at least one input/output (I/O) device. A computer processing arrangement receives a user selection of the target image file, a first identifier of a first set of electrical circuit designs with which the target image file is compatible; and makes a determination whether or not the first circuit has a design included in the first set by comparing the first identifier with a second identifier, the second identifier corresponding to a design definition of the circuit.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Altera Corporation
    Inventors: Steve Jahnke, Yves Vandervennet
  • Patent number: 8910102
    Abstract: Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: December 9, 2014
    Assignee: Altera Corporation
    Inventor: Kok Heng Choe
  • Patent number: 8901956
    Abstract: An IC with configuration context switchers is provided. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Tabula, Inc.
    Inventors: Trevis Chandler, Jason Redgrave, Martin Voogel
  • Publication number: 20140351780
    Abstract: A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Inventors: Stephen William Keckler, William J. Dally, Steven Lee Scott, Brucek Kurdo Khailany, Michael Allen Parker
  • Patent number: 8890567
    Abstract: In one aspect, a method of testing an IC is provided. In one embodiment, the method includes: programming a resistive element in the IC at an intermediate ON state, where in addition to the intermediate ON state, the resistive element has another ON state, further where at the intermediate ON state, the resistive element has a resistance that is at least 10 times greater than a resistance of the resistive element at the another ON state; and applying test data to the resistive element.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 18, 2014
    Assignee: Altera Corporation
    Inventor: David Lewis