Abstract: Methods for counting synchronization (SYN) packets to identify a SYN attack, applicable to network device, are provided. The network device includes a field programmable gate array (FPGA) for counting the total number of received SYN packets and a high-speed hardware memory connected to the FPGA. One of the methods includes: periodically traversing the count entries stored in the high-speed hardware memory, and aging any count entry for which a time difference between a current time and a creation time reaches a preset aging time interval; obtaining a first number of SYN packets and a second number of SYN packets; and updating the total number of the received SYN packets with a sum of the first number of SYN packets and the second number of SYN packets.

Abstract: Programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having reconfigurable partitions and primitive variations configurable in each of the reconfigurable partitions, comprises: before writing configuration bitstreams to the FPGA, compiling and storing primitive bitstreams for different primitive functions that can be implemented on the particular FPGA; receiving input in a graphical user interface to connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the graphical blocks; obtaining, from the digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; using partial reconfiguration operations, writing the subset of the p

Abstract: A logic network for an integrated circuit is synthesized as follows. The logic network is mapped to a network of lookup tables (LUTs). The LUT mapping is based at least in part on estimated areas of the LUTs. The individual LUTs in the network are improved (LUT optimization), for example using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.

Abstract: In some embodiments, a client device may obtain an external signal. The hardware components of an integrated circuit of the client device may be reconfigured from a first configuration to a second configuration based on information in the external signal such that one or more portions of the integrated circuit that was previously inaccessible is now accessible and an application may access the one or more portions of the integrated circuit. Further, in response to a trigger, the components of the integrated circuit may reconfigure from the second configuration to the first configuration such that the one or more portions of the integrated circuit is inaccessible.

Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

Abstract: An optimized reconfiguration algorithm based on dynamic voltage and frequency scaling (DVFS) is provided, which mainly has the following contributions. The optimized reconfiguration algorithm based on DVFS proposes a DVFS-based reconfiguration method, which schedules user tasks according to a degree of parallelism (DOP) of the user tasks so as to reconfigure more parallel user tasks, thereby achieving higher reliability. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based heuristic approximation algorithm, which minimizes the delay of the DVFS-based reconfiguration scheduling algorithm. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based method, which reduces memory overhead caused by DVFS-based reconfiguration scheduling. The optimized reconfiguration algorithm based on DVFS improves the reliability of a field programmable gate array (FPGA) system and minimizes the area overhead of a hardware circuit.

Abstract: The present application discloses a verification platform for a system on chip and a verification method thereof, the method comprises: constructing a simulation verification environment for the system on chip; creating a bus function model unit, and binding the bus function model unit to the same interface at which a central processing unit being connected to the bus; creating an Universal Verification Methodology test instance, and performing the Universal Verification Methodology test instance by the bus function model unit to implement the system on chip test; creating a plurality of software test instances; and compiling the software test instances, and performing the compiled software test instances by the central processing unit to implement the system on chip test.

Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

Abstract: A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

Abstract: A resource scheduling method, to improve resource utilization of a field-programmable gate array (FPGA) device, includes receiving a resource scheduling request from a host, where the resource scheduling request requests to schedule a partial region (PR) on the FPGA device to serve a first virtual device (VD) of the host, the FPGA device includes N PRs, the host includes M VDs, each of the M VDs is configured corresponding to one virtual machine (VM), the first VD is one of the M VDs, and both N and M are integers greater than one, obtaining context content of the first VD based on the resource scheduling request, determining a target PR in the N PRs, and deploying the context content of the first VD in the target PR.

Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.

Abstract: Rebuilding a next compile-time Intellectual Property (IP) core can include determining an IP core included in a runtime design for an integrated circuit (IC) by evaluating metadata of the runtime design. The IP core specifies a circuit configured for implementation in programmable circuitry of the IC. Source code for the IP core may be retrieved automatically based on source data read from the metadata. A new instance of the IP core, including the source code, may be generated in a memory. The new instance of the IP core may be included within a new compile time design.

Abstract: A data processing system includes a plurality of resources suitable for processing data, a host suitable for requesting at least one of the plurality of resources to process the data, a plurality of data paths suitable for transferring the data between the host and the plurality of resources, and an arbiter suitable for dividing the plurality of resources into a plurality of groups, allocating at least one first data path of the plurality of data paths to each of the groups, and rearranging the plurality of groups, based on their respective transmission statuses, by additionally allocating at least one second data path of the plurality of data paths to each of the groups or by moving at least one resource from one of the plurality of groups to another of the plurality of groups.

Abstract: In some embodiments, a client device may obtain an external signal. The hardware components of an integrated circuit of the client device may be reconfigured from a first configuration to a second configuration based on information in the external signal such that one or more portions of the integrated circuit that was previously inaccessible is now accessible and an application may access the one or more portions of the integrated circuit. Further, in response to a trigger, the components of the integrated circuit may reconfigure from the second configuration to the first configuration such that the one or more portions of the integrated circuit is inaccessible.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.

Abstract: A storage device includes a memory device and a controller. The controller includes a programmable logic device which is reconfigurable, based on requests which are received from an outside of the storage device, to adaptively support a plurality of protocols depending on the requests. As the programmable logic device is programmed to support a first protocol among the plurality of protocols based on a first request which is received from the outside of the storage device with regard to the first protocol, the programmable logic device processes the first request in compliance with the first protocol, and the controller communicates with the memory device based on the first request such that the memory device stores or outputs data corresponding to the first request.

Abstract: A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Abstract: A method and a device for analyzing data are provided. The method includes following steps. A plurality of queries for an event stored in a database are integrated to obtain a plurality of features. Each feature is limited at a searching condition. A plurality of items of searched data are obtained from the database according to respective searching condition of each feature. Whether a data volume of the searched data is higher or lower than a predetermined range is determined. If the data volume is higher than the predetermined range, the data volume of the searched data is reduced according to the features. If the data volume is lower than the predetermined range, the data volume of the searched data is increased according to the features. A correlation between the features and the event is analyzed according to the searched data.

Abstract: Utilization metrics associated with a plurality of eligible compute tasks executable on a plurality of field-programmable gate arrays are determined. The utilization metrics are evaluated to dynamically identify a reallocation of an identified field-programmable gate array resource of the field-programmable gate arrays to handle a selected eligible compute task of the eligible compute tasks. The identified field-programmable gate array resource is automatically reprogrammed to handle the selected eligible compute task.

Abstract: A data processing system is described herein that includes two or more software-driven host components. The two or more host components collectively provide a software plane. The data processing system also includes two or more hardware acceleration components (such as FPGA devices) that collectively provide a hardware acceleration plane. A common physical network allows the host components to communicate with each other, and which also allows the hardware acceleration components to communicate with each other. Further, the hardware acceleration components in the hardware acceleration plane include functionality that enables them to communicate with each other in a transparent manner without assistance from the software plane.

Abstract: Implementations for template directories for cartridges in a multi-tenant Platform-as-a-Service (PaaS) system are disclosed. A method of the disclosure includes maintaining, by a node executed by a processing device, a cartridge library comprising cartridge packages that provide functionality for applications executed by the node for a multi-tenant Platform-as-a-Service (PaaS) system, embedding, by the node, a cartridge instance from the cartridge library in a gear of the node, providing, via the cartridge instance, a template directory to an application utilizing the cartridge instance on the node, and executing, by the node, a sample application from the template directory to demonstrate functionality of the cartridge instance to an application developer of the application.

Abstract: A tag identification device automatically identifies a correspondence relationship between a tag name arbitrarily set by a user and a process value. The tag identification device includes a processor, in a first process, that obtains first definition information in which the tag name, a type of tag data which is handled using the tag name, an upper limit value, an lower limit value, and an engineering unit are defined for each tag. The processor extracts, from the first definition information, a tag coinciding with at least one of the type of tag, the upper limit value, the lower limit value, and the engineering unit of a predetermined first process value. The processor selects the tag data handled using the tag name defined for the extracted tag, using an actual measurement value of the tag data. The processor identifies the selected tag data as the first process value.

Abstract: An integrated circuit may include a reconfigurable functional circuit block coupled to a microcontroller. The microcontroller may monitor a trigger register that receives trigger signals at a reconfiguration portion. The trigger signals may initiate corresponding reconfiguration operations by triggering the execution of instructions in a reconfiguration sequence program to load appropriate configuration data to configuration registers. The configuration registers may determine the operating mode of the functional circuit block by activating a subcomponent module in the functional circuit block. By providing a reconfiguration port that has full control of the reconfiguration of the functional circuit block, sensitive information regarding the implementation of the functional circuit block, the microcontroller, and connections therebetween may be protected while simplifying the design process for a custom logic circuit generated based on the reconfigurable functional circuit block.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: In some embodiments, a client device may obtain an external signal. The hardware components of an integrated circuit of the client device may be reconfigured from a first configuration to a second configuration based on information in the external signal such that one or more portions of the integrated circuit that was previously inaccessible is now accessible and an application may access the one or more portions of the integrated circuit. Further, in response to a trigger, the components of the integrated circuit may reconfigure from the second configuration to the first configuration such that the one or more portions of the integrated circuit is inaccessible.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: Some embodiments of the invention provide a novel method of migrating virtualized computing instances (VCIs) that implement a multi-node application. The method may identify a plurality of VCIs that implement a multi-node application, each of the plurality of VCIs being executed on a respective source host, and may identify a role performed by each VCI of the identified plurality of VCIs. The method may also generate a plurality of batches, each batch of the plurality of batches including a set of the identified plurality of VCIs selected based on the identified role of each of the VCIs, and generate a migration sequence comprising an ordered sequence of the plurality of batches. The method may migrate the identified plurality of VCIs from its respective source host to a respective destination host according to the migration sequence.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing a partial reconfiguration of a partially reconfigurable programmable logic device. One of the methods includes providing, to an external memory device storing partial reconfiguration data, a first modified buffer offset. Before receiving partial reconfiguration data at the first modified buffer offset from the external memory, a first portion of prefetched data stored in local buffer memory is written to a configuration space of the partially reconfigurable device. When a first portion of data at the first modified buffer offset is received from the external memory device, the first portion of data at the first modified buffer offset is written to the configuration space of the partially reconfigurable device.

Abstract: An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.

Abstract: A relay module (30) for use in a lightweight machine to machine (LWM2M) communication network comprises a first interface module (31) for interfacing with one or more server devices, and a second interface module (33) for interfacing with a plurality of client devices. A processing unit (35) is adapted to establish at least one group object instance, wherein each group object instance is used to control communication between a server device and a group of client devices.

Abstract: A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.

Abstract: A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the controller unit and a network and having a first medium access controller for connection to the network and a second medium access controller coupled to the data port of the controller unit, the accelerator module being configured to: on behalf of the software entity, process incoming data packets received from the network in one or more streams associated with a first set of one or more network endpoints; encapsulate data resulting from said processing in network data packets directed to the software entity; and deliver the network

Abstract: A system comprises a network of computers comprising a master computer and slave computers. For a machine learning problem that is partitioned into a number of correlated sub-problems, each master computer is configured to store tasks associated with the machine learning problem, and each of the slave computers is assigned one of the correlated sub-problems. Each slave computer is configured to store variables or parameters or both associated with the assigned one of the correlated sub-problems; obtain information about one or more tasks stored by the master computer without causing conflict with other slave computers with regard to the information; perform computations to update the obtained information and the variables or parameters or both of the assigned sub-problem; send the updated information to the master computer to update the information stored at the master computer; and store the updated variables or parameters or both of the assigned sub-problem.

Abstract: An information processing apparatus has a processor and a programmable logic circuit device (PLD) that includes a reconfiguration region to configure a logic circuit requested by a configuration request from the processor. The processor compares a first execution time of a plurality of the logic circuits for a case when a degree of parallelism adjustment is performed by decreasing a degree of parallelism of a first logic circuit and increasing a degree of parallelism of a second logic circuit and a second execution time of the plurality of logic circuits for a case when the degree of parallelism adjustment is not performed, and requests the degree of parallelism adjustment to the PLD when the first execution time is shorter than the second execution time, and does not request the degree of parallelism adjustment to the PLD when the first execution time is not shorter than the second execution time.

Abstract: Improved techniques for controlling operation of a portable electronic device are disclosed. Portable electronic devices which interact with a host electronic device can have their operational settings (e.g., configurations or preferences) remotely controlled. As a result, a host electronic device can offer a more sophisticated user interface and portable electronic devices need less local user interface features because these operational settings can be remotely controlled. The remotely-controlled (i.e., host controlled) operational settings are transferred to the portable electronic devices, whereby the portable electronic devices can thereafter operate in accordance with such settings.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: Circuitry for an efficient configuration data management is presented. The circuitry includes an encoding circuit that compares configuration data of a circuit design with base configuration data of a base circuit design. The encoding circuit compresses a difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data can be stored in a storage circuit. For a purpose of implementing the circuit design in an integrated circuit, a decoding circuit can retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare a result of the decompression operation with the base configuration data to restore the configuration data. The restored configuration data can serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.

Abstract: Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.

Abstract: High level synthesis can include detecting, using a processor, an enumerated operation within an instruction of a loop construct of an application, determining, using the processor, whether the loop construct meets a modification condition, and responsive to determining that the loop construct meets the modification condition, modifying, using the processor, the loop construct to calculate the enumerated operation as a compile time constant, wherein the modified loop construct is functionally equivalent to the loop construct.

Abstract: The present invention provides a data transmission method, apparatus and device, and a base station, and relates to the field of communications technologies. The method of the present invention includes: receiving data sent by a radio unit; acquiring a standard identity of the data, where the standard identity is used to identify a standard type of the data; routing the data according to the standard identity of the data; and sending the routed data to a digital unit corresponding to the standard identity of the routed data.

Abstract: A communication apparatus comprising a plurality of signal processing units configured to perform a set of pre-determined signal processing functions according to a set of parameters, a plurality of programmable crossbars coupled to the plurality of signal processing units, and a plurality of control processors coupled to the plurality of programmable crossbars and configured to adjust the plurality of programmable crossbars to interconnect the signal processing units to implement a selected communication protocol, wherein at least one of the programmable crossbars routes data from a first of the plurality of signal processing units to a second of the plurality of signal processing units forming a data path without interception from the plurality of control processors.

Abstract: A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

Abstract: A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.

Abstract: A substrate processing system includes a main controller, a module controller connected to the main controller, the module controller controlling a device on the basis of a command from the main controller, and a programmable logic controller connected to the module controller, wherein the module controller automatically downloads, from the main controller, module controller software to be used for control of the module controller, PLC software to be used for control of the programmable logic controller, and an automatic transfer software for automatically transferring the PLC software to the programmable logic controller.

Abstract: Circuitry for efficient configuration data management is presented. The circuitry includes an encoding circuit that compares configuration data of a circuit design with base configuration data of a base circuit design. The encoding circuit compresses the difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data can be stored in a storage circuit. For a purpose of implementing the circuit design in an integrated circuit, a decoding circuit can retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare the result of a decompression operation with the base configuration data to restore the configuration data. The restored configuration data can serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design.

Abstract: Target device monitoring systems and methods are presented. In one embodiment, a host emulation target device control method includes receiving high level express interface direction to change a design element value. The design element values are associated with an operating target device. Design element values corresponding to the direction are created. The design element values are also forwarded to the operating target device in real time.

Abstract: A computer-readable recording medium storing therein a test data generating program to be executed by a computer, the program causing the computer to: generate, for each of a plurality of path conditions obtained by repeatedly performing symbolic execution, a simplified path condition by substituting a fixed value for a first symbolic variable included in the path condition; calculate, for each the simplified path condition, a value of the symbolic variable that satisfies the simplified path condition; generate test data including the values of the symbolic variable, the fixed values, and path conditions not subjected to simplification; and remove duplicative data from the test data that corresponds to a same path condition.

Abstract: CND load balancing in the cloud. Server resources are allocated at an edge data center of a content delivery network to properties that are being serviced by edge data center. Based on near real-time data, properties are sorted by trending traffic at the edge data center. Server resources are allocated for at least one property of the sorted properties at the edge data center. The server resources are allocated based on rules developed from long-term trends. The resource allocation includes calculating server needs for the property in a partition at the edge data center, and allocating the server needs for the property to available servers in the partition.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.