Abstract: A system and method for automatically generating placement of vias within redistribution layers of a semiconductor package are described. In various implementations, a user defines attributes to use for automatic via generation in redistribution layers of a semiconductor package. The circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator. The automatic via generator uses the attributes, data indicative of the RDL netlist of signal routes within the RDL, and RDL mask layout data representing the signal masks of the metal layers within the RDL. The processor generates placement of vias for in the RDL based on the attributes and an identification of overlapping regions between metal layers.

Abstract: A method for producing a printed circuit board on a substrate uses control data derived from a circuit schematic, CAD file, Gerber file or files or equivalents, to operates a function head configured to effect printing conductive and non-conductive materials on the substrate and produces control data to effect the circuit printing. The method optionally uses a layout translation module configured to accept PCB multilayer circuit board files and convert multilayer circuit board layout data of the PCB multilayer circuit board files to printing data files for controlling the function head to print conductive material and nonconductive material onto the substrate to produce a printed circuit effecting functionality of the multilayer circuit board layout data.

Abstract: Aspects of the invention include configuring an initial tile with a plurality of portions, placing the initial tile at a location of the integrated circuit, and overlaying a clock mesh placement at the location. One or more of the plurality of portions of the initial tile that overlap with the clock mesh placement are determined, and the initial tile is modified, based on the determining the one or more of the plurality of portions, to generate a final tile. A design of the integrated circuit is finalized for fabrication based on using the final tile at the location, the final tile representing a plate of a metal insulator metal capacitor (MIMCAP).

Abstract: A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second cost from the multitude of tap points to a multitude of clock sinks associated with the multitude of tap points, and determining the symmetric clock configuration cost in accordance with the first cost and the second cost.

Abstract: A capacitor of a semiconductor device and a distributed model circuit for the same are disclosed. The capacitor includes a lower electrode layer, a plurality of upper electrode layers disposed over the lower electrode layer, a plurality of dielectric layers disposed between the lower electrode layer and each of the plurality of upper electrode layers, each dielectric layer configured to include a plurality of storage nodes, a plurality of line layers disposed over at least one of the plurality of upper electrode layers, and configured to receive a voltage for measuring an equivalent series resistance (ESR), and a plurality of contacts that electrically couple the plurality of line layers to the at least one of the plurality of upper electrode layers, wherein a resistance resulting from position information of the plurality of line layers and the plurality of contacts in a routing pattern corresponds to the ESR.

Abstract: Aspects of the invention include a computer-implemented method of hierarchical large block synthesis (HLBS). At least a partial ring is created around an HLBS structure. The partial ring includes at least one or more of filler elements, which are engineering change order (ECO) books for adding repeaters to wire dominated nets, and decoupling capacitors of relatively large sizes. Certain areas of the HLBS structure within the partial ring that exhibit a unique characteristic are identified. Decoupling capacitors of the relatively large sizes are disposed in the certain areas. A remainder of the areas of the HLBS structure are filled with engineering change order (ECO) books and decoupling capacitors of relatively small sizes.

Abstract: Methods and apparatus for visualizing a surface covering on at least a portion of a surface in an image of a scene. The method comprises identifying, using at least one computer processor, a surface plane from the image of the scene, determining, for each pixel of a plurality of pixels corresponding to the surface plane, whether the pixel corresponds to at least a portion of the surface in the scene, and generating an updated image of the scene by overlaying on the surface plane, a visualization of a plurality of surface covering tiles on pixels along the surface plane determined to correspond to at least a portion of the surface in the scene.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.

Abstract: A radio-frequency (RF) coil for use in a low-field magnetic resonance imaging system and methods of making the same are provided. The RF coil may include a conductor arranged on a substrate in an arrangement such that symmetry in the arrangement cancels at least a portion of a common mode voltage when a current is passed through the conductor. The RF coil may be included in a magnetic resonance imaging (MRI) system for imaging a patient having at least one B0 magnet for generating a B0 magnetic field.

Abstract: An apparatus and a method for optimized calculation of 2D sub-holograms for object points of a three-dimensional scene and a pipeline for real-time calculation of holograms are provided. The invention shortens the calculation time of a hologram for representing a three-dimensional scene and/or to reduce the calculation complexity of such a hologram. This is achieved by a 2D sub-hologram of an object point, which has image elements of the spatial light modulator, comprises a half 1D sub-hologram, where the radius of each image element is determined and each image element of the 2D sub-hologram is fixedly assigned to at least one image element of the half 1D sub-hologram with identical or similar radius by way of an electronic circuit, by a method for encoding a hologram, and by a pipeline on the basis of FPGA and/or ASIC.

Abstract: An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.

Abstract: Various embodiments provide a system for performing operations that comprise accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a present timing offset of the clock tree to a target timing offset. In response, a group of clock sinks to be adjusted are identified to satisfy the request. The clock tree is then modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to update the clock tree. An indication is provided that the updated clock tree has been modified and complies with the target timing offset.

Abstract: The disclosed systems, structures, and methods are directed to an antenna comprising: a plurality of Composite Right Left Handed (CRLH) magneto-electric unit-cell based structures, each CRLH magneto-electric unit-cell based structure comprising: a ground electrode for common electrical contacts, a first coaxial connector and a second coaxial connector, a first ground surface and a second ground surface, the first ground surface connected to a second end of the first coaxial connector and the second ground surface connected to a second end of the second coaxial connector, a coaxial line included in the second coaxial connector, a microstrip feed line connected to the coaxial line and electromagnetically coupled with the first and the second ground surfaces, and a first non-resonant meta-surface patch and a second non-resonant meta-surface patch, each of the first and second non-resonant meta-surface patches placed above a series-capacitor gap between the first ground surface and the second ground surface.

Abstract: A method establishes an improved clock topology for a computation system, where the computation system is a network of nodes, and where multiple nodes are capable of being a grandmaster clock source. The method includes sequentially selecting each selectable node as an acting grandmaster node, the acting grandmaster node sending announce messages, each node with a determinative communication requirement extracting topology information from the announce messages. The above steps are repeated with another node until each selectable node has been an acting grandmaster. The method then includes selecting the clock source based on the best clock topology for the set of nodes with determinative communication requirements.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor.

Abstract: An information processing apparatus includes a receiving unit configured to receive input of shape data of a device that is a subject of a thermal analysis, a selection unit configured to select a modeling method for a component included in the device, a generation unit configured to generate a thermal network model of the component from the shape data based on the selected modeling method, an addition unit configured to add a node and an element to the thermal network model, a setting unit configured to set a boundary condition to the thermal network model, a determination unit configured to determine a physical quantity of the thermal network model, and a display unit configured to display the determined physical quantity.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Abstract: Pattern matching using anchors during integrated circuit (IC) verification is disclosed. According to one embodiment, a method includes obtaining match time estimates associated with pattern anchors of different anchor types for an IC pattern, generating revised match time estimates based on a target IC layout, and then selecting the pattern anchor associated with the shortest revised match time estimate. Then, target anchors of the same anchor type as the selected pattern anchor are generated for the target IC layout, and the target IC layout is searched for the IC pattern using the selected pattern anchor and the target anchors.

Abstract: Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.

Abstract: Graph partitioning for massive scale graphs is described, such as for graphs having vertices representing people and edges representing connections between people in a social networking system; or for graphs where the vertices represent other items and the edges represent relationships between the items. In various embodiments a graph data allocator receives a graph vertex and its edges and allocates the vertex to one of a plurality of clusters each associated with one or more computing devices. In various embodiments the allocation is made by optimizing an objective function which takes into account both a cost of edges between clusters and a cost related to sizes of the clusters. In some examples the cost related to sizes of the clusters comprises a convex function applied to each of the cluster sizes. In examples, computations on the graph data are carried out with reduced runtimes and communications cost.

Abstract: A system and method for providing electrical circuit design using cells with metal lines are described herein. According to one embodiment, a method includes instantiating a first parameterized cell (PCELL) into a first region of a row of an electrical circuit design. The first PCELL includes field effect transistor (FET) data representing a FET structure having a horizontal dimension and first metal track data representing a first set of adjustable parallel metal line segments extending along the horizontal dimension of the FET structure. The method also includes instantiating a second PCELL into a second region of the row adjacent to the first region. The second PCELL includes second metal track data representing a second set of adjustable parallel metal line segments. The method further includes connecting the first set of adjustable parallel metal line segments to the second set of adjustable parallel metal line segments and eliminating a connectivity short.

Abstract: A distributed system may implement evaluating placement configurations for distributed resource placement. Placement requests for a partition of a distributed resource may be received. An evaluation of prospective placement configurations of the distributed resource is performed that locates the partition at different resource hosts. In some embodiments, placement configurations may be analyzed with respect to infrastructure zone locality. Multiple infrastructure zone localities may be analyzed and combined to evaluate prospective placement configurations. Prospective placement configurations may be analyzed with respect to other criteria, such as resource host utilization data. Based, at least in part, on the evaluation of the prospective placement, a resource host is identified for placing the partition.

Abstract: Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

Abstract: A method includes obtaining a feature vector for each cell in a group of cells. The feature vector for a cell includes a score value for each feature in a set of features selected for characterizing the group of cells. The method includes clustering cells in the group into a selected number of clusters, based on distances between end points of feature vectors of the cells. The method includes generating a list of ranked critical cells in the selected number of clusters based on a list of prioritized features associated with the set of features. The method includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Abstract: A method of making a semiconductor device includes receiving a first layout of a device in a first technology node, wherein the first layout comprises a plurality of first conductive patterns spaced along a first direction and a plurality of first interconnect patterns connecting at least two of the plurality of first conductive patterns. The method includes identifying a plurality of second conductive patterns from the plurality of first conductive patterns according to a second technology node different from the first technology node. The method includes determining a scaling factor for the first layout in the first direction based on the plurality of first conductive patterns and the plurality of second conductive patterns. The method includes adjusting the plurality of first interconnect patterns along the first direction using the scaling factor to determine a plurality of second interconnect patterns connecting at least two of the plurality of second conductive patterns.

Abstract: A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration; selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.

Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.

Abstract: This application discloses a display, a display apparatus, and a ground resistor adjustment method. The display includes: a drive circuit of a display panel, an integrated end circuit, and an adjustable resistance circuit, where the adjustable resistance circuit controls and adjusts a resistance value between the drive circuit of the display panel and the integrated end circuit.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: Methods and apparatus for visualizing a surface covering on at least a portion of a surface in an image of a scene. The method comprises identifying, using at least one computer processor, a surface plane from the image of the scene, determining, for each pixel of a plurality of pixels corresponding to the surface plane, whether the pixel corresponds to at least a portion of the surface in the scene, and generating an updated image of the scene by overlaying on the surface plane, a visualization of a plurality of surface covering tiles on pixels along the surface plane determined to correspond to at least a portion of the surface in the scene.

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a logic strata, the logic strata including logic, and to a memory strata, the memory strata including memory; then performing a first placement of the memory strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, where the 3D Integrated Circuit includes through silicon vias for connection between the logic strata and the memory strata; and performing a second placement of the logic strata based on the first placement, where the memory includes a first memory array, where the logic includes a first logic circuit controlling the first memory array, where the first placement includes placement of the first memory array, and the second placement includes placement of the first logic circuit based on the placement of the first memory array.

Abstract: There are provided system and method of examining a semiconductor specimen. The method comprises: upon obtaining a Deep Neural Network (DNN) trained for a given examination-related application within a semiconductor fabrication process, processing together one or more fabrication process (FP) images using the obtained trained DNN, wherein the DNN is trained using a training set comprising ground truth data specific for the given application; and obtaining examination-related data specific for the given application and characterizing at least one of the processed one or more FP images. The examination-related application can be, for example, classifying at least one defect presented by at least one FP image, segmenting the at least one FP image, detecting defects in the specimen presented by the at least one FP image, registering between at least two FP images, regression application enabling reconstructing the at least one FP image in correspondence with different examination modality, etc.

Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

Abstract: A system includes a memory that stores computer executable components, and a processor executes the computer executable components stored in the memory. The computer executable components comprise: an assessment component that determines locations for mode suppression structures on a coplanar waveguide of a quantum chip having qubits; a simulation component that simulates performance of the quantum chip based on a subset of the locations for the mode suppression structures and parameters of the quantum chip, and generates a mode suppression structures placement model. A template component generates a template of specific coordinates for placement of a subset of the mode suppression structures on the quantum chip based on the mode suppression structures placement model; and a driver component employs the template to drive an auto-bonder to install the subset of the mode suppression structures on the quantum chip at the specific coordinates.

Abstract: A computing device for receiving a design problem statement describing a design problem in a controlled natural language (CNL) that defines permitted lexicons and syntax structures. The design problem statement is processed using the CNL lexicons and syntax structures to produce a job description executable by a design application for generating a design solution for the design problem statement. An improved CNL user interface that assists users to produce valid design problem statements that are CNL-compliant. The CNL user interface receives user-selectable terms that are compliant with the CNL lexicons and generates candidate problem statements that are compliant with CNL syntax structures and receives a selection of a candidate problem statement that is added to the design problem statement. A graphical user interface may display a graphical representation of a design problem statement that can be directly modified. A dialogue-based design process to explore possible design intentions and design solutions.

Abstract: An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.

Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.

Abstract: An energy management apparatus according to an embodiment of the present invention is designed to provide a method for visually displaying an energy operation status in various manners so as to facilitate energy analysis, and may comprise: a measurement unit for acquiring power state information of at least one energy apparatus constituting a system to which the energy management apparatus belongs; a control unit for analyzing an energy operation status on the basis of the acquired power state information; and a display unit for displaying the analyzed energy operation status in the form of a three-dimensional energy graph, wherein each of the X-, Y-, and Z-axes of the three-dimensional energy graph is mapped to one of time, an energy apparatus, and an object of energy analysis.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A method of designing a template pattern used for imprint lithography, includes generating data of a dummy template pattern to be formed in a third area between first and second areas of a template based on data of a design pattern of the template, the data of the dummy template pattern being generated so that a third surface area ratio showing a ratio of a surface area of the third area to an area of the third area is set smaller than a first surface area ratio showing a ratio of a surface area of the first area to an area of the first area and larger than a second surface area ratio showing a ratio of a surface area of the second area to an area of the second area.