Constraint-based Patents (Class 716/122)
  • Patent number: 10417367
    Abstract: Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: September 17, 2019
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Ke Wang, Kevin Skadron, Mircea R. Stan, Runjie Zhang
  • Patent number: 10417375
    Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy
  • Patent number: 10394994
    Abstract: A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Iris Maria Leefken, Silke Penth, Michael Stetter, Tobias T. Werner
  • Patent number: 10394995
    Abstract: Disclosed herein are embodiments of systems, methods, and products that generate two dimensional chains of layout devices, by retrieving the schematic orientation of schematic devices in a symbolic view, and abutting the layout devices based on the schematic orientation such that the two dimensional chains of the layout devices maintain the schematic orientation. More specifically, EDA systems and methods disclosed herein may separate the layout devices into different sets, wherein each set may contain a particular type of layout devices. For example, a first set may contain photonic waveguides and a second set may contain radio frequency (RF) transmission lines. For each set of layout devices, the EDA systems and methods deterministically and iteratively traverse through the layout devices, abutting the devices using the schematic orientation, and creating one or more two dimensional chains of the layout devices.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: August 27, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Mallon, Arnold Ginetti
  • Patent number: 10394676
    Abstract: Provided is a generation device including: a test vector generation unit for selecting, for each of parameters to be included in a test vector, one value from among possible values for the parameter to generate test vectors whose combinations of values are different from each other; an extraction unit for extracting, as partial sequences each including one or more test vectors, portions of a series including the test vectors output by the test vector generation unit; and a test sequence generation unit for generating a test sequence based on the extracted partial sequences.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shunichi Amano, Hisashi Miyashita, Hideki Tai
  • Patent number: 10394996
    Abstract: Via array placement on a printed circuit board (PCB) outline including receiving, by a PCB design module, via array data from a user; generating, by the PCB design module, a via array based on the via array data from the user, including placing the via array on the PCB outline, wherein the via array comprises a grid of vias; detecting, by the PCB design module, that a first PCB element has been placed on top of a first portion of the via array on the PCB outline; removing, by the PCB design module, the first portion of the via array under the first PCB element, wherein a second portion of the via array remains on the PCB outline after removing the first portion of the via array; and generating, by the PCB design module, a PCB design document using the PCB outline and the second portion of the via array.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10387607
    Abstract: Techniques are disclosed to determine the temperature-dependent insertion loss and propagation delay of traces in a printed circuit board design. For example, an example method includes determining a first temperature at a first portion of a trace of a PCB design based on a thermal map of the PCB design. The method further includes determining a second temperature at a second portion of the trace based on the thermal map. The method further includes calculating a temperature-dependent property of the PCB at the first portion based on the first temperature. The method further includes calculating the temperature-dependent property of the PCB at the second portion based on the second temperature. The method further includes calculating at least one of a signal loss and propagation delay on the trace based on the temperature-dependent property of the PCB at the first portion and the second portion.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 20, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Soumya De, Yaochao Yang
  • Patent number: 10372861
    Abstract: A method of macro placement includes partitioning an entire region of a semiconductor chip into sub-regions; determining a packing sequence of a plurality of movable macros in the sub-region; extracting search points of a plurality of placed blocks in the sub-region with respect to one of the movable macros; determining a feasible region associated with the search point; packing said movable macro in the feasible region; evaluating a legalizing cost function; and determining whether a value of the evaluated legalizing cost function is less than a predetermined threshold value.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 6, 2019
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Chia-Min Lin, Te-Wei Peng, Fa-Ta Chen, Chia-Ching Huang
  • Patent number: 10346942
    Abstract: A computer implemented method for event detection in real-time graphic applications, comprising: receiving an indication for a method selected from a group of methods for identifying an action-requiring element comprised in a frame rendered during a game; activating the method for recognizing whether the element is comprised in a frame to be rendered; and responsive to the element being comprised in the frame, taking the action, wherein the method is a least resource-consuming or least intrusive method of the group of methods applicable for the frame.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: July 9, 2019
    Assignee: Electronic Arts Inc.
    Inventor: Yuval Sarna
  • Patent number: 10339252
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Patent number: 10331805
    Abstract: A computer-implemented method for determining boundary offsets in a photovoltaic (PV) system based on shadow simulations is implemented by a design automation computer system in communication with a memory. The method includes identifying a set of obstructions wherein the set of obstructions includes a set of obstruction elevations and a set of obstruction offsets, simulating a set of shadow effects using a first coarse shadow algorithm based on the set of obstructions, refining the set of shadow effects using a second fine shadow algorithm based on the set of obstructions and the set of shadow effects, and defining a plurality of boundary of boundary offsets based on the refined set of shadow effects.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: June 25, 2019
    Assignee: FTC Solar, Inc.
    Inventors: Andrew Joseph Morse, Nagendra Srinivas Cherukupalli, Ravi Ranganathan, Krishnan Ramagopal
  • Patent number: 10332798
    Abstract: A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a substrate, wherein configuring the layout pattern includes: arranging pre-conductive patterns and post-conductive patterns for a first logic cell, a second logic cell, and a third logic cell; rearranging the pre-conductive patterns and the post-conductive patterns so that two conductive patterns that are adjacent to a boundary between two adjacent logic cells from among the first logic cell, the second logic cell, and the third logic cell are formed by different photolithography processes; and arranging conductive patterns for a dummy cell arranged between the second logic cell and the third logic cell.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Young Kim, JinTae Kim, Jae-Woo Seo, Dong-yeon Heo
  • Patent number: 10318685
    Abstract: A method of establishing regions for placing cells of an integrated circuit (IC) includes, in part, assigning a precedence value to each of a multitude of constraint regions of the IC, and forming a multitude regions each associated with one of the constraint regions. The region associated with each constraint region is formed in accordance with the precedence value of its associated constraint region and the precedence values associated with any other constraint regions overlapping the first constraint region. Each region in a subset of the constraint regions is further defined in accordance with the region's transparency/opacity attribute.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Mark William Bales, David L. Peart, Jeffrey Jude Loescher
  • Patent number: 10311201
    Abstract: Methods and a computer program product are described for placing, by an electronic design tool, a first alignment key shape of a first cell and a second alignment key shape of a second cell positioned on a common edge where the first cell abuts the second cell in a physical layout design. An abutting alignment key shape is formed by placement of the first alignment key shape and the second alignment key shape in the physical layout design. The abutting alignment key shape is checked by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined shape of a correct size. The disallowed cell placement is corrected, by a designer, through substitution of an allowed cell placement to provide a corrected physical layout design for manufacture of the IC.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nigel Chan, Germain Bossu
  • Patent number: 10311814
    Abstract: The disclosure provides an array substrate, a display panel, a display device and a display method. The array substrate comprises a display region provided with a plurality of data lines therein and a wiring region around the display region and provided with a plurality of leading wires therein. The plurality of leading wires are connected with the plurality of data lines respectively in a one-to-one correspondence way. The plurality of leading wires comprise a plurality of first leading wires and a plurality of second leading wires insulatively arranged in different layers. The plurality of first leading wires and the plurality of second leading wires comprise at least one pair of overlapped first and second leading wires to which data signals having the same polarity are input.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: June 4, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhifu Dong, Hongmin Li, Ping Song, Liqing Liao
  • Patent number: 10298506
    Abstract: A data traffic scheduling method that includes selecting, using a network controller, plurality of flows that traverses a network node, generating an augmented graph based on a flow rate of the plurality of flows and link capacities of the network node, computing a flow schedule for the flow using the augmented graph to minimize delay or delay variance of the flows, and outputting the flow schedule. A data traffic scheduling method that includes obtaining, using a network controller, a network topology for a network, generating an augmented graph based on the network topology, converting the augmented graph to a mixed-integer linear program, scheduling a flow in the network using the mixed-integer linear program to minimize delay or delay variance of the flow, and outputting a flow schedule.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 21, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: William McCormick, Tao Wan, Yufei Wang
  • Patent number: 10268796
    Abstract: A method performed by at least one processor includes selecting a pin in a cell, determining a type of the pin, assigning a first pin access and a second pin access of the pin to a same patterning group at different patterning tracks when the pin is determined to be a cross-track pin, determining whether a pin access of a first pin and a pin access of a second pin disposed adjacent to the first pin in the cell are on a same patterning track, separating the first pin and the second pin from each other by a first predetermined distance when the pin accesses are determined to not be on a same patterning track, and separating the first pin and the second pin from each other by a second predetermined distance when the pin accesses are determined to be on a same patterning track.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Li-Chun Tien, Shun-Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang
  • Patent number: 10268793
    Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Wu-An Kuo
  • Patent number: 10262097
    Abstract: A method for optimizing manufacturability of standard cells includes generating random contexts for the standard cells, inserting vias into the standard cells, and performing a lithography verification on the standard cells after the vias have been inserted. The method enables early detection and resolution of potential hot spots on standard cell pin connections and reduction of hot spots that are introduced by the router at the chip level. The early detection and reduction of hot spots shortens the cycle time of a standard-cell based design.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 16, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Lin Hong, Xue Li
  • Patent number: 10255401
    Abstract: A method according to one embodiment includes receiving a printed circuit board design in a memory; generating, using a processor, multiple schematic windows and multiple layout windows of the printed circuit board design; outputting a layout window depicting an entire layout of the printed circuit board design, receiving a user selection of a sub-portion of the printed circuit board design from the entire layout of the printed circuit board design, generating a first of multiple layout windows and a first of multiple schematic windows upon receiving the user selection, and outputting the multiple schematic windows of the printed circuit board design simultaneously with outputting the multiple layout windows of the printed circuit board design. The first of the schematic windows is paired with the first of the layout windows, the paired windows depicting representations of the selected sub-portion of the printed circuit board design.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: April 9, 2019
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventor: Jian Meng
  • Patent number: 10223081
    Abstract: Systems and methods which implement workflows for providing reconfigurable processor core algorithms operable with associated capabilities using description files, thereby facilitating the development and generation of instruction sets for use with reconfigurable processors, are shown. Embodiments implement a multistage workflow in which program code is parsed into custom instructions and corresponding capability descriptions for generating reconfigurable processor loadable instruction sets. The multistage workflow of embodiments includes a hybrid threading complier operable to compile input program code into custom instructions using a hardware timing agnostic approach. A timing manager of the multistage workflow of embodiments utilizes capabilities information provided in association with the custom instructions generated by the hybrid threading complier to impose hardware timing on the custom instructions.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tony Brewer
  • Patent number: 10210301
    Abstract: A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 19, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Ankur Chavhan, Devesh Jain, Behnam Farhat, Andrey Freidlin, Sundararajan Shanmugam, Susan Zueqing Zhang
  • Patent number: 10198834
    Abstract: Graph partitioning for massive scale graphs is described, such as for graphs having vertices representing people and edges representing connections between people in a social networking system; or for graphs where the vertices represent other items and the edges represent relationships between the items. In various embodiments a graph data allocator receives a graph vertex and its edges and allocates the vertex to one of a plurality of clusters each associated with one or more computing devices. In various embodiments the allocation is made by optimizing an objective function which takes into account both a cost of edges between clusters and a cost related to sizes of the clusters. In some examples the cost related to sizes of the clusters comprises a convex function applied to each of the cluster sizes. In examples, computations on the graph data are carried out with reduced runtimes and communications cost.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Milan Vojnovic, Charalampos E. Tsourakakis, Christos Gkantsidis, Bo{hacek over (z)}idar Radunović
  • Patent number: 10162931
    Abstract: A method of forming a serpentine resistor includes: setting a total length of a schematic resistor to make the schematic resistor to have a first resistance according to a sheet resistance; forming, by using a processor, a serpentine layer corresponding to the schematic resistor, forming, by using the processor, a dummy layer over a portion of the serpentine layer to form a modified serpentine layer, measuring, by using the processor, a modified length of the modified serpentine layer, and comparing, by using the processor, the total length and the modified length to generate a comparison result.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Wen-Shun Lo, Hsin-Li Cheng
  • Patent number: 10162909
    Abstract: In a three-dimensional model design assistance system in which design rules are registered in advance, it is difficult to manually input all of an enormous number of device placement rules including the distances and directions between respective devices in a design. Information relating to the relative distances and relative directions between respective devices included in performance CAD data is extracted. With respect to each of the extracted relative distances and relative directions in a plurality of cases, a correlation with a performance requirement specification value, and a placement priority are calculated and held as device placement rules. At design time, requirement specifications are inputted, accessory devices are determined, and thereafter the devices are placed according to placement priorities on CAD on the basis of the device placement rules.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: December 25, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Reiko Inoue, Takaharu Matsui, Kenji Okuda
  • Patent number: 10162927
    Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shih-Ying Liu, Chin-Hsiung Hsu, Chi-Yuan Liu, Chun-Chih Yang, Chao-Neng Huang
  • Patent number: 10157251
    Abstract: A method includes following operations. First circuit cells are partitioned into a first frame of a first tier and the first frame of a second tier. The first frame is divided into second frames according to a step size. The first circuit cells between the second frames of the first tier and the second tier are adjusted. The first tier and the second tier, to which the adjusted first circuit cells are assigned, are merged to generate data indicating a layout design, for fabrication of the circuit cells.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Ou, Chun-Chen Chen, Sheng-Hsiung Chen
  • Patent number: 10146516
    Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: December 4, 2018
    Assignee: Global Supercomputing Corporation
    Inventors: Kemal Ebcioglu, Emre Kultursay
  • Patent number: 10108769
    Abstract: Designing circuits can include, within a circuit design, detecting, using a processor, a high fan-out net having loads with a same timing requirement, wherein the circuit design is technology specific for a target integrated circuit (IC), determining, using the processor, a region having a predetermined shape and an area sized to fit loads of the high fan-out net within the region on the target IC, and determining, using the processor, a delay of the high fan-out net based upon a distance from a center of the region to an edge of the region. Designing circuits can also include assigning, using the processor, the delay to the high fan-out net.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: October 23, 2018
    Assignee: XILINX, INC.
    Inventors: Yau-Tsun S. Li, Grigor S. Gasparyan
  • Patent number: 10019474
    Abstract: A computer-implemented method for ranking design parameter significance includes a computer receiving an input dataset representative of a physical object. This input dataset includes a baseline parameters and associated probabilities. The computer also receives performance requirements. For each respective baseline parameter, the computer performs an analysis process. During this analysis process, a range of parameter values are selected for the respective baseline parameter based on its corresponding probability distribution. The range of parameter values are segmented into parameter subsets and multiple instances of a simulation are executed using the performance requirements to yield snapshots. A Proper Orthogonal Decomposition (POD) basis is derived using the snapshots. A sensitivity analysis is performed based on the POD basis to yield a sensitivity measurement representative of an effect of variation of the respective parameter on the performance requirements.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 10, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventors: Lucia Mirabella, Sanjeev Srivastava, Erhan Arisoy, Suraj Ravi Musuvathy
  • Patent number: 10007878
    Abstract: An operation plan decision method includes deriving an feasible solution by using a constraint violation minimization model, updating candidates for an optimum solution and adding the updated candidates to a candidate list by taking the derived feasible solution, as an initial value of a candidate for the optimum solution, and by using a time cross-section division model that is obtained by dividing an optimization model for each time cross-section, and selecting the optimum solution from the candidate list to which the updated candidates are added.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 26, 2018
    Assignee: Yokogawa Electric Corporation
    Inventors: Mika Kawata, Kenichi Ohara, Mitsunori Fukuzawa
  • Patent number: 9990460
    Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot mask and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Ting Huang, Shuo-Yen Chou, Ru-Gun Liu
  • Patent number: 9984192
    Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: 9977854
    Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 22, 2018
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Omid Rowhani, Ioan Cordos, Kerry Hamel, Donald Clay
  • Patent number: 9940424
    Abstract: The present disclosure is directed to systems and methods for a minimum-implant-area (MIA) aware detailed placement. In embodiments, the present disclosure clusters a violation cell with the cells having a same threshold voltage (Vt) and determines an optimal region for a cluster to minimize the wire-length. In further embodiments, an MIA-aware cell flipping technique minimizes a design area while satisfying the MIA constraint.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yao-Wen Chang, Kai-Han Tseng
  • Patent number: 9928331
    Abstract: A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 27, 2018
    Assignee: NXP USA, Inc.
    Inventors: Vladimir Pavlovich Rozenfeld, Robert L. Maziasz, Mikhail Anatolievich Sotnikov
  • Patent number: 9922161
    Abstract: Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: March 20, 2018
    Assignee: The Regents of the University of California
    Inventors: Andrew B. Kahng, Tuck Boon Chan
  • Patent number: 9904755
    Abstract: In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints is generated. Feasibility of the set of layout constraints is checked, which then is provided to a Linear Program solver for generating an output circuit layout.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 27, 2018
    Assignee: Synopsys, Inc.
    Inventors: Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir Husain Batterywala
  • Patent number: 9904753
    Abstract: A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: February 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Moo Kim, Seung Weon Paek
  • Patent number: 9881120
    Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 30, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Steven Durrill, Taranjit Singh Kukal
  • Patent number: 9846755
    Abstract: According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Zhang Kuo, Lee-Chung Lu, Cheng-Chung Lin, Li-Chun Tien, Sang-Hoo Dhong, Ta-Pen Guo
  • Patent number: 9792396
    Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 17, 2017
    Assignee: SYNOPSYS, INC.
    Inventor: Anand Arunachalam
  • Patent number: 9792398
    Abstract: A system provides placement of components for an integrated circuit having a plurality of flip-flops. The system clusters the plurality of flip-flops into a plurality of clusters and relocates one or more of the flip-flops in response to overlapping placement locations. The clustering includes using a K-means algorithm to assign a flip-flop to a cluster while adding weight to each cluster based on its current size.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: October 17, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Yue Xu, Manoj Kumar Ragupathy, Yu-Yen Mo, Dean Wu, Gang Wu
  • Patent number: 9785881
    Abstract: A method and system for producing electronic label are disclosed. The electronic label includes a first substrate and a second substrate. Layout information associated with the electronic label is developed. The layout information is automatically processed to develop print commands, circuit layout information, and component placement information therefrom. Information is printed on the first substrate in accordance with the print information and a conductive trace is deposited on the second substrate in accordance with circuit layout information. Components are placed on the deposited conductive trace in accordance with the component placement information.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 10, 2017
    Assignee: R.R. Donnelley & Sons Company
    Inventors: Theodore F. Cyman, Jr., Nancy A. Lee, Ali K. Cameron, Eric V. Palmer
  • Patent number: 9785739
    Abstract: The present disclosure relates to a system and method for fluid parameterized cell (Pcell) evaluation. Embodiments may include displaying a fluid Pcell in a first format. Embodiments may further include identifying a first state in a fluid Pcell evaluation code. In some embodiments, the first state may indicate that alterations are being made to the fluid Pcell. Embodiments may also include displaying instances of the fluid Pcell in a second format based upon, at least in part, identifying the first state in the fluid Pcell evaluation code. Embodiments may further include identifying a second state in the fluid Pcell evaluation code. In some embodiments, the second state may indicate the completion of the alterations to the fluid Pcell. Embodiments may also include displaying a final instance of the fluid Pcell in the first format based upon, at least in part, identifying the second state in the fluid Pcell evaluation code.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 10, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Reenee Tayal, Vishal Agarwal, Mayank Sharma, Farhat Alam Khan
  • Patent number: 9767242
    Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: September 19, 2017
    Assignee: Pulsic Limited
    Inventor: Graham Balsdon
  • Patent number: 9754070
    Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: September 5, 2017
    Assignee: SYNOPSYS, INC.
    Inventor: Russell B. Segal
  • Patent number: 9754072
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 5, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami
  • Patent number: 9747405
    Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 29, 2017
    Assignee: SYNOPSYS, INC.
    Inventor: Philip H. Tai
  • Patent number: 9740810
    Abstract: A system and method for designing an electrical component comprises a model extraction engine configured to generate a model based on a set of parameters, a simulator configured to simulate the generated model and measure performance, a rule-set usable to determine changes to the set of parameters, and an inference engine configured to change salience values of expert rules included in the rule set. The salience value determines when and if an expert rule is used to change the set of parameters. One or more microprocessors are configured to determine design characteristics of the electrical component by iteratively performing, until measured performance is within tolerance, the steps of generating a model based on an updated version of the set of parameters, simulating the generated model, measuring performance of the generated model, and updating the set of parameters using the rule-set if the measured performance is not within the predefined tolerance.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 22, 2017
    Assignee: HELIC S.A.
    Inventors: Sotirios Bantas, Paschalis Zampoukis