Abstract: In a method for legalizing a multi-patterning integrated circuit layout including a plurality of islands, a set of multi-patterning constraints is generated on the basis of multi-patterning conflicts identified between the plurality of islands. Based on general design rule constraints and the multi-patterning constraints a combined set of layout constraints is generated. Feasibility of the set of layout constraints is checked, which then is provided to a Linear Program solver for generating an output circuit layout.

Abstract: A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.

Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

Abstract: According to an embodiment, a method for cell placement in a semiconductor layout is provided. The method includes: providing a first cell having two sides, each side configured as at least one of a source side and a drain side; providing a place-and-route boundary (prBoundary) of the first cell based on the configuration of the two sides of the first cell; providing a second cell having two sides, each side configured as at least one of a source side and a drain side; providing a prBoundary of the second cell based on the configuration of the two sides of the second cell; and placing the first cell and the second cell based on the prBoundary of the first cell and the prBoundary of the second cell.

Abstract: A system provides placement of components for an integrated circuit having a plurality of flip-flops. The system clusters the plurality of flip-flops into a plurality of clusters and relocates one or more of the flip-flops in response to overlapping placement locations. The clustering includes using a K-means algorithm to assign a flip-flop to a cluster while adding weight to each cluster based on its current size.

Abstract: Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.

Abstract: A method and system for producing electronic label are disclosed. The electronic label includes a first substrate and a second substrate. Layout information associated with the electronic label is developed. The layout information is automatically processed to develop print commands, circuit layout information, and component placement information therefrom. Information is printed on the first substrate in accordance with the print information and a conductive trace is deposited on the second substrate in accordance with circuit layout information. Components are placed on the deposited conductive trace in accordance with the component placement information.

Abstract: The present disclosure relates to a system and method for fluid parameterized cell (Pcell) evaluation. Embodiments may include displaying a fluid Pcell in a first format. Embodiments may further include identifying a first state in a fluid Pcell evaluation code. In some embodiments, the first state may indicate that alterations are being made to the fluid Pcell. Embodiments may also include displaying instances of the fluid Pcell in a second format based upon, at least in part, identifying the first state in the fluid Pcell evaluation code. Embodiments may further include identifying a second state in the fluid Pcell evaluation code. In some embodiments, the second state may indicate the completion of the alterations to the fluid Pcell. Embodiments may also include displaying a final instance of the fluid Pcell in the first format based upon, at least in part, identifying the second state in the fluid Pcell evaluation code.

Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.

Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Abstract: Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.

Abstract: A system and method for designing an electrical component comprises a model extraction engine configured to generate a model based on a set of parameters, a simulator configured to simulate the generated model and measure performance, a rule-set usable to determine changes to the set of parameters, and an inference engine configured to change salience values of expert rules included in the rule set. The salience value determines when and if an expert rule is used to change the set of parameters. One or more microprocessors are configured to determine design characteristics of the electrical component by iteratively performing, until measured performance is within tolerance, the steps of generating a model based on an updated version of the set of parameters, simulating the generated model, measuring performance of the generated model, and updating the set of parameters using the rule-set if the measured performance is not within the predefined tolerance.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one TS-short-related failure mode.

Abstract: An apparatuses includes a processor, a storage unit, and a communication unit to access the storage unit without intermediary of the processor and to access a second apparatus of the plurality of information processing apparatuses via a communication unit of the second apparatus. The communication unit of a first apparatus of the plurality of information processing apparatuses executes at least one of a process of storing redundant data which is generated by making redundant data stored in the storage unit of the first apparatus in the storage unit of the second apparatus via the communication unit of the second apparatus, and a process of acquiring redundant data which is generated by making redundant data stored in the storage unit of the second apparatus via the communication unit of the second apparatus, and storing the acquired data in the storage unit of the first apparatus.

Abstract: Embodiments of the present invention provide efficient systems and methods for creating an optimal set of partitions across replica blocks using two checkpoints during the design process. The two checkpoints group a set of macros according to a timing constraint and a location proximity to the other macros. Clustering of the macros is iteratively performed until a distance parameter exceeds a pre-defined threshold.

Abstract: Embodiments of the present invention provide efficient systems and methods for creating an optimal set of partitions across replica blocks using two checkpoints during the design process. The two checkpoints group a set of macros according to a timing constraint and a location proximity to the other macros. Clustering of the macros is iteratively performed until a distance parameter exceeds a pre-defined threshold.

Abstract: An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

Abstract: A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.

Abstract: A method of manufacturing an integrated circuit (IC) includes: receiving a target layout of the IC, decomposing the target layout into a plurality of sub-layouts for a multiple patterning process, identifying re-locatable pattern edges in the sub-layouts, and relocating the edges to improve manufacturability of the IC. In an embodiment, relocating the edges includes: choosing an evaluation index based on a target manufacturing process, moving one or more of the edges, calculating a score of manufacturability based on the evaluation index, and repeating the moving and the calculating until the score meets a threshold.

Abstract: Embodiments of the present invention provide a system and method for SAV (self-aligned via) retargeting. The SAV (Self Aligned Vias) process aids in the alignment of the vias with the metal above (Mx+1) during the dual damascene process. The retargeting enables an increase the area of the via during photolithography without affecting the final critical dimension. SAV retargeting is the via retargeting during the mask tape-out to reshape the via and protect it against possible via-to-Mx+1 overlay error. With embodiments of the present invention, the via edge movement is linked to the actual driver behind the SAV retargeting, which is maintaining a minimum area coverage with the metal above at extreme overlay error conditions. Accordingly, for a via edge to get SAV retargeted, a calculation is first made to determine how much its opposite via edge is subject to be cut during SAV due to overlay error.

Abstract: A method, executed by a computer, for routing a circuit includes receiving a logic structure for a circuit, retrieving a logic template, determining whether the logic structure for the circuit matches the logic template, and routing the circuit using a routing recipe corresponding to the logic template in response to determining that the logic structure matches the logic template. A corresponding computer program product and computer system are also disclosed herein.

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Abstract: An integrated circuit (IC) design system includes a processor; and a non-transitory computer readable medium connected to the processor. The non-transitory computer readable medium is configured to store a configuration file containing a custom IC design parameter, to store a process design kit (PDK) containing a default IC design parameter, and to store instructions for execution by the processor. The instructions for execution by the process include instructions for extracting the custom IC design parameter from the configuration file. The instructions for execution by the process further include instructions for overwriting the default IC design parameter in the PDK with the custom IC design parameter. The instructions for execution by the process further include instructions for creating an IC design file using a module in the PDK using the custom IC design parameter in place of the default IC design parameter.

Abstract: Generating a target layout of an integrated circuit includes providing a source layout comprising one or more source pcells having one or more shapes; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit; for each shape of each source pcell, determining a corresponding target shape having a contour composed of edges with defined lengths, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, determining a corresponding edge of the corresponding target shape; for each edge, defining an edge length constraint for constraining the edge to have the length of the edge of the corresponding target shape; applying a legalization procedure to the source layout based on the connectivity constraints, the target design constraints, and the edge length constraints.

Abstract: A method, executed by a computer, for routing a circuit includes receiving a logic structure for a circuit, retrieving a logic template, determining whether the logic structure for the circuit matches the logic template, and routing the circuit using a routing recipe corresponding to the logic template in response to determining that the logic structure matches the logic template. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.

Abstract: This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.

Abstract: Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract: A method and system are provided for automatically enforcing a schematic layout strategy applied to a group of schematically represented circuit objects of an electronic circuit design. A circuit editing tool electronically renders schematic representations of circuit objects responsive to user input. A layout object acquisition unit coupled to the circuit editing tool actuates responsive to user input to selectively apply a predetermined layout strategy to at least one group of circuit objects for generating a corresponding layout object. The predetermined layout strategy includes a defining set of placement and interconnection routing schemes for the grouped circuit objects, one relative to the other. A layout object management unit coupled to the layout object acquisition unit and circuit editing tool adaptively reconfigures the layout object in accordance with the layout strategy thereof responsive to an editing operation being imposed on at least one circuit object within the layout object.

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

Abstract: A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

Abstract: A method and apparatus are provided to test an integrated circuit by identifying first and second components of an integrated circuit. The first and second components may share a relationship that causes the first and second components to generate a matching binary output in response to an input to the integrated circuit. A tap point may be selected within the integrated circuit. The tap point may be located at a point in the integrated circuit where an insertion of a bypass structure would affect the relationship. The bypass structure may be inserted at the tap point, and the bypass structure may be used to conduct a test of the integrated circuit.

Abstract: A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes.

Abstract: An information pushing device includes an information emitting device and a plurality of power generation members. The information pushing device is configured to push wireless information to mobile terminal equipments. Each power generation member includes a strip-shaped of electric generation film and two electrodes formed on two opposite surface of the electric generation film. The electric generation film is made from piezoelectric material, the power generation member comprises a first end and a second end opposite to the first end. The electrodes of the first end is electrically connected with the power supply unit, the second end swings under a cool or a heated airflow and produces charge. The charge is stored in the electrodes and provided to the information emitting device.

Abstract: This application relates to a method of routing circuit paths of an integrated circuit, IC. The IC comprises a plurality of circuit elements and a plurality of circuit paths connecting the circuit elements. The method comprises steps of: receiving a representation of the IC, comparing, based on the representation, the circuit elements of the IC against a set of reference circuit elements, classifying the circuit paths of the IC into a plurality of categories based on a result of the comparison, and routing the circuit paths of the IC in accordance with their respective categories. The application further relates to a computer-readable storage medium comprising a computer program that makes a computer perform the steps of said method when executed and to an apparatus for routing circuit paths of an IC.

Abstract: Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed.

Abstract: The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

Abstract: Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a first set of partitions for a circuit design, wherein each partition in the first set of partitions extends across the circuit design along a first direction. Next, the system can perform, in parallel, track assignment in the first direction on non-overlapping partitions in the first set of partitions. The system can then receive a second set of partitions for the circuit design, wherein each partition in the second set of partitions extends across the circuit design along a second direction which is different from the first direction. Next, the system can perform, in parallel, track assignment in the second direction on non-overlapping partitions in the second set of partitions. In some embodiments, each track assignment process being performed in parallel performs track assignment on a different net.

Abstract: Systems and techniques are described for solving an optimization problem using a constraints solver. A set of constraints that correspond to the optimization problem can be generated. Next, a set of upper bound constraints can be added to the set of constraints, wherein the set of upper bound constraints imposes an upper bound on one or more variables that are used in an objective function of the optimization problem. Next, the embodiments can iteratively perform the following set of operations on a computer: (a) solve the set of constraints using the constraints solver; (b) responsive to the constraints solver returning a solution, decrease the upper bound; and (c) responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increase the upper bound. The solution with the lowest upper bound value can be outputted as the optimal solution for the optimization problem.

Abstract: A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Abstract: Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.

Abstract: A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Abstract: Systems and techniques for circuit placement are described. An electronic design automation (EDA) tool can receive a netlist for the circuit design. Next, the EDA tool can represent the netlist as a graph, and perform fuzzy clustering on the graph to obtain a set of clusters and a set of probability values. The EDA tool can then partition and place the circuit design based on the set of clusters and the set of probability values. The EDA tool can then optimize the placed circuit design. During optimization the EDA tool can reassign at least one cell to a different layout bin based on the set of probability values.

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract: An integrated circuit design method includes extracting a custom IC design parameter from a configuration file using a design customization module (DCM) and creating an IC design file with a module in a processor design kit (PDK) using the custom IC design parameter.

Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.

Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm.