Abstract: Techniques are disclosed for storage resource resynchronization using pending IO requests.

Abstract: Computer-implemented method, apparatus and computer program for automatic analysis of a RDF, Resource Description Framework, dataset. The RDF dataset comprising a set of triples, wherein the RDF dataset is provided as an undirected graph comprising nodes and edges, wherein nodes represent entities and edges represent links between entities.

Abstract: Provided are a chip and a pin line-out design method therefor, which are applied to a BGA packaged chip. The method includes: according to pin position information and pin definition information of a chip, determining a number of circuit board layers required for pin line-out of the chip (S1); allocating line-out layers to pins of the chip in their respective circuit boards (S2); and according to a pin density and transmission line width requirement of the chip, determining a specification of a via hole in each circuit board for leading the pin of the chip out to the corresponding line-out layer, to perform a corresponding line-out design on the basis of the via hole (S3). It may be seen that the described unified pin line-out design for the BGA packaged chip is more refined, and the quality of the line-out design of the pins of the chip is ensured.

Abstract: A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.

Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model.

Abstract: A printed circuit board includes a spread weave of fibers having a first direction and a second direction with corresponding fibers spread more in the first direction than the second direction; and one or more pairs of traces on the spread weave of fibers, wherein the first direction has less differences in dielectric permittivity seen by each trace than the second direction, wherein the one or more pairs of traces are routed according to a routing design that includes one or more fixed regions on the spread weave of fibers, where routing of traces therein is restricted to linear, non-angled routed in the first direction.

Abstract: Techniques for an IC design include placing latches between a source and one or more sinks in the IC design, and performing an iterative process for maximizing slack on one or more input nets and one or more output nets for each of the latches, minimizing an absolute difference of the slack. The IC design includes optimizing routing for the latches and placing a clock gating latch in the IC design designated to control a LCB of LCBs. The IC design includes placing LCB logic in the IC design to control a required number of the LCBs, and placing a local clock buffer controller in the IC design in proximity to the positions of the latches.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing post-routing and post-placement physical synthesis optimizations. One of the methods includes receiving a circuit design of a multi-die integrated circuit (IC) device having a first die connected with a second die, wherein the circuit design specifies a respective initial component placement of each of a plurality of components on the first die and the second die. A first driver on the first die having a plurality of loads on the second die is selected. A transmit site is selected on the first die that reduces a distance between the first driver and a load of the plurality of loads on the second die. The circuit design is modified including moving the first driver to the selected transmit site on the first die.

Abstract: A method for partitioning for a hypergraph including a plurality of nodes into a plurality of bins includes assigning each node of the hypergraph to one of the plurality of bins to generate a candidate solution, and for each pair of nodes in the candidate solution, calculating a weighted covariance based on the bin assignment of each node of the pairs of nodes in the candidate solution. The assigning and the calculating are repeated to generate an accumulated weighted covariance for the pairs of nodes, from which a seed partition of the hypergraph is generated.

Abstract: An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.

Abstract: A processor performs vertex coloring for a graph based at least in part on the degree of each vertex of the graph and based at least in part with another coloring approach, such as comparison of random values assigned to the vertices. For each vertex in the graph, a processor determines whether the degree of the vertex is a local maximum; that is, whether the degree of the vertex is greater than the degree of each of its connected vertices. Each vertex having a local-maximum degree is assigned a specified or randomly selected color, and is then omitted from future iterations of the coloring process. After a stop criterion is met, the processor assigns random values to the remaining uncolored vertices and assigns colors based on comparisons of the random values.

Abstract: Partition management for a scalable, structured storage system is provided. The storage system provides storage represented by one or more tables, each of which includes rows that represent data entities. A table is partitioned into a number of partitions, each partition including a contiguous range of rows. The partitions are served by table servers and managed by a table master. Load distribution information for the table servers and partitions is tracked, and the table master determines to split and/or merge partitions based on the load distribution information.

Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.

Abstract: A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.

Abstract: A system for designing a power grid for an integrated circuit system forms a plurality of half pitch tiles that do not have a via violation, where each half pitch tile has a different orientation. The system generates sub tile arrays from each of the half pitch tiles. The system then forms a plurality of quarter pitch tiles that do not have a via violation, where each quarter pitch tile has a different orientation. The system generates deep sub tile cell arrays from each of the quarter pitch tiles. The system then covers a plurality of adjacent individual sub tile cells of the power grid with one of the sub tile arrays, and covers a plurality of adjacent individual deep sub tile cells of the power grid with one of the deep sub tile arrays.

Abstract: Methods and systems for partitioning a design across a plurality of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) are provided. The systems include SerDes (SERializer DESerializer) interfaces, such as PCIe, (Peripheral Component Interconnect Express) in the programmable logic devices operably connecting logic blocks of the design. Embodiments include a bridge in each programmable logic device for providing synchronization and deterministic latency of packets sent between the programmable devices.

Abstract: Methods and apparatuses for circuit design are described. In one embodiment, the method comprises determining a distribution of nets of a circuit, the distribution of the nets comprising numbers of blocks that each of the nets has in each of a plurality of partitions of the circuit in a partitioning solution, moving a first block of the circuit from a source partition to a destination partition to modify the partitioning solution, and updating the distribution of the nets after the moving.

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing placement using a 2D placer, performing placement for at least a first strata and a second strata, and then performing routing and completing the physical design of said 3D Integrated Circuit.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Abstract: A fixed-outline floorplanning approach for mixed-size modules is disclosed. Firstly, evenly distribute mixed-size circuit modules to whole chip area based on different requirements such as wire-length, routability, or thermal in the global distribution stage. To maintain the global distribution result and satisfy the fixed-outline constraint, generate a slicing tree by recursively applying partition algorithm to divide modules distributed in a given region into several sub-regions. Then, to remove overlap between circuit modules and find a best solution, use bottom-up shape curve merging and top-down back tracing procedure to generate a slicing tree. The shape curve for each leaf in the tree is built first by enumerated packing. Then, the curves in the tree are merged iteratively from bottom to top, and feasible solutions in the shape curve of the root node are identified according to the fixed-outline constraint. Finally, the best solution is determined by a top-down back tracing procedure.

Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.

Abstract: An integrated circuit (IC) design method includes providing a design layout of the IC and placing a first cell and a second cell into the design layout. The second cell is a minor of the first cell. The method further includes dividing the first cell into a first plurality of segments and dividing the second cell into a second plurality of segments. A third cell is formed by connecting a first portion of the first plurality of segments with a first portion of the second plurality of segments. A fourth cell is formed by connecting a second portion of the first plurality of segments with a second portion of the second plurality of segments. The first, second, third and fourth cells each have substantially the same function.

Abstract: An embodiment may include at least one die produced, at least in part, from a wafer, and may include at least one integrated circuit and/or at least one other integrated circuit. These integrated circuits may be mutual replications of each other and may include respective core and additional blocks. Each respective core block may have an associated respective capability. As formed in the wafer, the respective additional blocks may be coupled together so as to permit the associated respective capabilities of the respective core blocks to be functionally combined to provide an increased capability relative to each of the associated respective capabilities considered separately, and also so as to permit the integrated circuits to be externally interfaced as a unified device. The wafer may be separable into respective dice including respective of the integrated circuits such that the integrated circuits include respective external interfaces. Many modifications are possible.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.

Abstract: Disclosed are methods, systems, and articles of manufactures for implementing physical design decomposition with custom conductivity by identifying custom, incomplete conductivity for an electronic design, partitioning a physical design space multiple non-overlapping cells, and iteratively moving at least some of the nodes of these multiple cells to generate a floorplan or a placement layout until one or more convergence criteria are satisfied while maintaining the custom, incomplete conductivity. The floorplan or a placement layout generated resembles the final floorplan obtained through a floorplanner or the final placement layout through a placement tool without requiring that complete conductivity information be provided to the floorplanner or placement tool.

Abstract: In some embodiments, in a method performed by at least one processor, a physical netlist of a placed integrated circuit (IC) chip design is received by the at least one processor. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained by the at least one processor. Clusters of the registers are formed by the at least one processor. When forming cluster of the registers, candidate registers that are in physical vicinity of a first cluster are identified, and a first register is selected to be added to the first cluster by giving priority to a candidate register in a register pair across a boundary of the first cluster and with a higher timing criticality over a candidate register located closer to the first cluster. The registers in the same cluster have shorter non-common clock paths than the registers in different clusters.

Abstract: A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation system are also included.

Abstract: Aspects of the invention relate to simulation of circuits with repetitive elements. With various implementations of the invention, a circuit design for simulation is analyzed to derive information of memory-circuit device groups that comprise word-line-driven device groups. If the circuit design is hierarchically structured, the circuit design is flattened to device level but keep the memory-circuit device groups intact. The circuit design is then partitioned into a plurality of subcircuits for a simulation. During a transient simulation, whether an instance of a word-line-driven device group is activated is first determined. If activated, whether device model values exist for the word-line-driven device group at a voltage state associated with the activated instance is then determined. If they exist, the device model values are associated with the activated instance. If they do not exist, the device model values are computed for, stored for and associated with the activated instance.

Abstract: A method for designing a system on a target device is disclosed. The system is synthesized. The system is partitioned into a plurality of logical sections utilizing information derived from synthesizing the system and prior to performing placement of the system on the target device. Other embodiments are described and claimed.

Abstract: Embodiments of the disclosure relate to methods for facilitating the design of a clock grid in an integrated circuit. The method includes propagating a chip level virtual grid across a multi-level hierarchy of the integrated circuit and customizing the grid at each macro to create a customized virtual grid for each macro. The method further includes propagating the customized virtual grid for each of the plurality of macros to one of a plurality of units and customizing the chip level virtual grid at each of the plurality of units to create the customized virtual grid for each of the plurality of units. The method also includes propagating the customized virtual grid for each of the plurality of units to the chip level and combining the plurality of customized virtual grids to form the clock grid for the integrated circuit.

Abstract: A wiring design method and apparatus are provided. The wiring design method includes dividing a wiring region represented by wiring region data to generate a plurality of first division regions based on a first wiring rule and generating, when a second wiring rule different from the first wiring rule may be set in the first division region, second division regions with the second wiring rule in the first division region.

Abstract: Designing operation efficiency is improved by automatically transmitting and receiving circuit-related information and layout-related information required for designing each printed board between printed boards, for designing a plurality of printed boards at the same time. In an electric information processing method in a CAD system, the printed boards are designed at the same time by transmitting and receiving the circuit design information relating to the printed boards and the layout design information relating to the printed boards between the circuits and layouts relating to the printed boards.

Abstract: Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip).

Abstract: A method of configuring a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The data path is partitioned into a plurality of discrete regions, each region operating on a different clock phase and having discrete control logic elements. Phase transition registers to align data separated by a boundary between regions having different clock phases are introduced into the data path at the boundary. The graph and control logic elements define a hardware design for the pipelined parallel stream processor.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule.

Abstract: A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.

Abstract: A method of designing an acoustic microwave filter comprises selecting a filter section based on frequency response requirements. The filter section includes an input, an output, and a plurality of circuit elements. The circuit elements have at least in-line acoustic resonators or in-shunt acoustic resonators. The method further comprises selecting a value for each circuit element, selecting a number of filter sections, and cascading the selected number of filter sections to create a cascaded filter circuit design, such that at least one pair of immediately adjacent filter sections are connected to each other via their inputs or their outputs. The method further comprises adding parasitic effects to the cascaded filter circuit design to create a pre-optimized filter circuit design, optimizing the pre-optimized filter circuit design to create a final filter circuit design, and constructing the acoustic microwave filter based on the final filter circuit design.

Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.

Abstract: A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

Abstract: A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.

Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.

Abstract: Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.

Abstract: A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can include evaluating each cut set according to a cost function that depends, at least in part, upon a measure of inter-cut symmetry and selecting a cut set according to the cost function. Each cut of the selected cut set can represent an instantiation of at least one logic component within the programmable logic device. The circuit design specifying the selected cut set can be output.

Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Abstract: Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described.

Abstract: Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree.