Testing Or Evaluating Patents (Class 716/136)
  • Patent number: 10796315
    Abstract: A method for automated recertification of a safety critical system with at least one altered functionality is provided. The method includes providing a failure propagation model of the safety critical system. The method also includes updating the failure propagation model of the safety critical system according to the at least one altered functionality using inner port dependency traces between inports and outports of a failure propagation model element representing the at least one altered functionality. The method includes calculating top events of the updated failure propagation model, and comparing the calculated top events with predetermined system requirements to recertify the safety critical system.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: October 6, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventor: Kai Höfig
  • Patent number: 10783296
    Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Diakopto, Inc.
    Inventor: Maxim Ershov
  • Patent number: 10776538
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Mei Wong, Hsin-Cheng Chen
  • Patent number: 10769339
    Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ? ( F ˜ 1 , C ? 2 ? q ? E g ? N n ? e ? t ? ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 8, 2020
    Assignee: Synopsys, Inc.
    Inventors: Hiu Yung Wong, Rimvydas Mickevicius
  • Patent number: 10747433
    Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 18, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Jing Li, Jialiang Zhang
  • Patent number: 10747259
    Abstract: Herein is disclosed a multichip reference logging system comprising a control circuit, configured to generate a reference signal; a first chip, configured to generate a first operations log, the first chip further comprising a first reference circuit, configured to receive the reference signal and to create a first reference event in response to the received reference signal; a memory associated with the first chip, configured to store the first reference event within the first operations log; a second chip, configured to generate a second operations log, the second chip further comprising a second reference circuit, configured to receive the reference signal and to create a second reference event in response to the received reference signal; and a memory associated with the second chip, configured to store the second reference event within the second operations log.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Intel IP Corporation
    Inventors: Uwe Schumacher, Peter Lachner, Andrej Tkalcec, Donald Korinke
  • Patent number: 10706205
    Abstract: A method for detecting hotspots in physical design layout patterns includes receiving a given physical design layout pattern, utilizing a hotspot detection model to detect one or more potential hotspots in the given physical design layout pattern, and performing a verification to determine whether a given potential hotspot of the one or more potential hotspots detected by the hotspot detection model comprises a real hotspot or a nonexistent hotspot. The method also includes, responsive to determining that the given potential hotspot comprises an actual hotspot, modifying the given physical design layout pattern to remove the actual hotspot. The method further includes, responsive to determining that the given potential hotspot comprises a nonexistent hotspot, augmenting the hotspot detection model with additional training data generated based on the nonexistent hotspot.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dongbing Shao, Jing Sha, Kafai Lai
  • Patent number: 10698897
    Abstract: Systems and methods are disclosed for executing a distributed execution model with untrusted commands. The distributed execution model can be distributed to multiple nodes in a distributed computing environment. At least one node can process the distributed execution model to identify an untrusted command. The node can use data associated with the untrusted command to identify one or more files associated with the untrusted command. Based on the files, the node can generate a data structure, and execute at least a portion of the data structure.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 30, 2020
    Assignee: Splunk Inc.
    Inventors: Arindam Bhattacharjee, Sourav Pal, Alexander Douglas James
  • Patent number: 10684557
    Abstract: A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A functional relationship between local height deviations across a substrate and focus information, such as a determined focus amount, is determined for a substrate, e.g., a reference substrate. Height deviations are subsequently measured for another substrate, e.g. a production substrate. The height deviations for the subsequent substrate and the functional relationship are used to determine predicted focus information for the subsequent substrate. The predicted focus information is then used to control the lithographic apparatus to apply a product pattern to the product substrate.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: June 16, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Rene Marinus Gerardus Johan Queens, Emil Peter Schmitt-Weaver
  • Patent number: 10657303
    Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 19, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, Ching-Ho Lin
  • Patent number: 10657308
    Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sungjun Chun, Matteo Cocchini, Michael A. Cracraft
  • Patent number: 10620265
    Abstract: A method for real-time testing of a control unit with a simulator is provided. The simulator calculates a load current and a load voltage as electrical load state variables via converter control data and via an electrical load model that does not take into account current discontinuities caused by the converter, and transmits at least a portion of the load state variables to the control unit. A control observer is additionally implemented on the simulator that calculates at least the load current as a load state variable taking into account the converter control data and an observer load model. The observer detects a zero-crossing of the load current and a current discontinuity caused thereby from the calculated load current, and upon detection of a current discontinuity the observer calculates an electrical compensating quantity.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 14, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Quang Ha, Martin Aust, Frank Puschmann
  • Patent number: 10571514
    Abstract: A thermal transient response simulation is performed for a structure having a plurality of thermal model elements. The thermal transient response simulation determines a relation between transient thermal impedance of the structure and time and a relation between maximum temperature change of each of the thermal model elements and time. An onset time at which energy reaches each of the thermal model elements is determined based on the relation between maximum temperature change of each of the thermal model elements and time and a predetermined maximum temperature change threshold. An influence onset resistance value for each of the thermal model elements is determined by looking up a thermal resistance value corresponding to the onset time based on the relation between transient thermal impedance of the structure and time. A structural function is mapped based on the influence onset resistance value for each of the thermal model elements.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 25, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Byron Blackmore, Joseph Charles Proulx, Robin Bornoff, Andras Vass-Varnai
  • Patent number: 10546083
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Verma, Suyash Kumar, Habeeb Farah
  • Patent number: 10542301
    Abstract: A multimedia redirection method comprising receiving, by a server, a hardware decoding capability sent by a client, where the hardware decoding capability is a hardware decoding capability that is in a video hardware acceleration specification and that is converted from a hardware decoding capability of a non-Windows operating system by the client; restoring, by the server, video data to a video code stream of a standard encoding format after receiving the hardware decoding capability; and sending, by the server, the video code stream to the client for decoding and display.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chong Chen, Yanping Meng
  • Patent number: 10528644
    Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 7, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu
  • Patent number: 10522329
    Abstract: A method for re-calculating a pattern to be exposed on a target by means of a charged-particle multi-beam writing apparatus is presented. The pattern elements of a pattern, initially associated with a respective assigned dose, are recalculated in view of obtaining reshaped pattern elements which have a nominal dose as assigned dose. The nominal dose represents a predefined standard value of exposure dose to be exposed for pixels during a scanning stripe exposure within the multi-beam apparatus.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 31, 2019
    Assignee: IMS Nanofabrication GmbH
    Inventors: Elmar Platzgummer, Christoph Spengler, Wolf Naetar
  • Patent number: 10515612
    Abstract: A system and method for operating a display. In some embodiments, the method includes: transforming a stress profile for a slice of the display, with a first transformation, to form a transformed stress profile; compressing the transformed stress profile to form a compressed transformed stress profile; decompressing the compressed stress profile to form a decompressed transformed stress profile; and transforming the decompressed transformed stress profile, with a second transformation, to form a decompressed stress profile, the second transformation being an inverse of the first transformation.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amin Mobasher, Shiva Moballegh, Jalil Kamali
  • Patent number: 10430411
    Abstract: Incrementally updating statistics includes sampling rows from a database column in a database to generate a first sample, sampling a subset of modified rows from the database column after generating the first sample to generate a second sample, determining whether distribution changes occurred to the database column based on the first and second samples, and updating a database statistic about the database column in response to determining that a distribution change exists.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 1, 2019
    Assignee: MICRO FOCUS LLC
    Inventors: Choudur Lakshminarayan, Ramakumar Kosuru, QiFan Chen, Hansjorg Zeller
  • Patent number: 10429442
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 1, 2019
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 10417361
    Abstract: Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael James Floyd, Philip Benedict Giangarra, Abu Nasser Mohammed Abdullah, Zhengang Hong, Joseph Ralph Horn
  • Patent number: 10365320
    Abstract: There is a need to improve estimation accuracy of a failure estimation method or its failure estimation apparatus that performs failure estimation on a targeted instrument based on history information about several instruments mounted with the same type of semiconductor device as an instrument targeted at failure estimation. A failure estimation apparatus that includes a history information database storing history information about a plurality of instruments mounted with the same type of semiconductor device and performs failure estimation on a targeted instrument mounted with a semiconductor device whose type equals the type, wherein the history information contains operation information and failure information; wherein the operation information indicates a chronological operating state of the semiconductor device mounted on the instruments; wherein the failure information indicates a failure cause of a failed instrument; and wherein the operating state is categorized into a plurality of classifications.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuji Takehara, Takeo Mimura, Tomohiro Oono
  • Patent number: 10365326
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two module representations of the plurality of module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the plurality of module representations, and the one or more connections. The test scenario model includes a path from the input via the plurality of module representations and the one or more connections to the desired output.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 10353916
    Abstract: In one embodiment, techniques are provided for converting a CAD description maintained in a first storage format (e.g., a file-based storage format) of a source repository to a second storage format (e.g., a relational database-based storage format) of an output repository. The techniques may, generate a single, coherent representation from spatially ambiguous “fragments” by generating an acyclic model graph for each graphical view, and then storing models of the acyclic model graph in the second storage format (e.g., the relational database-based storage format). The techniques may further produce a post-conversion CAD description that preserves human-readable names and information relationships related to levels by examining attachment specific copies of level structures (i.e. levels and attached levels) referenced from attachments, and generating from these categories and subcategories in the second storage format (e.g., the relational database-based storage format).
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 16, 2019
    Assignee: Bentley Systems, Incorporated
    Inventors: Keith A. Bentley, Samuel W. Wilson
  • Patent number: 10354045
    Abstract: An integrated circuit (IC) design is received. The IC design has devices on different layers electrically connected to each other by conductive vias extending between the different layers. Relative locations of the vias, and of conductive components of the devices within adjacent layers of the different layers, are identified. The conductive components that overlap redundant vias are also identified. This allows 2D via checker data, that is a combination of the 3D adjacent layers, to be generated. The 2D via checker data includes rectangular geometric shapes that represent each instance of the conductive components overlapping redundant vias. Thus, the 2D via checker data is output, and lack of rectangular geometric shapes in the 2D via checker data provides data of locations in the IC design that fail to have redundant vias.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ahmed Abdelghany Alsayed Omara
  • Patent number: 10320494
    Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter and an RF receiver. The RF transmitter is configured to generate an RF signal in response to an analog test signal from a test signal generator of a module circuitry that is external to the IC. The RF receiver is configured to generate an outgoing signal according to an input RF signal, and to report the outgoing signal to the module circuitry. The module circuitry performs a test analysis on the RF signal generated by the RF transmitter or on the outgoing signal generated by the RF receiver to determine a test result. The test result is reported to a test equipment having no RF instruments.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 11, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Hwui Chung, Chung-Chin Tsai, Ping-Hsuan Tsu, Chun-Hsien Peng
  • Patent number: 10262408
    Abstract: A system, method, and computer program product are provided for systematic and stochastic characterization of pattern defects identified from a fabricated component. In use, a plurality of pattern defects detected from a fabricated component are identified. Additionally, attributes of each of the pattern defects are analyzed, based on predefined criteria. Further, a first set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be systematic pattern defects, and a second set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be stochastic pattern defects. Moreover, a first action is performed for the determined systematic pattern defects and a second action is performed for the determined stochastic pattern defects.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 16, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Allen Park, Moshe Preil, Andrew James Cross
  • Patent number: 10255394
    Abstract: A method for simulating an integrated circuit model is provided. The method includes receiving partition netlists of an integrated circuit in a partition scheduler and scheduling, by at least one computer, an execution of a computational thread associated with a first partition netlist. The method also includes preparing input data for a task and storing the input data set in an object storage. Also, the method includes executing, by the computer, the task in the computational thread. The method also includes building dependency trees between multiple tasks for reducing the input/output data overhead, and caching information that may be necessary for each task but may be reusable by the task when such information is unavailable from previously computed tasks.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 9, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Harsh Vardhan, Jalal Wehbeh, Robert MacDonald
  • Patent number: 10255405
    Abstract: A design supporting apparatus of a semiconductor integrated circuit includes an input device configured to receive data of a transient current waveform, a first modeling part configured to model the semiconductor integrated circuit as a current source for generating the transient current waveform and to connect the current source and an equivalent circuit of an evaluation board to generate an evaluation circuit model, a first calculation part configured to calculate electromagnetic interference of the evaluation circuit model, a first correction part configured to correct a portion of the equivalent circuit of the evaluation board, a second modeling part configured to add an additional circuit to a corrected evaluation circuit model to generate a countermeasure circuit model, a second calculation part configured to calculate electromagnetic interference of the countermeasure circuit model, and a second correction part configured to correct the additional circuit.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: April 9, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Ryosuke Inagaki
  • Patent number: 10242150
    Abstract: Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: March 26, 2019
    Assignee: XILINX, INC.
    Inventors: Sabyasachi Das, Xiaojian Yang, Niyati Shah, Govinda Keshavdas, Frederic Revenu
  • Patent number: 10241852
    Abstract: A method for automated qualification of a safety critical system including a plurality of components is provided. A functional safety behavior of each component is represented by an associated component fault tree element. The method includes automatically performing a failure port mapping of output failure modes to input failure modes of component fault tree elements based on a predetermined generic fault type data model stored in a database.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: March 26, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kai Höfig, Marc Zeller
  • Patent number: 10228421
    Abstract: Disclosure is related to a method and a system for intelligent defect classification and sampling, and a computer-readable storage device. The computer-implemented method acquires in-line defect inspection file, and retrieves the defect patterns over a device under test, e.g. a wafer from a fab. The system incorporates a defect pattern recognition engine to recognize the defect signature patterns from the defect patterns. A sampling scheme is performed to acquire weak defect patterns. A critical area analysis based on failure probability of weak patterns is incorporated to performing the sampling. The defect layout pattern groups probably causing the open or short failure can be obtained. The defect signature patterns through sampling are then displayed using a browsing system. Through a user interface, the user can perform functions, such as filtering, selection and merging, onto the defect patterns.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 12, 2019
    Assignee: Elite Semiconductor, Inc.
    Inventor: Iyun Leu
  • Patent number: 10224233
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and comprises a region of nitrogen-reacted nanovoids in the front surface region; a silicon dioxide layer on the surface of the semiconductor handle substrate; a dielectric layer in contact with the silicon dioxide layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 5, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Qingmin Liu, Robert Wendell Standley
  • Patent number: 10216878
    Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
  • Patent number: 10212036
    Abstract: Provided is a performance testing method, a system and a storage medium for the same. The method may include determining test object metadata that defines a protocol for a test object and test job metadata that defines a performance test using a prescribed job, generating job data based on the test job metadata, generating load data according to the prescribed job to provide the load data to at least one test performing node among a plurality of test performing nodes coupled to the test object, and causing the at least one test performing node to perform the performance test for the test object.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: February 19, 2019
    Assignee: LG CNS CO., LTD.
    Inventor: Seung Kab Rho
  • Patent number: 10192012
    Abstract: A method for determining a signal electromigration effect in a circuit includes obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a complementary netlist that couples a second input with the output is provided. The complementary netlist is logically independent from the reference netlist. The method includes modifying the partition netlist to couple the reference netlist and the complementary netlist in an inverting configuration, and providing an electromagnetic pulse to at least one of the first input or the second input to induce a current through one of the plurality of circuit components. The method also includes determining an electromigration effect from the current on the one of the plurality of circuit components.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 29, 2019
    Inventors: Jalal Wehbeh, Aswin Ramakrishnan, Igor Keller, Federico Politi, Ajish Thomas
  • Patent number: 10191998
    Abstract: A method includes receiving, at a master controller, a matrix representing a graph and a first vector, and initializing a counter variable and an array to track dimensionality reduction for the matrix. The method also includes multiplying a subset of the matrix based on the counter variable, by a subset of the first binary vector based on the counter variable. Multiplying includes providing, the vector and a matrix portion to a first processor, and the vector and another portion of the matrix to a second processor. The method also includes, at the processors, multiplying the vectors by the portions of the matrix and returning the results. The method also includes combining the results at the master controller. The method also includes incrementing the counter variable and updating the tracking array for larger dimensionality reduction of the matrix. The method also includes constructing the logical pathway based on the tracking array.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: January 29, 2019
    Assignee: The United States of America, as represented by the Director, National Security Agency
    Inventor: Paul Burkhardt
  • Patent number: 10061670
    Abstract: An apparatus includes an input that receives a continuous function chart for each component of the investigated safety-critical system. A processor generates a corresponding component fault tree element. Inports and outports of the component fault tree element are generated and interconnected based on unique names of the inputs and outputs of the corresponding continuous function chart of the respective system component. Input failure modes and output failure modes are generated based on generic mapping between connector types of the continuous function chart and failure types of failure modes of the component fault tree element. The input failure modes of a component fault tree element are connected to output failure modes of the component fault tree element via internal failure propagation paths based on interconnected function blocks of the continuous function chart of the respective system component. An output outputs the generated component fault tree of the safety-critical system.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 28, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kai Höfig, Marc Zeller
  • Patent number: 10002827
    Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: June 19, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Yuping Ren, Chin Teong Lim, Xusheng Wu, Paul Ackmann
  • Patent number: 9989589
    Abstract: A system and method for testing electronic circuit devices. The system has a central processing unit with a plurality of separate core processing units. The utility service program is initiated at the startup of the computer program which acts as an intermediary between user applications and the computer operating system. The utility service is responsive to an ATE execution engine to set an affinity for one or more processing cores for exclusive use for the ATE execution engine. The ATE execution engine communicates with the utility service to reserve one or more processing cores for execution of the program for testing electronic devices.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 5, 2018
    Inventors: William Birurakis, Valeriy Pavlenko
  • Patent number: 9989591
    Abstract: Method and apparatus for performing Pattern-Controlled tests on an automatic test equipment (ATE). The ATE includes a diagnostic instrument and a control device. An application programming interface (API) is installed in the control device and operates to interact with a test program and thereby automatically controls the diagnostic instrument to perform a test. The test program is coded in a high-level programming language and defines a plurality of operation events for the test based on user input. The API identifies the operational events and determines respective operational types associated therewith. Events of an operational type are assigned to a respective pattern label. The pattern labels are then aggregated into a pattern burst which is downloaded to the diagnostic instrument.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: June 5, 2018
    Assignee: ADVANTEST CORPORATION
    Inventors: Liang Ge, Jia-Min Wang
  • Patent number: 9971250
    Abstract: A method of decomposing layout design for preparing a photomask set printed onto a wafer by photolithography includes the following steps. An integrated circuit layout design including several features is obtained. The overlay relation of these features is recognized to classify these features into a first group and a second group. These features printed onto different layers of the wafer are distinguished to decompose the first group into a first feature and a third feature, and the second group into a second feature and a fourth feature. The first feature is outputted to a first photomask, the second feature is outputted to a second photomask, a third feature is outputted to a third photomask and a fourth feature is outputted to a fourth photomask. A method of forming a photomask set and a method of fabricating an integrated circuit are also provided.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: May 15, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 9940426
    Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sungjun Chun, Matteo Cocchini, Michael A. Cracraft
  • Patent number: 9940430
    Abstract: Method of burn-in power optimization which includes: testing integrated circuit devices to record a performance speed for each of the integrated circuit devices; categorizing each integrated circuit device by a selective voltage binning (SVB) process into a voltage bin according to the performance speed of the integrated circuit device; performing a burn-in operation on each of the integrated circuit devices while toggling an SVB performance monitor on each of the integrated circuit devices; testing the plurality of integrated circuit devices after the burn-in operation; categorizing each integrated circuit device into the SVB voltage bin according to the performance speed of the integrated circuit device after the burn-in operation; when the SVB voltage bin after the burn-in operation corresponds to an SVB voltage bin having a slower performance speed than before the burn-in operation, changing the SVB voltage bin to the slower performance speed.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. Bickford, Nazmul Habib, Baozhen Li, Tad J. Wilder
  • Patent number: 9934410
    Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 3, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
  • Patent number: 9931882
    Abstract: An identification patch having a plasmonic resonance structure may be used to ensure that an article is counterfeit-proof. The identification patch may be formed by a printing process, such as roll-to-roll printing or nanoimprinting, to create a distinctive ordered pattern of resonance elements. When the plasmonic resonance structure is irradiated, the ordered pattern of resonance elements produces a unique spectral response that is associated only with the counterfeit-proof article. The counterfeit-proof article may be a metal component or an integrated circuit. The resonant absorption of the plasmonic resonance structure may be measured to verify the authenticity of the article before use of the article.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 3, 2018
    Assignee: Raytheon Company
    Inventor: Gerald P. Uyeno
  • Patent number: 9922209
    Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 20, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventors: Victor Markus Purri, Caio Araújo Teixeira Campos, Magnus Björk, Lawrence Loh, Claudionor Jose Nunes Coelho
  • Patent number: 9916410
    Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sungjun Chun, Matteo Cocchini, Michael A. Cracraft
  • Patent number: 9880550
    Abstract: A computerized system that may include a recipe module and a yield diagnostics module. The yield diagnostics module may be configured to generate evaluation results that are indicative of an outcome of an evaluation process of at least one manufacturing stage of at least one electrical circuit. The evaluation results differ from end of line (EOL) results. The recipe module may be configured to receive EOL results relating to the at least one electrical circuit, to receive the evaluation results relating to the at least one electrical circuit; to correlate the evaluation results and the EOL results to provide correlation results; and respond to the correlation results. The responding to the correlation results may include determining whether to alter a recipe in response to the correlation results and altering the recipe if it is determined to alter the recipe.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 30, 2018
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventor: Amir Wachs
  • Patent number: 9881111
    Abstract: Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 30, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Jie Liu, Victor Moroz, Michael C. Shaughnessy-Culver, Stephen Lee Smith, Yong-Seog Oh, Pratheep Balasingam, Terry Sylvan Kam-Chiu Ma