Abstract: A method for establishing a variation model related to circuit characteristics for performing circuit simulation includes: performing first, second, third, and fourth Monte Carlo simulation operations according to a first netlist file and predetermined process model data to generate a first, a second, a third, and a fourth performance simulation results, respectively, where the first netlist file is arranged to indicate a basic circuit in a circuit system; and execute a performance simulation results expansion procedure according to the first, the second, the third, and the fourth performance simulation results to generate a plurality of performance simulation results to establish the variation model, for performing the circuit simulation to generate at least one circuit simulation result according to one or more performance simulation results among the plurality of performance simulation results, where the number of the plurality of performance simulation results is greater than four.

Abstract: A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the emulation compiler. The processing device performs a design verification using the modified simulation compiler.

Abstract: A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where the subset of the set of constraints may include an inconsistency which caused the rule check to fail.

Abstract: An IC includes a pad, a current detection device connected to the pad and configured to generate monitoring information corresponding to an electrostatic discharge (ESD) event, and an internal circuit configured to receive the monitoring information from the current detection device, wherein the current detection device includes a current sensing circuit having a T-coil that is configured to generate an ESD current when the ESD event occurs and is further configured to generate an induced voltage corresponding to the ESD current, a plurality of detection circuits outputting a detection signal based on the induced voltage, and a monitoring circuit configured to receive the detection signal from each of the plurality of detection circuits and configured to generate the monitoring information, wherein the plurality of detection circuits have different sensitivities with respect to the induced voltage.

Abstract: A semiconductor metrology system including a spectrum acquisition tool for collecting, using a first measurement protocol, baseline scatterometric spectra on first semiconductor wafer targets, and for various sources of spectral variability, variability sets of scatterometric spectra on second semiconductor wafer targets, the variability sets embodying the spectral variability, a reference metrology tool for collecting, using a second measurement protocol, parameter values of the first semiconductor wafer targets, and a training unit for training, using the collected spectra and values, a prediction model using machine learning and minimizing an associated loss function incorporating spectral variability terms, the prediction model for predicting values for production semiconductor wafer targets based on their spectra.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.

Abstract: Method and System for Parallel Design and Technology Optimization are disclosed. The disclosed method enables efficient parallel design and technology optimization (PDTO) and allow designers to sign off the technology development or find the optimal design point with the design analysis tools. The method includes generating, from a manufacturing technology process, a baseline SPICE model based on technology specification and manufacturing process data; extending the baseline SPICE model to a corresponding description of technology specification window in the circuit design process, where the technology specification window describes extended ranges of device model parameters; extracting a targeted SPICE model using the technology specification window; verifying, by a circuit design process that operates in parallel to the manufacturing technology process, the integrated circuit meets a design specification using the targeted SPICE model.

Abstract: Methods, systems and apparatus for benchmarking quantum computing hardware. In one aspect, a method includes defining an initial circuit configured to operate on an array of qubits, wherein the initial circuit comprises multiple instances of the two-qubit gate, wherein each instance of the two-qubit gate performs a same operation on a respective pair of neighboring qubits in the array; partitioning the initial circuit into multiple layers, wherein instances of the two-qubit gate in a respective layer can be implemented in parallel; for each of the multiple layers: constructing benchmarking circuits for the layer, wherein each benchmarking circuit for the layer comprises one or more cycles of quantum gates, each cycle comprising: the layer of instances of the two-qubit gate, and a plurality of single qubit gates; implementing the constructed benchmarking circuits to obtain experimental benchmarking data; and adjusting control parameters of the control model using the experimental benchmarking data.

Abstract: A method for fault tree analysis (FTA) of a system, the method may include (i) preforming FTA of the system using multiple hybrid events to provide a FTA result, wherein each hybrid event represents both latent failure modes and evident failure modes; and (ii) responding to the FTS result.

Abstract: A method and system for controlling actions of testbench components present within a test environment based on a testing context is disclosed. In some embodiments, the method includes receiving a controllable actions packet from each of a plurality of testbench components in the test environment; parsing a testing context associated with a test sequence; generating a context-based actions control packet for each of the plurality of testbench components, based on the testing context metadata and the list of controllable actions corresponding to each of the plurality of testbench components; and transmitting the context-based actions control packet to an associated testbench component of the plurality of testbench components.

Abstract: Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Abstract: This disclosure provides methods and apparatuses for testing a tested circuit. In an implementation, a chip test circuit transmits input data of a test vector to a data distribution circuit through an input of a test bus, and transmits the input data of the test vector to a scan input channel of a tested circuit through the data distribution circuit. After scanning of the tested circuit ends, output data of the test vector of the scan output channel of the tested circuit is transmitted to an output of the test bus through the data distribution circuit to complete the test of the tested circuit. A dynamic correspondence between the data distribution circuit and the test bus is implemented by configuring a first selector, so that test resources can be dynamically allocated.

Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.

Abstract: A method for real-time extraction of on-chip simulation information including acquiring simulation job information, and analyzing the simulation job information to obtain option and parameter information; and acquiring index information from a simulation project according to the option and the parameter information, and formatting the index information to obtain a simulation result. According to said method, key information of a simulation result is extracted in real time by performing text scanning and pattern analysis on a log file during a simulation process, so that a user can conveniently learn about the progress situation of the current simulation task at any time, and determine to continue or terminate the task at any time according to the current state and result situation, thereby more flexibly controlling a flow according to an actual situation, simplifying operations, increasing design efficiency, and compensating for the disadvantages of traditional simulation methods.

Abstract: A phase shifter includes functional actively controlled phase-shift elements formed with TSVs. The phase shifter may include plural phase shifter elements each including: a signal line including a signal line through-substrate-via (TSV) in a substrate; a ground return line including a ground return line TSV in the substrate; a capacitance control line including a capacitance control line TSV in the substrate; and an inductance control line including an inductance control line TSV in the substrate, wherein the phase shifter element has one of a first phase shift and a second phase shift, different from the first phase shift, based on a capacitance and an inductance of the signal line TSV.

Abstract: An apparatus for conducting an engineering analysis of a structural product is provided. The apparatus produces a computer-aided design (CAD) model of the structural product including component parts joined by fasteners and produces a finite-difference time-domain (FDTD) model of the structural product from the CAD model. The apparatus assigns one or more electrical properties to a mesh of elements representing the component parts and fasteners, and performs a finite-difference time-domain analysis on the FDTD model with the one or more electrical properties assigned, and with the FDTD model exposed to simulated lightning, to predict an impact of lightning on the fasteners and therefrom generate a corresponding prediction. The apparatus produces an output based on the corresponding prediction that indicates one or more levels of the impact of lightning on the fasteners and displays the output to facilitate design or manufacture of the structural product.

Abstract: The present disclosure discloses a dynamic equivalent circuit of a combined heat and power system, and a working method thereof. Controlled sources are used to represent a thermoelectric coupling source; equivalent inductance is used to represent a delay of a heat transmission pipeline; equivalent resistance is used to represent a heat load and a heat loss of the heat transmission pipeline; and equivalent capacitance is used to represent a heat storage water tank. A circuit model is used to uniformly represent two thermoelectric heterogeneous energy sources, and a single power simulation tool may be used to simulate a combined heat and power system, so that the simulation system has a simple structure and is easy to develop and maintain.

Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

Abstract: Some embodiments of the present disclosure discloses a method and apparatus for acquiring information, relates to the technical field of information transmission and distributed network architecture. The method includes: determining, in response to receiving an instruction used to indicate to acquire configuration information, for each of a plurality of physical machines, a set of candidate processes of the physical machine; acquiring a first key value, and determining a target candidate process of the physical machine from the set of candidate processes based on the first key value; acquiring a second key value, and determining a target process from a plurality of target candidate processes determined based on the plurality of physical machines based on the second key value; and acquiring the configuration information using the target process.

Abstract: A method for system-on-chip (SoC) verification is disclosed.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: Provided are a method and a device for electrical DRC of an integrated circuit. The method includes: acquiring a parasitic parameter netlist of the integrated circuit; receiving a circuit simulation result of the integrated circuit and electrical DRC rules; and performing electrical DRC on the integrated circuit based on the parasitic parameter netlist, the circuit simulation result and the electrical DRC rules.

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.

Abstract: The invention relates to a graph clustering method based on perception application algorithm semantics and a computer readable medium. The graph clustering method includes: acquiring original graph data G and a graph's application algorithm A; initializing a subgraph Gi; randomly selecting a vertex v and a corresponding connecting edge thereof from the graph G, and deleting the v and the corresponding edge thereof from the graph G; computing a semantic serial degree after adding the vertex v into the subgraph Gi; determining a clustering block with the maximum semantic serial degree, and adding the vertex v and the corresponding connecting edge into the subgraph; repeating the steps until the graph G is empty; and completing graph clustering, and outputting a clustering result. Compared with the prior art, the method provided by the invention has the advantages of being able to greatly accelerate application analysis and mining of big graph data.

Abstract: A method is disclosed for improving the permissiveness of a vehicle designed to operate within an operational design domain (“ODD”) where the vehicle has an autonomous vehicle control system capable of collecting sensor data. The method, which can be incorporated into a system or into instructions placed on storage media, includes partitioning the ODD into subsets (“micro-ODDs”) that relate to different operational situations and creating safety envelopes for those subsets. The safety envelopes are used to keep the vehicle operating safely and can be optimized to improve permissiveness of the vehicular operation.

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

Abstract: The present disclosure discloses a method and apparatus for optimizing a qubit control signal, and a quantum computer. The method includes: obtaining an operating frequency of a qubit based on a Ramsey experiment; obtaining a detuning amount of a frequency of the qubit control signal based on an amplified phase error (APE) experiment, where the APE experiment is an experiment that measures a change in quantum state information of the qubit with a preset detuning amount of the frequency of the qubit control signal; and optimizing the qubit control signal based on the detuning amount of the frequency.

Abstract: The computer executable instructions include a command that accepts multiple user input through various command options. The command encapsulates and implements multiple original software algorithms that convert trunking design intent, expressed via the command options, into trunks on multiple layers of a process technology node. Once executed, the command generates shapes of trunks of specified topology on specified layers. The command includes a set of options to generate a simple or complex trunking topology. The command accepts topology, set of zones, nets and many other options that the user provides to the command to yield trunks of a desired topology. The topology description is relative; thus, it can easily adjust as design changes. The command together with its options represents trunk creation intent.

Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.

Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.

Abstract: A computer design verification system comprising a parsing module configured to receive output messages from a computer design testing tool and to compose from the output messages formatted objects comprising a set of fields having field descriptors and test values; a signoff module holding a plurality of signoff objects, each comprising a plurality of fields having a field descriptor, at least some fields populated with a signoff expression, each signoff object associated with a severity level indicative of the severity of a condition represented by the signoff object. The signoff module is configured compare at least one test value in the formatted objects received from the parsing module with at least one signoff expression in the signoff objects to determine if a signoff object matches the formatted object, and in the case of a match, associating the severity level of the signoff object with the formatted object.

Abstract: A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.

Abstract: A simulation method and system of verifying an operation of a semiconductor memory device of a memory module at a design level. The simulation method includes setting a configuration and an arrangement of a registered clock driver (RCD) and a configuration and an arrangement of first semiconductor memory devices to fourth semiconductor memory devices, on a printed circuit board (PCB) through a graphic user interface (GUI). When a RCD test execution command is applied through the GUI, executing a test program to apply control signals to control signal terminals of the PCB based on a command truth table, to compare the applied control signals and control signals output through first driver output terminals of the RCD, and to create an RCD test result. When the RCD operates normally, performing a test on the memory module.

Abstract: The present invention provides a novel approach for storing, analyzing, and/or accessing biological data in a cloud computing environment. Sequence data generated by a particular sequencing device may be uploaded to the cloud computing environment during a sequencing run, which reduces the on-site storage needs for the sequence data. Analysis of the data may also be performed in the cloud computing environment, and the instructions for such analysis may be set at the originating sequencing device. The sequence data in the cloud computing environment may be shared according to permissions. Further, the sequence data may be modified or annotated by authorized secondary users.

Abstract: This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.

Abstract: A method for auto-generating an AutoCAD drawing includes providing an interface for extracting only input data required for drawing equipment from strength calculation data, displaying all components and nozzles constituting the equipment and providing or correcting information thereon. The AutoCAD drawing is automatically generated based on information on all components constituting the equipment and nozzles.

Abstract: A computing device, method and computer program product are provided in order to develop a system model. In a method, a simulation model is designed that is configured to digitally simulate a corresponding portion of a system. The method also includes associating a simulation assessment module with the simulation model. The simulation assessment module is configured to verify one or more signals propagating within the simulation model. In an instance in which the simulation assessment module has verified the one or more signals, the method includes performing a unit test upon the simulation model to confirm proper operation of the simulation model. In an instance in which the unit test is successful, the method includes integrating a plurality of simulation models to form the system model.

Abstract: Proposed by the present disclosure are an FPGA-based resequencing analysis method and device, wherein the method comprises: receiving genomic resequencing data; using the resequencing data as an input of an FPGA, determining a comparison result in the resequencing process according to an output of the FPGA, and simultaneously performing sorting and deduplication processing on the comparison result; correcting a base quality value of the comparison result after sorting and deduplication processing; and detecting a mutation result according to the corrected comparison result. The described method may save program running time, save calculation costs, and improve resequencing efficiency.

Abstract: Methods and computing devices for allocating test pods to a distributed computing system for executing a test plan on a device-under-test (DUT). Each test pod may include a test microservice including one or more test steps and an event microservice specifying function relations between the test microservice and other test microservices. The test pods are allocated to different servers to perform a distributed execution of the test plan on the DUT through one or more test interfaces.

Abstract: A method is provided for placing a first content and a second content on a display screen at a distance D along a Y-axis in an orthogonal coordinate system formed by an X-axis and the Y-axis. The method includes identifying, in the first content, a first non-display-target region which is located on the second content side, identifying, in the second content, a second non-display-target region which is located on the first content side, calculating a plurality of total widths each of which is a sum of a width of the first non-display-target region in a direction of the Y-axis and a width of the second non-display-target region in the direction of the Y-axis, the widths being at a same X-coordinate, and determining the distance D based on the plurality of total widths and a predetermined reference.

Abstract: Security measures for signal paths with tree structures can be implemented at design phase using an EDA software program or tool with security feature functionality that, when executed by a computing system, directs the computing system to: display a canvas through which components of a circuit are arranged; and provide a menu of commands, including an option to add components from a library to the canvas and an option to secure a tree. In response to receiving a selection of the option to secure the tree, the system can be directed to add a hardware countermeasure coupled to at least two lines or terminal nodes of a tree structure identified from components on the canvas or in a netlist corresponding to a circuit's design.

Abstract: In a network-on-chip (NoC) interconnect connected to one or more agents with multiple input ports, one or more switches are provided with a round robin arbiter constructed to use representations of the input ports and, in some embodiments, the current round robin state, as thermometer codes. By using thermometer code to represent port information, the correspondence to the current input and the current state to be granted can be rapidly determined through a simple two-step AND and XOR operations. With such a simple logical procedure, the number of steps to make the determination, and therefore the energy required, can be reduced by log 2(n) steps or up to 43%. Using thermometer code reduces the number of computations required. Hence, the number of logic circuit elements required to carry out the calculation is reduced, shrinking the floorplan area needed for the arbiter.

Abstract: A robust predictive model. A plurality of different predictive models for a target feature are run, and a comparative analysis provided for each predictive model that meet minimum performance criteria for the target feature. One of the predictive models is selected, either manually or automatically, based on predefined criteria. For semi-automatic selection, a static or dynamic survey is generated for obtaining user preferences for parameters associated with the target feature. The survey results will be used to generate a model that illustrates parameter trade-offs, which will be used to finalize the optimal predictive model for the user.

Abstract: A method enables testing and evaluation of an expert human reviewer or an artificial intelligence (AI) error detection engine associated with a radiotherapy treatment planning process. Intentional errors are introduced into the output of a software module or AI engine that performs a certain step in the radiotherapy treatment planning process. The efficacy of the human or AI reviewer in detecting errors can then be evaluated or tested by determining whether the human or AI reviewer has detected the introduced error.

Abstract: A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.

Abstract: A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.

Abstract: A semiconductor metrology system including a spectrum acquisition tool for collecting, using a first measurement protocol, baseline scatterometric spectra on first semiconductor wafer targets, and for various sources of spectral variability, variability sets of scatterometric spectra on second semiconductor wafer targets, the variability sets embodying the spectral variability, a reference metrology tool for collecting, using a second measurement protocol, parameter values of the first semiconductor wafer targets, and a training unit for training, using the collected spectra and values, a prediction model using machine learning and minimizing an associated loss function incorporating spectral variability terms, the prediction model for predicting values for production semiconductor wafer targets based on their spectra.

Abstract: A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.