Testing Or Evaluating Patents (Class 716/136)
  • Patent number: 11182530
    Abstract: A computer-implementable method, a computing system, and a non-transitory computer-readable medium for automating workflow for routing metal wiring structures on an integrated circuit. The method automates, monitors, and controls all tasks for an auto-routing workflow. The method retrieves the auto-routing rules definition from a centrally stored location for easy maintenance. The method allows entry of wiring auto-routing constraints. The method enables customization per the design application to control signal integrity affected by the intrinsic routing metallization parasitic. The virtual copy of the layout database allows the layout database preparation without modifying the actual project layout. The virtual copy is used as an input for the workflow system. The method keeps the project layout database up to date.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 23, 2021
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Giuliano Fernandes Marinelli
  • Patent number: 11182528
    Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang, Jui-Feng Kuan
  • Patent number: 11169184
    Abstract: A method for measuring the intensity of a current, comprising the steps of obtaining a computation matrix M comprising a set of terms, proportional to a distance between a measuring point and a reference point, raised to a power higher than or equal to zero, forming a vector B including measurements of the value of the magnetic field in a direction at a measuring point, computing the components of a vector A, each component being a coefficient of a decomposition of the magnetic field into spatial harmonics proportional to the intensity of the current such that the matrix relation B=M×A is satisfied, and determining the intensity.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 9, 2021
    Assignees: INSTITUT POLYTECHNIQUE DE GRENOBLE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Orphée Cugat, Jérôme Delamare, Olivier Pinaud, Laure-Line Rouve, Benjamin Wilsch
  • Patent number: 11152237
    Abstract: A sample simulates a processing state of a semiconductor sample and is measured by a measurement device. The sample includes: a first surface formed at a first height when viewed from a sample surface; a second surface formed at a second height higher than the first height; and a plurality of inflow parts which allow a particle for performing processing on the first surface to flow between the first surface and the second surface. The processing by the particle flowing from the inflow parts is superimposed in at least a part of a region to be processed on the first surface, and the region where the processing is superimposed on the first surface is measured by the measurement device.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 19, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Hyakka Nakada, Takeshi Ohmori, Tatehito Usui, Masaru Kurihara, Naoyuki Kofuji
  • Patent number: 11144379
    Abstract: Modeling a multi-component control or actuator system using a fault tree is provided, which solves the problem of ring closures included in a fault tree. To identify ring closures, failure propagation paths are back-traced and is checked if the respective failure propagation path forms a ring closure.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 12, 2021
    Assignee: SIEMENS INDUSTRY SOFTWARE NV
    Inventors: Kai Höfig, Jonathan Menu, Marc Zeller
  • Patent number: 11121878
    Abstract: Methods, systems, and apparatus for authenticating and authorizing users using quantum key distribution through segmented quantum computing environments. In one aspect, a method includes receiving a first and second plaintext data input from a first party and from a second party, respectively; applying a quantum computation translation operation to the first and second plaintext data inputs to generate a corresponding first sequence of quantum computations and a second sequence of quantum computations; implementing the first and second sequence of quantum computations in a first and second segmented quantum computing environment, respectively, to obtain a first and second sequence of measurement results; generating a first and second encryption key using the first and second sequence of measurement results, respectively, and an encrypted authorization token using the second encryption key; and sending the first encryption key to the first party, and the encrypted authorization token to the second party.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Accenture Global Solutions Limited
    Inventors: Benjamin Glen McCarty, Ellie Marie Daw
  • Patent number: 11107209
    Abstract: An electronic device includes at least one processor, at least one memory storing a model based definition (MBD) representing a model of a part, and an artificial intelligence (AI) client service. The AI client service, in response to execution by the at least one processor, is configured to receive inspection data corresponding to a cut part being fabricated based on the model of the part, compare the received inspection data to the MBD to determine any deviations of the cut part from the MBD, determine whether the cut part is defective based on the comparison, and update a digital thread corresponding to the part when the cut part is determined to be defective.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 31, 2021
    Assignee: The Boeing Company
    Inventors: Iti Srivastava, Raviendra Sidath Suriyaarachchi, Benjamin Rennison
  • Patent number: 11093840
    Abstract: A semiconductor metrology system including a spectrum acquisition tool for collecting, using a first measurement protocol, baseline scatterometric spectra on first semiconductor wafer targets, and for various sources of spectral variability, variability sets of scatterometric spectra on second semiconductor wafer targets, the variability sets embodying the spectral variability, a reference metrology tool for collecting, using a second measurement protocol, parameter values of the first semiconductor wafer targets, and a training unit for training, using the collected spectra and values, a prediction model using machine learning and minimizing an associated loss function incorporating spectral variability terms, the prediction model for predicting values for production semiconductor wafer targets based on their spectra.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: August 17, 2021
    Assignee: NOVA MEASURING INSTRUMENTS LTD.
    Inventors: Eitan Rothstein, Ilya Rubinovich, Noam Tal, Barak Bringoltz, Yongha Kim, Ariel Broitman, Oded Cohen, Eylon Rabinovich, Tal Zaharoni, Shay Yogev, Daniel Kandel
  • Patent number: 11079685
    Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien Hsieh, Ru-Gun Liu, Wei-Shuo Su
  • Patent number: 11068636
    Abstract: A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonjae Hwang, Sungwook Moon
  • Patent number: 11055409
    Abstract: In one embodiment, a protected system, includes a first apparatus disposed on a silicon chip, and to perform a functional process, a second apparatus disposed on the silicon chip, and to perform a protecting process having a verifiable test result, the first and the second apparatus having a physical layout which interleaves at least part of the first apparatus with at least part of the second apparatus so that an attack on the at least part of the first apparatus also attacks the at least part of the second apparatus, a primary controller to signal the second apparatus to perform the protecting process during a time period that the first apparatus is performing the functional process, and an attack handling controller to perform a protective action to protect the functional process responsively to the protecting process failing to verify the verifiable test result providing an indication that the attack is being performed.
    Type: Grant
    Filed: January 6, 2019
    Date of Patent: July 6, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Ziv Hershman
  • Patent number: 11048852
    Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: June 29, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Elias Lee Fallon, Wangyang Zhang, Sheng Qian
  • Patent number: 11048483
    Abstract: An industrial integrated development environment (IDE) supports open or extensible application programming interfaces (APIs) that enable end users (e.g., plant asset owners, original equipment manufacturers (OEM), system integrators, etc.) to build upon the IDE's development platform to create custom views or to code custom functionality. This can include, for example, defining a control programming syntax supported by the industrial IDE, customizing a development environment view afforded by the IDE's interface, modifying or creating project editing functions, defining customized programming guardrails designed to guide compliance with in-house programming standards, or other such IDE customizations.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 29, 2021
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Ryan Dunn, Karl Staas, Andrew Stump, Anthony Carrara, Eashwer Srinivasan, Christopher Como, Sharon Billi-Duran
  • Patent number: 11036907
    Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 15, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Slimane Boutobza, Andrea Costa, Sorin Ioan Popa
  • Patent number: 10997137
    Abstract: Methods, systems, and computer-readable media for two-dimensional partition splitting in a time-series database are disclosed. Stream processor(s) write elements of time-series data to a first replica group of a first tile associated with a first set of spatial and temporal boundaries. A second replica group is initialized with the same boundaries. A control plane generates updated metadata for the first tile. The updated metadata indicates a modified first set of spatial and temporal boundaries for the first replica group associated with the first tile and a second set of spatial and temporal boundaries for the second replica group associated with a second tile. The modified first set represents a first portion of the first set, and the second set represents a second portion of the first set. The updated metadata is obtained by the stream processor(s) which write, to the second tile, time-series data within the second set of boundaries.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 4, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Dumanshu Goyal, Timothy A. Rath
  • Patent number: 10943051
    Abstract: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse Surprise, Gerald Strevig, III, Shawn Kollesar, Chris Aaron Cavitt, Chaobo Li, Dina Hamid, Christopher Berry
  • Patent number: 10929582
    Abstract: Circuits may be designed using computer aided design tools and may comprise a plurality of different possible variants of individual components. These multi-variant component circuits may be validated to identify potential problems by generating an aggregate parametric model for the multi-variant components and then using the aggregate parametric model in applying tests to different connection networks of the circuit definition.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Michael Alam
  • Patent number: 10908511
    Abstract: Systems and methods for multi-patterning in layout design data. A method includes receiving a coloring rule by a computer system. The method includes applying the coloring rule to the layout design data to identify a unique uncolored geometric element corresponding to the rule, by the computer system. The method includes, when the applied rule did not identify the unique uncolored geometric element corresponding to the rule, repeat the receiving and applying processes with a different coloring rule. The method includes, when the applied rule did identify the unique uncolored geometric element corresponding to the rule, assigning a patterning color to the unique uncolored geometric element, by the computer system.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 2, 2021
    Assignee: Mentor Graphics Corporation
    Inventor: Fedor G. Pikus
  • Patent number: 10909283
    Abstract: A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on a number of toggling netlists in each cluster for each clock cycle, and on the average toggle weight factor for each cluster, merging, with a compiler tool, the instrument logic with the circuit layout into an executable file for an emulator tool. The method includes evaluating the power consumption of the circuit layout with the emulator tool; and modifying the circuit layout when the power consumption of the circuit layout exceeds a pre-selected threshold.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 2, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Long Wang, Tsair-Chin Lin, Jingbo Gao
  • Patent number: 10867008
    Abstract: Embodiments of the present invention provide a hierarchical, multi-layer Jacobi method for implementing a dense symmetric eigenvalue solver using multiple processors. Each layer of the hierarchical method is configured to process problems of different sizes, and the division between the layers is defined according to the configuration of the underlying computer system, such as memory capacity and processing power, as well as the communication overhead between device and host. In general, the higher-level Jacobi kernel methods call the lower level Jacobi kernel methods, and the results are passed up the hierarchy. This process is iteratively performed until a convergence condition is reached. Embodiments of the hierarchical Jacobi method disclosed herein offers controllability of Schur decomposition, robust tolerance for passing data throughout the hierarchy, and significant cost reduction on row update compared to existing methods.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: December 15, 2020
    Assignee: NVIDIA Corporation
    Inventor: Lung-Sheng Chien
  • Patent number: 10866281
    Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Pin Changchien, Hong-Chen Cheng, Pei-Ying Lin, Hsin-Wu Hsu
  • Patent number: 10838006
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 17, 2020
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 10817671
    Abstract: Systems and methods for analyzing a large number of textual passages are described. A computing device receives the textual passages as input and generates a Raw Pair Distance (RPD) table. The device then determines a Node table and an Node-Node Distance (NND) matrix from the RPD table. An energy reduction process is used to generate an NSPACE matrix from the NND matrix. Finally, a 3D visualizer displays aspects of the Nodes table and the NSPACE matrix to a user. The systems and methods may enable a user to quickly search and understand the text relationships within the large number of textual passages.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 27, 2020
    Assignee: SAVANTX, Inc.
    Inventors: David Linus Ostby, Edmond Audrey Heinbockel
  • Patent number: 10815816
    Abstract: A propulsion system including a casing surrounding a fan rotor assembly is provided. The casing includes an outer layer material defining a first coefficient of thermal expansion (CTE) and an inner layer material. The casing further includes a spring member disposed between the outer layer material and the inner layer material coupling the outer layer material and the inner layer material. The spring member is coupled to each of the outer layer material and the inner layer material within a flow passage defined between the outer layer material and the inner layer material. The spring member defines a second CTE greater than the first CTE.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: October 27, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Nicholas Joseph Kray, Nitesh Jain, Manoj Kumar Jain
  • Patent number: 10796315
    Abstract: A method for automated recertification of a safety critical system with at least one altered functionality is provided. The method includes providing a failure propagation model of the safety critical system. The method also includes updating the failure propagation model of the safety critical system according to the at least one altered functionality using inner port dependency traces between inports and outports of a failure propagation model element representing the at least one altered functionality. The method includes calculating top events of the updated failure propagation model, and comparing the calculated top events with predetermined system requirements to recertify the safety critical system.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: October 6, 2020
    Assignee: Siemens Aktiengesellschaft
    Inventor: Kai Höfig
  • Patent number: 10783296
    Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: September 22, 2020
    Assignee: Diakopto, Inc.
    Inventor: Maxim Ershov
  • Patent number: 10776538
    Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Yuan Ting, Sandeep Kumar Goel, Yun-Han Lee, Mei Wong, Hsin-Cheng Chen
  • Patent number: 10769339
    Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ? ( F ˜ 1 , C ? 2 ? q ? E g ? N n ? e ? t ? ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 8, 2020
    Assignee: Synopsys, Inc.
    Inventors: Hiu Yung Wong, Rimvydas Mickevicius
  • Patent number: 10747259
    Abstract: Herein is disclosed a multichip reference logging system comprising a control circuit, configured to generate a reference signal; a first chip, configured to generate a first operations log, the first chip further comprising a first reference circuit, configured to receive the reference signal and to create a first reference event in response to the received reference signal; a memory associated with the first chip, configured to store the first reference event within the first operations log; a second chip, configured to generate a second operations log, the second chip further comprising a second reference circuit, configured to receive the reference signal and to create a second reference event in response to the received reference signal; and a memory associated with the second chip, configured to store the second reference event within the second operations log.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Intel IP Corporation
    Inventors: Uwe Schumacher, Peter Lachner, Andrej Tkalcec, Donald Korinke
  • Patent number: 10747433
    Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 18, 2020
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Jing Li, Jialiang Zhang
  • Patent number: 10706205
    Abstract: A method for detecting hotspots in physical design layout patterns includes receiving a given physical design layout pattern, utilizing a hotspot detection model to detect one or more potential hotspots in the given physical design layout pattern, and performing a verification to determine whether a given potential hotspot of the one or more potential hotspots detected by the hotspot detection model comprises a real hotspot or a nonexistent hotspot. The method also includes, responsive to determining that the given potential hotspot comprises an actual hotspot, modifying the given physical design layout pattern to remove the actual hotspot. The method further includes, responsive to determining that the given potential hotspot comprises a nonexistent hotspot, augmenting the hotspot detection model with additional training data generated based on the nonexistent hotspot.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dongbing Shao, Jing Sha, Kafai Lai
  • Patent number: 10698897
    Abstract: Systems and methods are disclosed for executing a distributed execution model with untrusted commands. The distributed execution model can be distributed to multiple nodes in a distributed computing environment. At least one node can process the distributed execution model to identify an untrusted command. The node can use data associated with the untrusted command to identify one or more files associated with the untrusted command. Based on the files, the node can generate a data structure, and execute at least a portion of the data structure.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: June 30, 2020
    Assignee: Splunk Inc.
    Inventors: Arindam Bhattacharjee, Sourav Pal, Alexander Douglas James
  • Patent number: 10684557
    Abstract: A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A functional relationship between local height deviations across a substrate and focus information, such as a determined focus amount, is determined for a substrate, e.g., a reference substrate. Height deviations are subsequently measured for another substrate, e.g. a production substrate. The height deviations for the subsequent substrate and the functional relationship are used to determine predicted focus information for the subsequent substrate. The predicted focus information is then used to control the lithographic apparatus to apply a product pattern to the product substrate.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: June 16, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Rene Marinus Gerardus Johan Queens, Emil Peter Schmitt-Weaver
  • Patent number: 10657303
    Abstract: This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 19, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao, Chien-Nan Liu, Yu-Kang Lou, Ching-Ho Lin
  • Patent number: 10657308
    Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sungjun Chun, Matteo Cocchini, Michael A. Cracraft
  • Patent number: 10620265
    Abstract: A method for real-time testing of a control unit with a simulator is provided. The simulator calculates a load current and a load voltage as electrical load state variables via converter control data and via an electrical load model that does not take into account current discontinuities caused by the converter, and transmits at least a portion of the load state variables to the control unit. A control observer is additionally implemented on the simulator that calculates at least the load current as a load state variable taking into account the converter control data and an observer load model. The observer detects a zero-crossing of the load current and a current discontinuity caused thereby from the calculated load current, and upon detection of a current discontinuity the observer calculates an electrical compensating quantity.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 14, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Quang Ha, Martin Aust, Frank Puschmann
  • Patent number: 10571514
    Abstract: A thermal transient response simulation is performed for a structure having a plurality of thermal model elements. The thermal transient response simulation determines a relation between transient thermal impedance of the structure and time and a relation between maximum temperature change of each of the thermal model elements and time. An onset time at which energy reaches each of the thermal model elements is determined based on the relation between maximum temperature change of each of the thermal model elements and time and a predetermined maximum temperature change threshold. An influence onset resistance value for each of the thermal model elements is determined by looking up a thermal resistance value corresponding to the onset time based on the relation between transient thermal impedance of the structure and time. A structural function is mapped based on the influence onset resistance value for each of the thermal model elements.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 25, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Byron Blackmore, Joseph Charles Proulx, Robin Bornoff, Andras Vass-Varnai
  • Patent number: 10546083
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: January 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Amit Verma, Suyash Kumar, Habeeb Farah
  • Patent number: 10542301
    Abstract: A multimedia redirection method comprising receiving, by a server, a hardware decoding capability sent by a client, where the hardware decoding capability is a hardware decoding capability that is in a video hardware acceleration specification and that is converted from a hardware decoding capability of a non-Windows operating system by the client; restoring, by the server, video data to a video code stream of a standard encoding format after receiving the hardware decoding capability; and sending, by the server, the video code stream to the client for decoding and display.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 21, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chong Chen, Yanping Meng
  • Patent number: 10528644
    Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 7, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu
  • Patent number: 10522329
    Abstract: A method for re-calculating a pattern to be exposed on a target by means of a charged-particle multi-beam writing apparatus is presented. The pattern elements of a pattern, initially associated with a respective assigned dose, are recalculated in view of obtaining reshaped pattern elements which have a nominal dose as assigned dose. The nominal dose represents a predefined standard value of exposure dose to be exposed for pixels during a scanning stripe exposure within the multi-beam apparatus.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 31, 2019
    Assignee: IMS Nanofabrication GmbH
    Inventors: Elmar Platzgummer, Christoph Spengler, Wolf Naetar
  • Patent number: 10515612
    Abstract: A system and method for operating a display. In some embodiments, the method includes: transforming a stress profile for a slice of the display, with a first transformation, to form a transformed stress profile; compressing the transformed stress profile to form a compressed transformed stress profile; decompressing the compressed stress profile to form a decompressed transformed stress profile; and transforming the decompressed transformed stress profile, with a second transformation, to form a decompressed stress profile, the second transformation being an inverse of the first transformation.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amin Mobasher, Shiva Moballegh, Jalil Kamali
  • Patent number: 10429442
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: October 1, 2019
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 10430411
    Abstract: Incrementally updating statistics includes sampling rows from a database column in a database to generate a first sample, sampling a subset of modified rows from the database column after generating the first sample to generate a second sample, determining whether distribution changes occurred to the database column based on the first and second samples, and updating a database statistic about the database column in response to determining that a distribution change exists.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 1, 2019
    Assignee: MICRO FOCUS LLC
    Inventors: Choudur Lakshminarayan, Ramakumar Kosuru, QiFan Chen, Hansjorg Zeller
  • Patent number: 10417361
    Abstract: Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael James Floyd, Philip Benedict Giangarra, Abu Nasser Mohammed Abdullah, Zhengang Hong, Joseph Ralph Horn
  • Patent number: 10365320
    Abstract: There is a need to improve estimation accuracy of a failure estimation method or its failure estimation apparatus that performs failure estimation on a targeted instrument based on history information about several instruments mounted with the same type of semiconductor device as an instrument targeted at failure estimation. A failure estimation apparatus that includes a history information database storing history information about a plurality of instruments mounted with the same type of semiconductor device and performs failure estimation on a targeted instrument mounted with a semiconductor device whose type equals the type, wherein the history information contains operation information and failure information; wherein the operation information indicates a chronological operating state of the semiconductor device mounted on the instruments; wherein the failure information indicates a failure cause of a failed instrument; and wherein the operating state is categorized into a plurality of classifications.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuji Takehara, Takeo Mimura, Tomohiro Oono
  • Patent number: 10365326
    Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two module representations of the plurality of module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the plurality of module representations, and the one or more connections. The test scenario model includes a path from the input via the plurality of module representations and the one or more connections to the desired output.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: July 30, 2019
    Assignee: Breker Verification Systems
    Inventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
  • Patent number: 10353916
    Abstract: In one embodiment, techniques are provided for converting a CAD description maintained in a first storage format (e.g., a file-based storage format) of a source repository to a second storage format (e.g., a relational database-based storage format) of an output repository. The techniques may, generate a single, coherent representation from spatially ambiguous “fragments” by generating an acyclic model graph for each graphical view, and then storing models of the acyclic model graph in the second storage format (e.g., the relational database-based storage format). The techniques may further produce a post-conversion CAD description that preserves human-readable names and information relationships related to levels by examining attachment specific copies of level structures (i.e. levels and attached levels) referenced from attachments, and generating from these categories and subcategories in the second storage format (e.g., the relational database-based storage format).
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 16, 2019
    Assignee: Bentley Systems, Incorporated
    Inventors: Keith A. Bentley, Samuel W. Wilson
  • Patent number: 10354045
    Abstract: An integrated circuit (IC) design is received. The IC design has devices on different layers electrically connected to each other by conductive vias extending between the different layers. Relative locations of the vias, and of conductive components of the devices within adjacent layers of the different layers, are identified. The conductive components that overlap redundant vias are also identified. This allows 2D via checker data, that is a combination of the 3D adjacent layers, to be generated. The 2D via checker data includes rectangular geometric shapes that represent each instance of the conductive components overlapping redundant vias. Thus, the 2D via checker data is output, and lack of rectangular geometric shapes in the 2D via checker data provides data of locations in the IC design that fail to have redundant vias.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Ahmed Abdelghany Alsayed Omara
  • Patent number: 10320494
    Abstract: An integrated circuit (IC) is provided. The IC includes an RF transmitter and an RF receiver. The RF transmitter is configured to generate an RF signal in response to an analog test signal from a test signal generator of a module circuitry that is external to the IC. The RF receiver is configured to generate an outgoing signal according to an input RF signal, and to report the outgoing signal to the module circuitry. The module circuitry performs a test analysis on the RF signal generated by the RF transmitter or on the outgoing signal generated by the RF receiver to determine a test result. The test result is reported to a test equipment having no RF instruments.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 11, 2019
    Assignee: MEDIATEK INC.
    Inventors: Yuan-Hwui Chung, Chung-Chin Tsai, Ping-Hsuan Tsu, Chun-Hsien Peng