Abstract: A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

Abstract: An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient voltage droops in the power-supply network of the integrated circuit to be sufficiently small to ensure proper and reliable operation of the integrated circuit.

Abstract: One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.

Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

Abstract: A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

Abstract: In one aspect, a technique for performing signal activity extraction in an integrated circuit an integrated circuit is described. The integrated circuit includes multiple nodes. The technique includes compiling a design of the integrated circuit, estimating signal activities at the nodes, determining a node of interest from the nodes, and connecting a signal activity circuit to the node of interest. The determination of the node of interest and the connection of the signal activity circuit to the node of interest first compared to the remaining nodes of the integrated circuit improves efficiency in determining nodes of the integrated circuit at which signals can be analyzed first. Such signal activity extraction may involve power analysis and power optimization.

Abstract: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (?) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: An analysis support apparatus includes a processor that is configured to acquire circuit data that indicates plural elements within a circuit and a node to which at least two elements are connected among the elements, and determine, based on the acquired circuit data and by referring to a memory unit that correlates and stores for each of the elements, the type of the element and information that indicates whether the phase of a signal is reversed when the signal passes through the element, whether the phase of the signal is reversed when the signal that passed through a given node among a plurality of nodes within the circuit returns to the given node; and an output unit that outputs information that indicates the given node when the processor determines that the phase of the signal is not reversed.

Abstract: An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.

Abstract: An object of the present invention is to provide wiring board design system and wiring board design method to determine a component and a wiring pattern in real-time when designing a wiring on a circuit board. The wiring board design system provides a cloud service for a terminal which is used by users via a network. When to arrange components on the circuit board, while pushing out automatically wirings which are overlapped with the components on the arranging position, the wiring board design system secures a space on that can arrange the component. The wiring processing is performed automatically and the fine adjustment such as rotation, movement of arranged components is performed automatically if necessary. The processing for equalization is performed so as to be the equal wiring density on the circuit board.

Abstract: Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration analysis on the design. In one implementation, an intelligent connectivity may be applied to the hierarchical extraction to achieve an approximate location of the connection points between the blocks of the design. In one example, the intelligent connectivity technique may utilize a coordinate grid related to the design to approximate the connection points between the blocks of the design.

Abstract: A first signal is transmitted through a first path. A computing device determines a signal propagation time of the first signal. The computing device transmits a second signal through a second path, wherein the second path includes the second signal traversing across at least one interconnecting structure. The computing device determines a signal propagation time of the second signal. The computing device determines a propagation time difference between the signal propagation time of the first signal and the signal propagation time of the second signal. The computing device adjusts a clock based on the determined propagation time difference.

Abstract: An apparatus includes a memory device that includes instructions for analyzing RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The instructions can include receiving RTL code, and identifying a statement in the RTL code. The instructions can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The instructions can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The instructions can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.

Abstract: A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified. Additionally, the callback function is recursively applied to the plurality of data values in order to determine a result. Further, the result is returned.

Abstract: A system, method, and computer program product are provided for translating a hardware design. In use, a hardware design is received that is encoded as one or more data flows and one or more control constructs. A node is generated for each data flow of the one or more data flows and for each control construct of the one or more control constructs. Additionally, connectivity of the nodes is determined to generate a graph-based intermediate representation of the hardware design and the graph-based intermediate representation of the hardware design is stored in a source database.

Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Abstract: Systems and methods for generating compact models that include the effects of physical and electrical variations independent of available hardware data. A method includes generating a physics-based model using a technology computer-aided design (TCAD) of the one or more devices in a technology node. The method further includes deriving electrical parameters for the one or more devices from the physics-based model. The method further includes generating the compact model based on the derived electrical parameters.

Abstract: Burn-in (BI) stress using stress patterns with pin-specific power characteristics. A control device for each conductive pathway from BI board (BIB) contacts to device under test (DUT) connectors/contacts can adjust power delivered to a respective connector/contact responsive to a controller. The control devices can be included in the BIB or an interposer (IP) can be used with existing equipment. Each control device can include a regulator, such as a latchable array of field effect transistors that can regulate power delivered to a respective package connector.

Abstract: Techniques and a system for creating a vendor independent computer language and compiling the language into an architecture specification language allowing for taking a source data stream (file, WSDL, XML) and passing thru a language parser, populating a storage medium with a plurality of technical inputs and vendor technical specifications for generic technologies and probable technologies required for desired architectures generated by the language parser, and optimizing the inputs and creating relationships between technologies and groups of technologies and storing results in the storage medium.

Abstract: An energy consumption simulation and evaluation system for embedded device in energy consumption evaluation technology for electronic devices, which solves the problem that the energy consumption cannot be simulated under tasks operation condition with the existing systems.

Abstract: A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector value is calculated based, at least in part, on a plurality of criteria vectors of the benchmark circuits. A shift is applied on each of the groups by the tuning vector value and a technology file, such as a 2.5 dimensional RC techfile, is regenerated.

Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.

Abstract: Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.

Abstract: An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the circuit design with a fault in the analog portion of the circuit design, simulating the circuit design with the fault for a fault interval time period, and determining whether the fault is detectable.

Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.

Abstract: Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A method of detailed placement for ICs is provided. The method receives an initial placement and iteratively builds sets of constraints for placement of different groups of cells in the IC design and uses a satisfiability solver to resolve placement violations. In some embodiments, the constraints include mathematical expressions that express timing requirements. The method in some embodiments converts the mathematical expressions into Boolean clauses and sends the clauses to a satisfiability solver that is only capable of solving Boolean clauses. In some embodiments, the method groups several cells in the user design and several sites on the IC fabric and uses the satisfiability solver to resolve all placement issues in the group. The satisfiability solver informs placer after each cell is moved to a different site. The method then dynamically builds more constraints based on the new cell placement and sends the constraints to the satisfiability solver.

Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.

Abstract: As consistent with one or more embodiments, electronic circuitry is characterized to provide an indication of susceptibility of the circuitry to error. As consistent with one or more embodiments, bits corresponding to a circuit component of a circuit design are evaluated using a software program that characterizes a hardware description language representing the circuit components and their interconnectivity. A noise power value is calculated for each bit, and bits are identified as being susceptible to data error based upon the noise power value and a signal-to-noise (SNR) ratio reference value. A characterization of the circuit components (e.g., a quality factor) is provided based upon a number of bits susceptible to data errors.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Abstract: Systems and methods of using hardware to simulate software, specifically the semantic operations defined in HDL simulation languages. Traditional software HDL simulation kernel operations of advancing time, activating threads in response to notified events, and scheduling those threads of execution are handled via a simulation controller. The simulation controller is comprised of a timing wheel, an event-processor, a thread/process dispatch engine, a token processor, and a resource-allocator. These components work together with a control logic component to perform the semantic operations of an HDL software kernel.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: The present invention may comprise an apparatus and method for calculating power consumption, including a unit for generating a clock-level analysis without synthesis of an algorithm description and calculating operating ratios of storage elements and arithmetic units. The invention may also comprise a method for estimating the power to be consumed by a SystemC model. By estimating this value, a user may gauge the amount of power a specific semiconductor design might consume, once manufactured into a chip.

Abstract: Coexistence of multiple types of verification components in a single verification framework is provided. Particularly, the coexistence of proprietary e verification components in an open verification methodology framework is provided.

Abstract: A system and a method are disclosed for concurrently simulating multiple parameters of a design of an electrical circuit. A first simulation time and a first set of environmental parameters is determined and the design is simulated for the determined first simulation time. Multiple simulation engines, each analyzing on simulation parameter, simulate the design based on the first set of environmental parameters and the first set of environmental parameters are updated based on the results of each of the simulation engines. A determination is made whether the simulation results have converged. If the simulation results have not converged, each of the analysis engines simulated the design using the updated set of environmental parameters. If the simulation results are determined to be convergent, the simulation system determines a second simulation time and repeats the simulation process for the second simulation time.

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract: A method for checking the inter-chip connectivity of a three-dimensional (3D) integrated circuit (IC) generally comprises receiving a design file for each of a plurality of chips of the 3D IC and generating a plurality of inter-layer ports to be shared between at least two of the of chips based on the design files for each of the chips. A layout without the share ports for each of the chips based on the design files for each of the chips is generated and a layout versus schematic (LVS) check is conducted for each of the generated layouts by using the identified inter-layer ports.

Abstract: Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.

Abstract: A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical.

Abstract: Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling.

Abstract: A configuration system, method, and software program is provided for enabling users to create and use rule patterns to generate custom product-configuration rules. The method includes enabling a designer to submit example rules or template rules for a rule pattern. The designer is then able to select which variables will be customizable in instances of the rule pattern. A modeler is able to select the rule pattern from a rule pattern library as a basis for creating custom configuration rules for a product. In response to the modeler selecting the rule pattern from the library, a user interface is generated in which the customizable fields for each template rule in the rule pattern are displayed and the modeler is able to enter values for the customizable fields. Configuration rules are then generated for the product from the template rules and the values entered by the modeler for the customizable fields.

Abstract: An approach for methodology, and an associated system, enabling a prioritizing of devices, circuits, and modules of interest is disclosed. Embodiments include: determining a first electrical layout indicating an electrical performance of a physical layout of an IC design, the first electrical layout indicating a plurality of devices of the physical layout; selecting a subset of the plurality of the devices based on one or more connections of the devices; and generating a second electrical layout indicating the electrical performance of the physical layout, the second electrical layout indicating the selected devices without at least one of the plurality of devices.

Abstract: Methods, systems, and techniques for estimating a transient diffusion potential of a diffusive property involve modeling, as a circuit, diffusive behavior of a diffusion region and then simulating operation of the circuit to estimate the transient diffusion potential at a location in the diffusion region by determining circuit potential at a node in the circuit that corresponds to the location in the diffusion region. The circuit has steady-state and transient portions that model the steady-state and transient behavior of the diffusion region, respectively. The transient behavior is modeled using a capacitive circuit element. The diffusive property diffuses linearly within the diffusion region and generation of the diffusive property is distributed within the diffusion region.

Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.