Abstract: A method for making an electromagnetic band gap structure includes performing a single full wave simulation for the structure using a computer to perform the simulation, extracting a multiple port scattering matrix based on the single full wave simulation using a computer, and measuring or estimating a transmission of waves across the body between a first port and a second port of the body. The body has multiple ports between the first port and the second port that are defined by scattering elements using the computer. The matrix may be reduced to a two by two matrix recursively one dimension at a time using the computer.

Abstract: A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

Abstract: There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit part 1 as seed points 3, projecting a specifically designed polygon shape 4 proximal to a seed point 3 and calculating an overlap area 5 between the projected polygon shape 4 and a second circuit part 2. The layout is rejected when the overlap area does not conform to a threshold overlap area determined by the design intent.

Abstract: A method performed by at least one processor comprises the steps of: generating a layout data of a chip comprising transistors; determining heat-related parameters for the transistors based on the locations thereof in the layout data; generating a netlist data comprising the heat-related parameters; performing a post-layout simulation based on the netlist data; and verifying whether the post-layout simulation meets a design specification.

Abstract: Examples for performing static timing analysis on clocked circuits are described. An example static timing analysis computing device includes a logic device, and a storage device holding instructions executable by the logic device, the instructions including instructions executable to receive an input representative of one or more delays within a signal path in a cross-domain circuit, the cross-domain circuit configured to transfer data between a first domain having a first clock and a second domain having a second clock asynchronous with the first clock, receive an input representative of a static timing analysis constraint to be met by a signal traveling the signal path in the cross-domain circuit, apply the constraint in a static timing analysis of the signal path in the cross-domain circuit, and output a result based upon applying the static timing analysis constraint.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist.

Abstract: Aspects of the disclosed techniques relate to techniques of layout decomposition for multiple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified by repeatedly applying a plurality of graph simplification units. Each of the graph simplification units is configured to use a unique approach to simplify a graph. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed.

Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: An electronic apparatus includes a user interface to receive an input selecting a plurality of circuit devices, a storage to store electrical current information and a Scattering parameter regarding input/output ports of the plurality of circuit devices, respectively, a calculator to calculate impedance per number of de-coupling capacitors based on the stared S-parameters and to calculate an accumulated noise value per number of the decoupling capacitors based on the calculated impedance and the electrical current information, and a controller to determine a number of the de-coupling capacitors based on the calculated accumulated noise values and to control the user interface to display the determined number of the de-coupling capacitors.

Abstract: A computer program product for implementing a scan chain to test a semiconductor including one or more computer-readable storage media and program instructions stored on the one or more computer-readable storage media, the program instructions including: program instructions to obtain an initial structure of the scan chain, program instructions to determine, according to function modules of the semiconductor corresponding to scan registers on the scan chain, at least one scan register pair with backward dependency, program instructions to adjust the initial structure of the scan chain such that the at least one scan register pair with backward dependency becomes a scan register pair with forward dependency, and program instructions to determine a key subset of a fan-out scan register in the at least one scan register pair with backward dependency.

Abstract: Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver.

Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

Abstract: A software test apparatus and a software test method and a computer readable medium thereof are provided. The software test apparatus stores a software testing program, an under-tested code, a plurality of basic test benches and a plurality of candidate test benches. The under-tested code includes a hard-to-detect code and the hard-to-detect code has at least one hard-to-detect section. The software test apparatus runs the software testing program to execute the following operations: parsing the hard-to-detect code to generate a condition-statement tree; based on the basic test benches and the condition-statement tree, using a support vector machine (SVM) to establish a support vector regression (SVR) predictor; and applying the SVR predictor to choose a best candidate test bench from the candidate test benches.

Abstract: A method and apparatus for adaptively tuning an integrated circuit are disclosed. For example, an integrated circuit (IC) comprises a monitored path comprising circuit elements operating on a clock signal, where a last circuit element of the circuit elements comprises a first flip flop. The IC also comprises a second flip flop operating on an early clock signal, where the early clock signal is phase shifted from the clock signal, and where the second flip flop is coupled to the monitored path prior to the last circuit element. The IC also comprises a transition detection module for detecting when an output from the first flip flop toggles, and an error prediction module to detect a potential error on the monitored path. The IC comprises a controller that is configured to scale a voltage or a frequency of the IC.

Abstract: An application-specific integrated circuit (ASIC) is provided. The ASIC includes a group of non-configurable circuits customized for performing operations for a particular use. The ASIC also includes a set of reconfigurable circuits for configurably performing a set of operations based on configuration data. The ASIC also includes a configuration and monitoring network that receives a set of signals from the non-configurable circuits of the ASIC. The configuration and monitoring network also receives incremental sets of configuration data while the ASIC is performing operations of the user design. Each incremental set of data is used for reconfiguring the configuration and monitoring network (i) to monitor one or more signals in the set of signals and (ii) to take a set of actions when values of the monitored signals satisfy a condition.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmed to provide test patterns and an interface to at least one device under test (DUT). The system also includes a connection to the at least one DUT, wherein the connection is coupled directly between the configurable IC and the at least one DUT.

Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.

Abstract: A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable.

Abstract: Systems and methods of data analytics, which in various embodiments enable business analysts to apply certain machine learning and analytics algorithms in a self-service manner by binding them to generic business questions that they can be used to answer in particular domains. The general approach may be to define the application of an algorithm to solve specific problems (questions) for particular combinations of a business domain and a data category. At design time, the algorithm may be linked to canonical data within a data category and programmed to run with this canonical data set. At runtime, given a dataset and its category, and a business domain, a user may choose from the corresponding questions and the system may run the algorithm bound to that question.

Abstract: A method, system and non-transitory computer readable storage medium for coverage determination of DUT tests. The method may include obtaining via an input device a selection of a subset of interest of coverage reports included in one or a plurality of saved merged coverage reports. The method may further include using a processing unit, finding a saved merged coverage report of said one or a plurality of saved merged coverage reports that has the smallest number of unwanted coverage reports. The method may also include using the found saved merged coverage report to obtain a merged coverage report that corresponds to the subset and merging the merged coverage report with the newly gathered coverage reports into a new merged coverage report.

Abstract: A system and method for operating a many-core processor including resilient cores may include determining a frequency variation map for the many-core processor and scheduling execution of a plurality of tasks on respective resilient cores of the many-core processor in accordance to the frequency variation map.

Abstract: A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.

Abstract: The present invention provides a method and system for automatic verification of automatically generated standalone code intended for execution on a target computing platform against its original design simulated in a simulation environment. The present invention also applies to execution comparisons between two implementations, such as two simulations, one simulation and one standalone code implementation, or two standalone code implementations. Block diagrams can be used to create a comparison model that compares two implementations. The comparison of different implementations can be performed at a block level, a subsystem level, a model level, or multi-model level. The present invention allows automatic comparison once a user supplies the intermediate outputs and/or signals that the user wants to compare and monitor. Reports can be generated to show the statistics of the comparison results.

Abstract: A synchronous circuit comprises a functional circuitry and one or more validation circuits for validating synchronization of the functional circuitry. The functional and the validation circuits are clocked by a clock source. Each validation circuit comprises a clock distribution network, a test signal generator, a capture cell, a test signal path from the test signal generator to the capture cell, and a verification unit. The clock distribution network applies a launch clock signal at the test signal generator and a capture clock signal at the capture cell. The test signal generator produces a bi-level test signal. The test signal path transmits the test signal to the capture cell, which generates a proof sequence by sampling the test signal. The verification unit determines whether the proof sequence is identical to the test sequence. A method of designing a synchronous circuit and method of validating a synchronous circuit are also described.

Abstract: A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.

Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.

Abstract: The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.

Abstract: Techniques and a system for creating a vendor independent computer language and compiling the language into an architecture specification language allowing for taking a source data stream (file, wsdl, xml) and passing thru a language parser, populating a storage medium with a plurality of technical inputs and vendor technical specifications for generic technologies and probable technologies required for desired architectures generated by the language parser, and optimizing the inputs and creating relationships between technologies and groups of technologies and storing results in said storage medium.

Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.

Abstract: A design layout generating method is provided. A design layout including a first pattern and a second pattern is provided to a computer system, wherein the first pattern and the second pattern meet a design rule of an integrated circuit, respectively. The first pattern and the second pattern are combined into a third pattern. Next, the third pattern is checked if it meets a definition of a weak pattern, wherein the weak pattern is a pattern that meets the design rule but still forms defects. Then, the third pattern is modified and a new design layout is generated.

Abstract: A method comprises generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also comprises generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further comprises selecting a layout generation configuration for generating the layout of semiconductor components. The method additionally comprises generating the layout of semiconductor components based on the selected layout generation configuration.

Abstract: Aspects of the invention relate to techniques for classifying memory failure bitmaps using both rule-based classification and artificial neural network-based classification methods. The rule-based classification method employs classification rules comprising those for global failure patterns. The artificial neural network-based classification method classifies local failure patterns. One of the artificial neural network models is the Kohonen self-organizing map model. The input vector for a failure pattern may contain four elements: pattern aspect ratio, failing bit ratio, dominant failing column number and dominant failing row number.

Abstract: Embodiments relate to systems and methods for application development using middleware. A developer can launch a development request from a client or local network to a remote development server, thereby invoking a set of frameworks and other tools to carry out a desired application build. The development request can specify the type or configuration of the desired application, such as, for example, email, spreadsheet, media playback, or other applications, along with parameters such as target operating systems. The user can assemble desired code from libraries stored in the virtualized middleware framework, and debug the application build against a set of data sources aggregated by the development server. A developer can therefore leverage rapid application development tools at the middleware, without a necessity to invest in local development tools or separately build or locate test data sources.

Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Abstract: A method and apparatus for power delivery network (PDN) analysis comprises obtaining time-domain single-pulse current response of the PDN, computing a maximum transient simultaneous switching noise (SSN) of the PDN according to the time-domain single-pulse current response, and determining that noise performance of the PDN conforms to a design requirement of the PDN if the maximum transient SSN is less than a PDN SSN threshold. Transient characteristics of the PDN can be analyzed.

Abstract: To improve a delay fault coverage without increasing an area overhead, provided is a scan test circuit including: scan flip-flops forming a clock domain that operates according to the same clock within a semiconductor integrated circuit including a target of a delay fault test; a test pattern generation mode control unit (scan flip-flop) that is supplied with the same clock as that supplied to the scan flip-flops, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and a scan enable signal output unit (OR gate) that outputs a first scan enable signal, which is determined based on the test pattern generation mode, to the scan flip-flops.

Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

Abstract: Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.

Abstract: Described herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.

Abstract: A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

Abstract: Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

Abstract: A slew-based effective capacitance (Ceff) is used to compute gate output slew during early synthesis of an integrated circuit design. A ? model is constructed for the gate and reduced to two parameters which are used to compute a slew value for the model, given a slew definition. A capacitance coefficient is then calculated as a function of this slew value. The effective capacitance is the product of the coefficient and the total capacitance of the ? model. The output slew of the gate may in turn be computed using the slew-based Ceff. The coefficient may be computed by iteratively solving an equation representing output voltage over time dependent on the first and second parameters, by directly solving a closed-form equation which is a function of the first and second parameters, or by looking up the capacitance coefficient in a table indexed by the first and second parameters.

Abstract: Disclosed is a technique for modeling resistance of a conductive component of a device, where the component comprises multiple conductive materials. If necessary (e.g., for a complex conductive component), the component is divided into multiple conductive regions. For a given conductive region, current flow-through and current flow-in-and-terminate axes are determined and the conductive region is divided into layers. Relative electric currents flowing along the current flow-through axis in each layer and along the current flow-in-and-terminate axis in each layer are evaluated to determine a total resistance value for the conductive region.

Abstract: A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

Abstract: A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

Abstract: A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist.

Abstract: The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.

Abstract: A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors.