Abstract: A method, computer program product, and/or system is disclosed for testing integrated circuits, e.g., processors, that includes: generating a software design prototype of the functional behavior of an integrated circuit to be tested; creating a lab All-Events-Trace (AET) normalized model of the integrated circuit, wherein the normalized model captures the functions of the integrated circuit and not the non-functional aspects of the integrated circuit; generating a lab scenario using the software design prototype and the AET normalized model of the integrated circuit for a particular cycle of interest, wherein the lab scenario contains initialization for all signals that have hardware information; and generating a replayed lab normalized AET for the particular cycle of interest.

Abstract: Embodiments described herein are directed to a microarchitecture modeling tool configured to model and analyze a microarchitecture using a dependency graph. The dependency graph may be generated based on an execution trace of a program and a microarchitecture definition that specifies various features and/or characteristics of the microarchitecture on which the execution trace is based. The dependency graph includes vertices representing different microarchitectural events. The vertices are coupled via edges representing a particular dependency therebetween. The edges are associated with a cost for performing microarchitectural event(s) corresponding to the vertices coupled thereto. The dependency graph also takes into account various policies for structural hazards of the microarchitecture. The microarchitecture modeling tool analyzes the costs associated with each of the edges to determine a design metric of the microarchitecture.

Abstract: A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

Abstract: Analysis of power supply noise in simulations of a design of a circuit can use per instance dynamic voltage drops (DVD) in timing analyses so that the simulated DVD values on a per victim cell basis can accurately guide the timing analysis on each victim instead of a global DVD for all victims during the timing analysis. In one embodiment, a method can: determine, during a power analysis simulation, a representation of an energy lost, during each switching window at each output of each victim cell, at one or more power supply rails of each of the victim cells in the set of victim cells due to aggressors in the design; and provide the representation of the energy lost separately for each victim cell to a timing analysis system. The representation can be a rectangle having a width defined by a switching window of a victim's output.

Abstract: Embodiments include dynamic control of coverage by a verification testbench. Aspects include obtaining a design under test to be verified by the verification testbench and obtaining one or more testcases for execution by the verification testbench on the design under test. Aspects also include obtaining a plurality of triggers corresponding to the design under test, wherein each of the plurality of triggers includes an activation condition, a deactivation condition and a coverage. Aspects further include simulating, by the verification testbench, execution of the one or more testcases by the design under test. Based on detecting the activation condition of one of the plurality of triggers, aspects also include recording, in a coverage database, data specified in the coverage corresponding the one of the plurality of triggers until the deactivation condition is detected.

Abstract: A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

Abstract: On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

Abstract: A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Abstract: A method for simulating a circuit represented by a top circuit and a plurality of subcircuit instances (SCIs) forming a hierarchy under the top circuit. The method comprises, during an iteration round of one or more iteration rounds, obtaining respective circuit equation parameters for each respective SCI of the plurality of SCIs in a bottom-up process, in which at least some of the circuit equation parameters for a parent SCI are obtained using a portion of the circuit equation parameters for a child SCI of the parent SCI. The method further comprises determining respective signal values of each respective SCI of the plurality of SCIs in a top-down process, where, for each child SCI having internal nets, signal values at internal nets of the child SCI are obtained using one or more signal values determined for a parent SCI and corresponding to one or more signal values at external ports of the child SCI.

Abstract: Methods, systems and media for simulating or analyzing voltage drops in a power distribution network can use an incremental approach to define a portion of a design around a victim to capture a sufficient collection of aggressors that cause appreciable voltage drop on the victim, and then an incremental simulation of just the portion can be performed rather than computing simulated voltage drops across the entire design. This approach can be both computationally efficient and can limit the size of the data used in simulating dynamic voltage drops in the power distribution network. Multiple different portions can be simulated separately in separate processing cores or elements. In one embodiment, a system can provide options of user selected constraints for the simulation to provide better accuracy or use less memory. Better accuracy will normally use a larger set of aggressors for each victim at the expense of using more memory.

Abstract: The control circuit includes a signal indication circuit, a control/isolation circuit, and an energy storage circuit; the signal indication circuit is a logic AND gate circuit, has an input end connected to multiple paths of power-down monitoring signals and an output end connected to an input end of the control/isolation circuit, and when a level of any path of power-down monitoring signal is low, outputs a low level to the control/isolation circuit; an output end of the control/isolation circuit is connected to an enable end of a Direct Current (DC) power chip, and the control/isolation circuit controls and isolates an output signal of the signal indication circuit by means of two-stage Metal-Oxide-Semiconductor (MOS) transistors; and an output end of the energy storage circuit is connected to the control/isolation circuit to provide reserve power for operation of the MOS transistors of the control/isolation circuit.

Abstract: A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.

Abstract: A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.

Abstract: Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.

Abstract: Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application may be retrieved on-demand.

Abstract: An excitation source planning method for an electrical stimulation is proposed to plan an excitation source. A layout importing step is performed to drive a processing unit to import a PCB layout to an electromagnetic simulation software module. A port establishing step is performed to set the excitation source to be vertically disposed between a signal layer and a main ground layer. A model generating step is performed to perform the electrical simulation according to the excitation source to generate a three-dimensional simulation model corresponding to the PCB layout. When the signal layer is not electrically connected to the main ground layer, the electromagnetic simulation software module executes an extending step. The extending step is performed to provide a first metal unit to be connected to the signal layer, and reset the excitation source to be vertically disposed between the first metal unit and the main ground layer.

Abstract: Implementing a design for a heterogeneous device can include mapping, using computer hardware, a plurality of applications of a design for a device to a plurality of domains of the device, wherein each domain includes a different compute unit, performing, using the computer hardware, validity checking on the plurality of applications, detecting, using the computer hardware, a conflict between two or more of the plurality of applications from the validity checking, and, in response to the detecting, generating a notification of the conflict using the computer hardware. Operations such as automatically generating a boot image, debugging, and/or performing system level performance analysis may also be performed.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

Abstract: An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

Abstract: Methods and systems for automated testing of extremely-high frequency devices are disclosed. A device under test (DUT) is set in a simultaneous transmit and receive mode. The DUT receives a lower frequency radio frequency (RF) signal from a test unit and up-converts the lower frequency RF signal to a higher frequency RF signal. The DUT transmits the higher frequency RF signal using a first antenna, and receives the higher frequency RF signal using a second antenna. The DUT down-converts the received higher frequency RF signal to a received test RF signal and provides the received test RF signal to the test unit for comparing measurements derived from the received test signal to a design specification for the DUT.

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.

Abstract: This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes.

Abstract: A method for analyzing an analog circuit controlled by a plurality of digital inputs is presented. The circuit is represented with a data structure with nodes connected via edges, which represent a circuit component. The data structure can be traversed across all connected nodes; and said digital inputs can be toggled between two or more input states. The method steps include identifying a set of boundary nodes in the data structure which are at a digital-analog boundary of the data structure; for each digital input, identifying associated boundary nodes which are coupled with the digital input; grouping digital inputs into input sets, where each of the different input sets are associated with mutually exclusive sets of associated boundary nodes, and analyzing the circuit by successively analyzing one or more of the input sets for all possible combinations of inputs states within that set.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: A system having design tools and methods for using the same in designing an integrated circuit (IC) are described.

Abstract: An IC is provided. The IC includes a plurality of a plurality of P-type fin field-effect transistors (FinFETs). The P-type FinFETs includes at least one first P-type FinFET and at least one second P-type FinFET. Source/drain regions of the first P-type FinFET have a first depth, and source/drain regions of the second P-type FinFET have a second depth that is different from the first depth. A first semiconductor fin of the first P-type FinFET includes a first portion and a second portion that are formed by different materials, and the second portion of the first semiconductor fin has a third depth that is greater than the first depth.

Abstract: A Toffoli magic state to be injected in preparation of a Toffoli gate may be prepared using a bottom-up approach. In the bottom-up approach, computational basis states are prepared in a fault tolerant manner using a STOP algorithm. The computational basis states are further used to prepare the Toffoli magic state. The STOP algorithm tracks syndrome outcomes and can be used to determine when to stop repeating syndrome measurements such that faults are guaranteed to be below a threshold level. Also, the STOP algorithm may be used in growing repetition code from a first code distance to a second code distance, such as for use in the computational basis states.

Abstract: A database stored electrical signatures of mounting points for generic modules within a vehicle model. Software for programming each mounting point is mapped to the mounting points. For a production unit of the vehicle model, generic modules are placed at the mounting points without being programmed to perform a specific function. The generic modules measure the electrical signature of the mounting point at which they are mounted. The generic modules then coordinate with a server to identify a matching electrical signature in the database and programming the generic modules with corresponding software for performing specific functions.

Abstract: A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

Abstract: A circuit comprising a first processing element having a first output configured to couple to a voltage control circuit, a second output configured to couple to a gate terminal of a first transistor, and a third output configured to couple to a first node and a control circuit. The control circuit comprises a second processing element having multiple outputs, a second transistor having a gate terminal configured to couple to one of the outputs of the second processing element, a first terminal configured to couple to a second node and to a drain terminal of the first transistor, and a second terminal, and a third transistor having a gate terminal configured to couple to a second of the outputs of the second processing element, a first terminal configured to couple to a third node, and a second terminal.

Abstract: A logic simulation verification system designates a change timing designation unit configured to designate a reference signal and a change timing and calculate a first time for which there is a possibility that a first signal to be assigned to a variable described in a library, a circuit description, and a test bench is changed in accordance with the reference signal. The system calculates a second time for which there is a possibility that a second signal assigned a variable described in the library, the circuit description, and the test bench will be checked in accordance the reference signal and then determines whether different circuits for which first signals are the same have first times that match. The system also determines whether a first time and a second time match with each other when a first signal of one circuit and a second signal of another circuit are the same.

Abstract: Capturing and processing a digital image of a pictorial (e.g., hand-drawn) representation of a schematic or block diagram as a digital image to aid in creation and maintenance of electrical designs is disclosed. Processing of the digital image includes processing to determine design parameters to create an informational format useful as input to other design software. Design parameters may include schematic layout and attributes such as maximum output voltage, minimum input voltage, ambient temperature, etc. The method and system also include storage of information accessible to refine designs and perform simulations of designs as part of an overall electrical design process. Associated devices and methods are disclosed as well.

Abstract: An example method includes controlling a switching order of a plurality of power switches. The power switches are coupled to a flying capacitor and include parasitic bipolar transistors susceptible to the voltage overstress in response to excess stray inductance of the flying capacitor. The method further includes, in response to the controlled switching order, converting an input voltage of a first voltage level to an output voltage of a second voltage level while mitigating the voltage overstress of the parasitic bipolar transistors of the plurality of power switches.

Abstract: The present disclosure provides a measurement method for a contact resistance of a transistor test device and a computer-readable medium. The measurement method includes: providing multiple transistor test devices, where the transistor test devices each include a source, a drain, an active layer, a gate located at the active layer, and wires connected to the source and the drain, widths of gates, channel region lengths of active layers, and quantities of connected wires of the transistor test devices are the same, and widths of the active layers of the transistor test devices are different; obtaining multiple total resistances of the transistor test devices by measuring the transistor test devices; and determining contact resistances of the transistor test devices based on the multiple total resistances and the widths of the active layers matching the total resistances.

Abstract: A method for generating a program to run on multiple tiles. The method comprises: receiving an input graph comprising data nodes, compute vertices and edges; receiving an initial tile-mapping specifying which data nodes and vertices are allocated to which tile; and determining a subgraph of the input graph that meets one or more heuristic rules. The rules comprises: the subgraph comprises at least one data node, the subgraph spans no more than a threshold number of tiles in the initial tile-mapping, and the subgraph comprises at least a minimum number of edges outputting to one or more vertices on one or more other tiles. The method further comprises adapting the initial mapping to migrate the data nodes and any vertices of the determined subgraph to said one or more other tiles.

Abstract: A power profile for an electronics design is implemented by accessing a unit descriptive of an electronic design comprising a first intellectual property (IP) block expressed in a simulation language and comprising a netlist. A total number (NT) of net weights are identified in the netlist, wherein each respective net weight is proportional to an effective load capacitance of an associated net. A total number (NP) of populated nets having associated toggle simulation data are identified in the netlist. A ratio (KS) equal to a sum of all NT net weights divided by a sum of all NP populated net weights is generated. A sample energy (ES) is generated based on the associated toggle simulation data of and net weights for each of the NP populated nets. And a block power profile is modelled based on an estimated block energy (EN) equal to KS multiplied by ES.

Abstract: Techniques for detecting a data race condition between multiple execution engines of an integrated circuit device are provided. Computations and data movements involving execution engines of an integrated circuit may be described with a flow graph, where graph nodes represent computation or data movement operations and graph edges represent dependencies between the operations. When a graph has incorrect dependencies, data races may result. To detect data race conditions, compiler-generated vector clocks that track the relationships of operations performed by various execution engines may be used to determine concurrent operations between nodes of different execution engines, and memory access patterns for the operations may be compared to determine if the concurrent operations access the same memory address.

Abstract: An approach is provided for dynamic beacons address allocation. The approach involves reporting, by each child node of a beacon tree structure, to a parent node, a load collection packet including a load count of each child node. Each child node is either a leaf node or a parent node. The parent node is either a root node or a child node reporting to another node. The parent node is located on a shortest path from a leaf node to the root node. The load count is a total number of the other nodes reporting to the parent node plus one. The approach also involves receiving, by each child node from the parent node, an address distribution packet that includes a contiguous logical address range and a weighted distance to the root node (WDR). The WDR and/or the tree structure are provided as an input for a drone navigation task.

Abstract: A machine control device includes: a diagnostic test time calculation unit that calculates a scheduled execution time of a diagnostic test; a program execution time prediction unit that predicts a predicted ending time of a program before executing the program; a diagnostic test execution determination unit that determines whether to execute the diagnostic test at a predetermined time, by determining whether the predicted ending time of the program exceeds the scheduled execution time of the diagnostic test, and a diagnostic test execution unit that executes the diagnostic test, in which, in a case in which the predicted ending time of the program exceeds the scheduled execution time of the diagnostic test, the diagnostic test execution determination unit instructs the diagnostic test execution unit to execute the diagnostic test prior to the scheduled execution time of the diagnostic test before executing the program.

Abstract: Systems and methods for analyzing structured data are described. A device may receive a table of structured data and create a Raw Pair Distance (RPD) table. The device then selects a set of nodes from the elements in the RPD table and outputs a nodes table. The device may also output a node-node distance (NND) matrix using the RPD table and run an energy reduction algorithm on the NND matrix in order to create an NSPACE matrix including n-dimensional coordinates for each node. The device may display (e.g., via a 3D visualizer) a graphical representation of selected nodes and coordinated relationships between the selected nodes. The systems and methods may enable a user to quickly search and understand relationships within a large structured data set.

Abstract: A deterioration detecting system for semiconductor process kits has a Raman spectrometer, an optical detecting unit, a Raman spectra database unit, and a controlling-computing unit. The optical detecting unit and the controlling-computing unit are both coupled to the Raman spectrometer. The Raman spectrometer detects a semiconductor process kit under detection through the optical detecting unit to obtain a scatter light having an excited Raman spectrum signal. The Raman spectra database unit stores a plurality of Raman spectrum signals corresponding to multiple known use hours, multiple known materials, multiple known material compounds, or multiple known material deterioration state, of the semiconductor process kit under detection.

Abstract: The present disclosure provides a GPU-based third-order low-rank tensor completion method. Operation steps of the method includes: (1) transmitting, by a CPU, input data DATA1 to a GPU, and initializing the loop count t=1; (2) obtaining, by the GPU, a third-order tensor Yt of a current loop t based on the least squares method; (3) obtaining, by the GPU, a third-order tensor Xt of the current loop t based on the least squares method; (4) checking, by the CPU, whether an end condition is met; and if the end condition is met, turning to (5); otherwise, increasing the loop count t by 1 and turning to (2) to continue the loop; and (5) outputting, by the GPU, output data DATA2 to the CPU. In the present disclosure, in the third-order low-rank tensor completion, a computational task with high concurrent processes is accelerated by using the GPU to improve computational efficiency.

Abstract: Methods, systems and computer readable media are disclosed for providing a quantum cipher based on phase inversion, A shared key is established between a first party and a second party. A Hadamard transformation is applied to a message intended for a second party from the first party to produce an equal superposition state. A key phase inversion is applied to the output of the Hadamard transformation. A multiple phase inversion transformation is applied to the output of the key phase inversion to produce an encrypted quantum state with a uniform probability and relative phase distributions. The result is sent to the second party.

Abstract: Methods, systems, and computer-readable media for ingestion partition auto-scaling in a time-series database are disclosed. A first set of one or more hosts divides elements of time-series data into a plurality of partitions. A second set of one or more hosts stores the elements of time-series data from the plurality of partitions into one or more storage tiers of a time-series database. An analyzer receives first data indicative of the resource usage of the time-series data at the first set of one or more hosts. The analyzer receives second data indicative of the resource usage of the time-series data at the second set of one or more hosts. Based at least in part on analysis of the first data and the second data, the analyzer initiates a split of an individual one of the partitions into two or more partitions.

Abstract: An apparatus for learning a rank of an artificial neural network is configured to decompose a weight tensor into a first weight tensor and a second weight tensor. A set of rank selection parameters are applied to the first weight tensor and the second weight tensor to truncate the rank of the first weight tensor and the second weight tensor. The set of rank selection parameters are updated simultaneously with the weight tensors by averaging updates calculated for each rank selection parameter of the set of rank selection parameters.

Abstract: Technologies are provided for feature-based continuous integration. A feature manifest can be created that identifies versions of program/hardware definition assets (such as source code files and register-transfer-level (RTL) definition files) that are stored in separate source control repositories but are related to a particular application or hardware feature. The identified versions of the assets can be retrieved from the separate repositories and, optionally, built, deployed, and/or tested. For example, a hardware feature manifest can be defined that identifies a version of an RTL definition for a hardware component stored in a first repository and a version of a verification program stored in a second repository. The hardware feature manifest can be used to retrieve the identified RTL definition from the first repository and to deploy it. The identified version of the verification program can be retrieved from the second repository and used to test the deployed RTL definition.

Abstract: Command execution data is received. The command execution data comprises a block address corresponding to an functional component, a register identifier corresponding to a design for testability (DFT) register of the functional component, and command data. The command execution data is converted to a serial command. The serial command is committed to the DFT register of the functional component. A response to the serial command is received. The response is generated by the functional component based on the serial command. The response is converted to command response data and is provided to a testing sub-system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.