Abstract: A fault rules engine generates a plurality of fault rules files. Each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design, and each fault rules file of the plurality of fault rules files can include data quantifying a nominal delay for a given two-cycle test pattern of a set of two-cycle test patterns and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects for a given cell type in the IC design. An IC test engine generates cell-aware test patterns based on the plurality of fault rules files to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of the plurality of candidate defects characterized in the plurality of fault rules files.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: Capturing and processing a digital image of a pictorial (e.g., hand-drawn) representation of a schematic or block diagram as a digital image to aid in creation and maintenance of electrical designs is disclosed. Processing of the digital image includes processing to determine design parameters to create an informational format useful as input to other design software. Design parameters may include schematic layout and attributes such as maximum output voltage, minimum input voltage, ambient temperature, etc. The method and system also include storage of information accessible to refine designs and perform simulations of designs as part of an overall electrical design process. Associated devices and methods are disclosed as well.

Abstract: A logic simulation verification system designates a change timing designation unit configured to designate a reference signal and a change timing and calculate a first time for which there is a possibility that a first signal to be assigned to a variable described in a library, a circuit description, and a test bench is changed in accordance with the reference signal. The system calculates a second time for which there is a possibility that a second signal assigned a variable described in the library, the circuit description, and the test bench will be checked in accordance the reference signal and then determines whether different circuits for which first signals are the same have first times that match. The system also determines whether a first time and a second time match with each other when a first signal of one circuit and a second signal of another circuit are the same.

Abstract: The present disclosure provides a measurement method for a contact resistance of a transistor test device and a computer-readable medium. The measurement method includes: providing multiple transistor test devices, where the transistor test devices each include a source, a drain, an active layer, a gate located at the active layer, and wires connected to the source and the drain, widths of gates, channel region lengths of active layers, and quantities of connected wires of the transistor test devices are the same, and widths of the active layers of the transistor test devices are different; obtaining multiple total resistances of the transistor test devices by measuring the transistor test devices; and determining contact resistances of the transistor test devices based on the multiple total resistances and the widths of the active layers matching the total resistances.

Abstract: An example method includes controlling a switching order of a plurality of power switches. The power switches are coupled to a flying capacitor and include parasitic bipolar transistors susceptible to the voltage overstress in response to excess stray inductance of the flying capacitor. The method further includes, in response to the controlled switching order, converting an input voltage of a first voltage level to an output voltage of a second voltage level while mitigating the voltage overstress of the parasitic bipolar transistors of the plurality of power switches.

Abstract: A method for generating a program to run on multiple tiles. The method comprises: receiving an input graph comprising data nodes, compute vertices and edges; receiving an initial tile-mapping specifying which data nodes and vertices are allocated to which tile; and determining a subgraph of the input graph that meets one or more heuristic rules. The rules comprises: the subgraph comprises at least one data node, the subgraph spans no more than a threshold number of tiles in the initial tile-mapping, and the subgraph comprises at least a minimum number of edges outputting to one or more vertices on one or more other tiles. The method further comprises adapting the initial mapping to migrate the data nodes and any vertices of the determined subgraph to said one or more other tiles.

Abstract: A power profile for an electronics design is implemented by accessing a unit descriptive of an electronic design comprising a first intellectual property (IP) block expressed in a simulation language and comprising a netlist. A total number (NT) of net weights are identified in the netlist, wherein each respective net weight is proportional to an effective load capacitance of an associated net. A total number (NP) of populated nets having associated toggle simulation data are identified in the netlist. A ratio (KS) equal to a sum of all NT net weights divided by a sum of all NP populated net weights is generated. A sample energy (ES) is generated based on the associated toggle simulation data of and net weights for each of the NP populated nets. And a block power profile is modelled based on an estimated block energy (EN) equal to KS multiplied by ES.

Abstract: Techniques for detecting a data race condition between multiple execution engines of an integrated circuit device are provided. Computations and data movements involving execution engines of an integrated circuit may be described with a flow graph, where graph nodes represent computation or data movement operations and graph edges represent dependencies between the operations. When a graph has incorrect dependencies, data races may result. To detect data race conditions, compiler-generated vector clocks that track the relationships of operations performed by various execution engines may be used to determine concurrent operations between nodes of different execution engines, and memory access patterns for the operations may be compared to determine if the concurrent operations access the same memory address.

Abstract: An approach is provided for dynamic beacons address allocation. The approach involves reporting, by each child node of a beacon tree structure, to a parent node, a load collection packet including a load count of each child node. Each child node is either a leaf node or a parent node. The parent node is either a root node or a child node reporting to another node. The parent node is located on a shortest path from a leaf node to the root node. The load count is a total number of the other nodes reporting to the parent node plus one. The approach also involves receiving, by each child node from the parent node, an address distribution packet that includes a contiguous logical address range and a weighted distance to the root node (WDR). The WDR and/or the tree structure are provided as an input for a drone navigation task.

Abstract: A machine control device includes: a diagnostic test time calculation unit that calculates a scheduled execution time of a diagnostic test; a program execution time prediction unit that predicts a predicted ending time of a program before executing the program; a diagnostic test execution determination unit that determines whether to execute the diagnostic test at a predetermined time, by determining whether the predicted ending time of the program exceeds the scheduled execution time of the diagnostic test, and a diagnostic test execution unit that executes the diagnostic test, in which, in a case in which the predicted ending time of the program exceeds the scheduled execution time of the diagnostic test, the diagnostic test execution determination unit instructs the diagnostic test execution unit to execute the diagnostic test prior to the scheduled execution time of the diagnostic test before executing the program.

Abstract: Systems and methods for analyzing structured data are described. A device may receive a table of structured data and create a Raw Pair Distance (RPD) table. The device then selects a set of nodes from the elements in the RPD table and outputs a nodes table. The device may also output a node-node distance (NND) matrix using the RPD table and run an energy reduction algorithm on the NND matrix in order to create an NSPACE matrix including n-dimensional coordinates for each node. The device may display (e.g., via a 3D visualizer) a graphical representation of selected nodes and coordinated relationships between the selected nodes. The systems and methods may enable a user to quickly search and understand relationships within a large structured data set.

Abstract: The present disclosure provides a GPU-based third-order low-rank tensor completion method. Operation steps of the method includes: (1) transmitting, by a CPU, input data DATA1 to a GPU, and initializing the loop count t=1; (2) obtaining, by the GPU, a third-order tensor Yt of a current loop t based on the least squares method; (3) obtaining, by the GPU, a third-order tensor Xt of the current loop t based on the least squares method; (4) checking, by the CPU, whether an end condition is met; and if the end condition is met, turning to (5); otherwise, increasing the loop count t by 1 and turning to (2) to continue the loop; and (5) outputting, by the GPU, output data DATA2 to the CPU. In the present disclosure, in the third-order low-rank tensor completion, a computational task with high concurrent processes is accelerated by using the GPU to improve computational efficiency.

Abstract: A deterioration detecting system for semiconductor process kits has a Raman spectrometer, an optical detecting unit, a Raman spectra database unit, and a controlling-computing unit. The optical detecting unit and the controlling-computing unit are both coupled to the Raman spectrometer. The Raman spectrometer detects a semiconductor process kit under detection through the optical detecting unit to obtain a scatter light having an excited Raman spectrum signal. The Raman spectra database unit stores a plurality of Raman spectrum signals corresponding to multiple known use hours, multiple known materials, multiple known material compounds, or multiple known material deterioration state, of the semiconductor process kit under detection.

Abstract: Methods, systems and computer readable media are disclosed for providing a quantum cipher based on phase inversion, A shared key is established between a first party and a second party. A Hadamard transformation is applied to a message intended for a second party from the first party to produce an equal superposition state. A key phase inversion is applied to the output of the Hadamard transformation. A multiple phase inversion transformation is applied to the output of the key phase inversion to produce an encrypted quantum state with a uniform probability and relative phase distributions. The result is sent to the second party.

Abstract: Methods, systems, and computer-readable media for ingestion partition auto-scaling in a time-series database are disclosed. A first set of one or more hosts divides elements of time-series data into a plurality of partitions. A second set of one or more hosts stores the elements of time-series data from the plurality of partitions into one or more storage tiers of a time-series database. An analyzer receives first data indicative of the resource usage of the time-series data at the first set of one or more hosts. The analyzer receives second data indicative of the resource usage of the time-series data at the second set of one or more hosts. Based at least in part on analysis of the first data and the second data, the analyzer initiates a split of an individual one of the partitions into two or more partitions.

Abstract: An apparatus for learning a rank of an artificial neural network is configured to decompose a weight tensor into a first weight tensor and a second weight tensor. A set of rank selection parameters are applied to the first weight tensor and the second weight tensor to truncate the rank of the first weight tensor and the second weight tensor. The set of rank selection parameters are updated simultaneously with the weight tensors by averaging updates calculated for each rank selection parameter of the set of rank selection parameters.

Abstract: Technologies are provided for feature-based continuous integration. A feature manifest can be created that identifies versions of program/hardware definition assets (such as source code files and register-transfer-level (RTL) definition files) that are stored in separate source control repositories but are related to a particular application or hardware feature. The identified versions of the assets can be retrieved from the separate repositories and, optionally, built, deployed, and/or tested. For example, a hardware feature manifest can be defined that identifies a version of an RTL definition for a hardware component stored in a first repository and a version of a verification program stored in a second repository. The hardware feature manifest can be used to retrieve the identified RTL definition from the first repository and to deploy it. The identified version of the verification program can be retrieved from the second repository and used to test the deployed RTL definition.

Abstract: Command execution data is received. The command execution data comprises a block address corresponding to an functional component, a register identifier corresponding to a design for testability (DFT) register of the functional component, and command data. The command execution data is converted to a serial command. The serial command is committed to the DFT register of the functional component. A response to the serial command is received. The response is generated by the functional component based on the serial command. The response is converted to command response data and is provided to a testing sub-system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Abstract: Embodiments of the present disclosure relate to a transistor and methods for forming a transistor. A transistor includes a gate electrode structure disposed over a channel region, a source/drain extension region disposed adjacent to the channel region, and a source/drain region disposed on the source/drain extension region. The source/drain region includes antimony (Sb). The method of forming a transistor includes forming the source/drain extension region and forming the source/drain region on the source/drain extension region. The antimony helps prevent unwanted migration of dopants from the source/drain region to the source/drain extension region.

Abstract: A computer-implementable method, a computing system, and a non-transitory computer-readable medium for automating workflow for routing metal wiring structures on an integrated circuit. The method automates, monitors, and controls all tasks for an auto-routing workflow. The method retrieves the auto-routing rules definition from a centrally stored location for easy maintenance. The method allows entry of wiring auto-routing constraints. The method enables customization per the design application to control signal integrity affected by the intrinsic routing metallization parasitic. The virtual copy of the layout database allows the layout database preparation without modifying the actual project layout. The virtual copy is used as an input for the workflow system. The method keeps the project layout database up to date.

Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

Abstract: A method for measuring the intensity of a current, comprising the steps of obtaining a computation matrix M comprising a set of terms, proportional to a distance between a measuring point and a reference point, raised to a power higher than or equal to zero, forming a vector B including measurements of the value of the magnetic field in a direction at a measuring point, computing the components of a vector A, each component being a coefficient of a decomposition of the magnetic field into spatial harmonics proportional to the intensity of the current such that the matrix relation B=M×A is satisfied, and determining the intensity.

Abstract: A sample simulates a processing state of a semiconductor sample and is measured by a measurement device. The sample includes: a first surface formed at a first height when viewed from a sample surface; a second surface formed at a second height higher than the first height; and a plurality of inflow parts which allow a particle for performing processing on the first surface to flow between the first surface and the second surface. The processing by the particle flowing from the inflow parts is superimposed in at least a part of a region to be processed on the first surface, and the region where the processing is superimposed on the first surface is measured by the measurement device.

Abstract: Modeling a multi-component control or actuator system using a fault tree is provided, which solves the problem of ring closures included in a fault tree. To identify ring closures, failure propagation paths are back-traced and is checked if the respective failure propagation path forms a ring closure.

Abstract: Methods, systems, and apparatus for authenticating and authorizing users using quantum key distribution through segmented quantum computing environments. In one aspect, a method includes receiving a first and second plaintext data input from a first party and from a second party, respectively; applying a quantum computation translation operation to the first and second plaintext data inputs to generate a corresponding first sequence of quantum computations and a second sequence of quantum computations; implementing the first and second sequence of quantum computations in a first and second segmented quantum computing environment, respectively, to obtain a first and second sequence of measurement results; generating a first and second encryption key using the first and second sequence of measurement results, respectively, and an encrypted authorization token using the second encryption key; and sending the first encryption key to the first party, and the encrypted authorization token to the second party.

Abstract: An electronic device includes at least one processor, at least one memory storing a model based definition (MBD) representing a model of a part, and an artificial intelligence (AI) client service. The AI client service, in response to execution by the at least one processor, is configured to receive inspection data corresponding to a cut part being fabricated based on the model of the part, compare the received inspection data to the MBD to determine any deviations of the cut part from the MBD, determine whether the cut part is defective based on the comparison, and update a digital thread corresponding to the part when the cut part is determined to be defective.

Abstract: A semiconductor metrology system including a spectrum acquisition tool for collecting, using a first measurement protocol, baseline scatterometric spectra on first semiconductor wafer targets, and for various sources of spectral variability, variability sets of scatterometric spectra on second semiconductor wafer targets, the variability sets embodying the spectral variability, a reference metrology tool for collecting, using a second measurement protocol, parameter values of the first semiconductor wafer targets, and a training unit for training, using the collected spectra and values, a prediction model using machine learning and minimizing an associated loss function incorporating spectral variability terms, the prediction model for predicting values for production semiconductor wafer targets based on their spectra.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.

Abstract: In one embodiment, a protected system, includes a first apparatus disposed on a silicon chip, and to perform a functional process, a second apparatus disposed on the silicon chip, and to perform a protecting process having a verifiable test result, the first and the second apparatus having a physical layout which interleaves at least part of the first apparatus with at least part of the second apparatus so that an attack on the at least part of the first apparatus also attacks the at least part of the second apparatus, a primary controller to signal the second apparatus to perform the protecting process during a time period that the first apparatus is performing the functional process, and an attack handling controller to perform a protective action to protect the functional process responsively to the protecting process failing to verify the verifiable test result providing an indication that the attack is being performed.

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design. Embodiments may include receiving, using at least one processor, data corresponding to an electronic design schematic. Embodiments may further include analyzing the data to learn one or more device size parameters, a range of parameters, or a matching relationship of parameters based upon, at least in part, the electronic design schematic or the electronic design layout, wherein analyzing occurs without user action.

Abstract: An industrial integrated development environment (IDE) supports open or extensible application programming interfaces (APIs) that enable end users (e.g., plant asset owners, original equipment manufacturers (OEM), system integrators, etc.) to build upon the IDE's development platform to create custom views or to code custom functionality. This can include, for example, defining a control programming syntax supported by the industrial IDE, customizing a development environment view afforded by the IDE's interface, modifying or creating project editing functions, defining customized programming guardrails designed to guide compliance with in-house programming standards, or other such IDE customizations.

Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.

Abstract: Methods, systems, and computer-readable media for two-dimensional partition splitting in a time-series database are disclosed. Stream processor(s) write elements of time-series data to a first replica group of a first tile associated with a first set of spatial and temporal boundaries. A second replica group is initialized with the same boundaries. A control plane generates updated metadata for the first tile. The updated metadata indicates a modified first set of spatial and temporal boundaries for the first replica group associated with the first tile and a second set of spatial and temporal boundaries for the second replica group associated with a second tile. The modified first set represents a first portion of the first set, and the second set represents a second portion of the first set. The updated metadata is obtained by the stream processor(s) which write, to the second tile, time-series data within the second set of boundaries.

Abstract: Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Abstract: Circuits may be designed using computer aided design tools and may comprise a plurality of different possible variants of individual components. These multi-variant component circuits may be validated to identify potential problems by generating an aggregate parametric model for the multi-variant components and then using the aggregate parametric model in applying tests to different connection networks of the circuit definition.

Abstract: A method for receiving a circuit layout including modules in a hierarchical structure. The method includes selecting a module in the hierarchical structure, identifying multiple toggling netlists in the module during multiple clock cycles, grouping the toggling netlists into clusters based on a toggle weight factor, and finding an average toggle weight factor for each cluster. The method includes generating instrument logic to determine a power consumption of the circuit layout based on a number of toggling netlists in each cluster for each clock cycle, and on the average toggle weight factor for each cluster, merging, with a compiler tool, the instrument logic with the circuit layout into an executable file for an emulator tool. The method includes evaluating the power consumption of the circuit layout with the emulator tool; and modifying the circuit layout when the power consumption of the circuit layout exceeds a pre-selected threshold.

Abstract: Systems and methods for multi-patterning in layout design data. A method includes receiving a coloring rule by a computer system. The method includes applying the coloring rule to the layout design data to identify a unique uncolored geometric element corresponding to the rule, by the computer system. The method includes, when the applied rule did not identify the unique uncolored geometric element corresponding to the rule, repeat the receiving and applying processes with a different coloring rule. The method includes, when the applied rule did identify the unique uncolored geometric element corresponding to the rule, assigning a patterning color to the unique uncolored geometric element, by the computer system.

Abstract: Embodiments of the present invention provide a hierarchical, multi-layer Jacobi method for implementing a dense symmetric eigenvalue solver using multiple processors. Each layer of the hierarchical method is configured to process problems of different sizes, and the division between the layers is defined according to the configuration of the underlying computer system, such as memory capacity and processing power, as well as the communication overhead between device and host. In general, the higher-level Jacobi kernel methods call the lower level Jacobi kernel methods, and the results are passed up the hierarchy. This process is iteratively performed until a convergence condition is reached. Embodiments of the hierarchical Jacobi method disclosed herein offers controllability of Schur decomposition, robust tolerance for passing data throughout the hierarchy, and significant cost reduction on row update compared to existing methods.

Abstract: A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.

Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.

Abstract: A propulsion system including a casing surrounding a fan rotor assembly is provided. The casing includes an outer layer material defining a first coefficient of thermal expansion (CTE) and an inner layer material. The casing further includes a spring member disposed between the outer layer material and the inner layer material coupling the outer layer material and the inner layer material. The spring member is coupled to each of the outer layer material and the inner layer material within a flow passage defined between the outer layer material and the inner layer material. The spring member defines a second CTE greater than the first CTE.

Abstract: Systems and methods for analyzing a large number of textual passages are described. A computing device receives the textual passages as input and generates a Raw Pair Distance (RPD) table. The device then determines a Node table and an Node-Node Distance (NND) matrix from the RPD table. An energy reduction process is used to generate an NSPACE matrix from the NND matrix. Finally, a 3D visualizer displays aspects of the Nodes table and the NSPACE matrix to a user. The systems and methods may enable a user to quickly search and understand the text relationships within the large number of textual passages.

Abstract: A method for automated recertification of a safety critical system with at least one altered functionality is provided. The method includes providing a failure propagation model of the safety critical system. The method also includes updating the failure propagation model of the safety critical system according to the at least one altered functionality using inner port dependency traces between inports and outports of a failure propagation model element representing the at least one altered functionality. The method includes calculating top events of the updated failure propagation model, and comparing the calculated top events with predetermined system requirements to recertify the safety critical system.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.

Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ? ( F ˜ 1 , C ? 2 ? q ? E g ? N n ? e ? t ? ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant.

Abstract: A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.