Abstract: A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.

Abstract: Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are provided on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second radius R2 if the via is not connected to any trace on the corresponding intermediate layer. If a trace is connected to a dynamic via, the via radius changes from the second radius R2 to a first radius R1, where R1 is greater than R2.

Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Abstract: A method for connecting a programmable device (PD) and an electronic component (EC) based on a protocol, including: obtaining a signal group of the protocol having a group constraint, a first pin definition including an electrical constraint and a logical constraint, and a second pin definition; mapping the first pin definition to a first pin of the PD based on the electrical constraint, the logical constraint, and the group constraint; identifying a first pin of the EC to connect with the first pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and a connection preference; generating a first connection between the first pin of the EC and a second pin of the PD based on the electrical constraint, the logical constraint, the group constraint, and the connection preference; and storing the first connection in an edge list.

Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels.

Abstract: A method for reducing leakage current of a delay line on a static net is provided. The static net provides a signal communication path between a data output of a first flip-flop and a data input of a second flip-flop via the delay line. The delay line is designed using standard cells but the standard cells are selected based on leakage power consumption in order to reduce the leakage power consumption of the delay line.

Abstract: In designing a printed circuit board, first and second copies of views of first and second major surfaces of the board respectively, are created. The first and second copies are positioned to contact each other. First and second segments on a side of the printed circuit board and normal to a first element in the first copy and a second element in the second copy respectively are obtained. A third segment joining ends of the first and second segments is obtained, and a point dividing the third segment according to a ratio of a distance from the first element to the side and a distance from the second element to the side is calculated. Distances from the first element to the point and from the point to the second element are calculated, and a creepage distance, a sum of the two distances and a thickness of the board, is obtained.

Abstract: A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical information regarding the printed circuit boards, for each of the printed circuit boards; creating an automatic wiring processing process automatically according to a result of analyzing setting, wiring progress, and wiring situation at present regarding each of the printed circuit boards, after reading the printed circuit board information, stored in the storage unit at the storing, for each of the printed circuit boards; and executing the automatic wiring processing according to the automatic wiring processing process created at the creating, for each of the printed circuit boards.

Abstract: A test circuit can use a simple test pattern data without customization for each substrate and considerably reduce a test preparation process. A connection test circuit is generated by receiving the input of the data of the connection relation indicating the devices mutually line-connected among a plurality of devices, the number of connection lines corresponding to the respective connection relations, and the device outputting a test result, sequentially searching for a connection destination device from the output terminal of an output device, and embedding a test circuit module in a test route.

Abstract: Disclosed is a computer implemented method for determining a voltage reference error in a PCB design comprising receiving information about said PCB design, identifying a signal associated with said design, receiving one or more user defined voltage references for said signal, and comparing the user defined voltage reference to the voltages of the power planes adjacent to said signal.

Abstract: A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Abstract: A design method includes creating power supply planes in each layer of a circuit board, from CAD data of the circuit boards whereby the power supply planes form one power supply conductor interconnect and supply power or connect to ground, expanding the shape of the power supply planes by a predetermined width, creating power supply pairs which are formed by opposing portions wherein two power supply planes existing in different layers are separated by an insulator and correcting the parameter by use of the mesh area.

Abstract: The present invention relates to a method for finding design weakness and potential field failure of a PCB assembly which includes components, comprising the steps of: (a) creating a model of the PCB assembly by which natural frequencies and mode shapes of the PCB assembly can be determined; (b) performing a natural frequencies simulation for determining natural frequencies and mode shapes of the PCB assembly; and (c) analyzing said determined natural frequencies and mode shapes and identifying local dominant oscillations of components, components identified as having a local dominant oscillation in at least one of said determined mode shapes are identified as components having a relatively high potential of field failure.

Abstract: An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.

Abstract: An apparatus is provided that comprises a plurality of signaling planes providing signal pathways and at least one internal reference plane providing either a voltage or a ground connection. The at least one internal reference plane are provided between at least two of the signaling planes. The apparatus further comprises a signal blind/buried via coupling a signal pathway of a first one of the at least two signaling planes with a signal pathway of a second one of the at least two signaling planes. The blind/buried via runs through the at least one internal reference plane. The apparatus also comprises at least one first conductive feature in the first one of the at least two signaling planes. The at least one first conductive feature is in close proximity to the signal blind/buried via and increases the capacitive coupling of currents in the reference planes of the apparatus.

Abstract: A user may optimize a circuit design using a control presented within an Internet browser. The user can change the optimization value of the circuit that in turn places more or less emphasis on a parameter (e.g. foot print vs. efficiency). Once optimized for the values, the list of components matching the design as well as the optimization operating values are presented to the user.

Abstract: In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary scan and other forms of testing), custom driver/receiver circuitry, etc. The pad ring in the programmable logic device, on the other hand, may be predetermined as part of the production of the programmable logic device. The generation may include removing the pad logic and other pad-related circuitry from one or more design files that represent the integrated circuit, as well as mapping the input, output, and input/output signals of the integrated circuit to the available programmable logic device pads.

Abstract: In an embodiment, a method to automatically select groups of signals to be multiplexed on pins of a programmable logic device in a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The set of signals that may be candidates for multiplexing may be received (e.g., the set may be output by programmable logic device design tool). Clock domain tracing may be performed, and signals that have matching clock domains may be identified as candidates for multiplexing. Signals from matching clock domains may be grouped (up to a maximum number of signals that may be multiplexed on one pin) and assigned to pins of the programmable logic devices.

Abstract: In an embodiment, a method to automatically process modifications to a set of design files is contemplated. The design files describe at least a portion of an integrated circuit design, and may be coded in a hardware description language. The modifications may be made to prepare the design files for inclusion in a programmable logic device implementation of the integrated circuit (or portion thereof). Specifically, the modifications may be specified using a set of commands which may be assembled by a user.

Abstract: In an embodiment, a methodology for automating the generation of a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The methodology may operate on one or more hardware description language (HDL) files which describe the integrated circuit as an input. Additionally, one or more user-generated control files may be input to the methodology. The methodology may process the one or more HDL files, generating a bitstream to program one or more programmable logic devices to implement the described design. The methodology may include automated modification of the HDL files to prepare them for programmable logic device implementation, automated pad ring generation, automated pin multiplexing, daughter card definition, partitioning, etc.

Abstract: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.

Abstract: A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design.

Abstract: A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver.

Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

Abstract: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.

Abstract: A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data.

Abstract: A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.

Abstract: In designing a printed circuit board, first and second copies of views of first and second major surfaces of the board respectively, are created. The first and second copies are positioned to contact each other. First and second segments on a side of the printed circuit board and normal to a first element in the first copy and a second element in the second copy respectively are obtained. A third segment joining ends of the first and second segments is obtained, and a point dividing the third segment according to a ratio of a distance from the first element to the side and a distance from the second element to the side is calculated. Distances from the first element to the point and from the point to the second element are calculated, and a creepage distance, a sum of the two distances and a thickness of the board, is obtained.

Abstract: A system and method that can analyze a temperature rise of a printed circuit board (PCB). The system and method receives attribute parameters of the PCB from an input device, and generates a temperature rise formula according to the received attribute parameters. Additionally, the system and method calculates a temperature rise of a local area surrounding each component on the PCB according to the temperature rise formula.

Abstract: A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon.

Abstract: A method is disclosed for electronically processing constraints rules defined in a previously developed first PCB design having a first constraints output file, to facilitate the development of a second PCB design having a second constraints output file. The second design has substantially identical topology to the first design and the second constraints output file comprises constraints for signals with identical attributes. The method includes several steps. Firstly, the board file of the first design is compared with the net list file of the second design to identify respective differences between the designs. On the basis of the established differences, a file attributes change report is generated. At least some data from the file attributes change report is stored into an attributes change file.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining corresponding outlines of selected component and unselected components in response to a user selecting one component; obtaining the range value; generating a reference outline according to the obtained range value and outline of the selected component; performing an intersection operation according to the reference outline and outlines of the unselected components, and determining whether one component is associated within the reference outline; marking and displaying the outlines of the corresponding unselected components when the unselected components are associated within the reference outline.

Abstract: A high-level logic description is developed based on a non-primitive-based standard cell library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic cells to create a primitive constructed version of each referenced standard cell. The set of primitive logic cells is defined for integration within a base array. The primitive constructed version of each referenced standard cell is included within a primitive-based cell library. The primitive-based cell library is used to place and route the netlist for the logic design for integration within the base array. The logic design is then integrated within the base array.

Abstract: An automatic system for providing printed circuit board (PCB) layout of a PCB includes an input device, a data processing device, and a storage device. The data processing device includes an invoking module, a calculating module, and a determining module. The invoking module is to read a name and a thickness of each layer of the PCB from the storage device. The calculating module is to calculate an actual length of a via stub of each layer according to the name and thickness of each layer, and calculate an ideal length of the via stub of the PCB according to input information from the input device, and a preset formula. The determining module is to compare the ideal length and the actual length of the via stub of each layer to determine whether the layer can be used as a high-speed signal layout layer or not.

Abstract: An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file.

Abstract: A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from predetermined design options for custom circuit boards. The hardware description language (HDL) module generates HDL corresponding to the design specifications and outputs the HDL to a circuit board producer.

Abstract: According to one embodiment, a design support apparatus determines one of a first impedance between a power plane and a ground plane in the printed circuit board at an ON time of a high-side transistor in the switching power supply, a second impedance between the power plane and the ground plane at an ON time of a low-side transistor in the switching power supply, and a third impedance in an intermediate range between the first impedance and the second impedance to be an impedance between the power plane and the ground plane, based on ON-time information indicative of a ratio of an ON period of the high-side transistor to a switching cycle of the switching power supply in an operation period of the device. The apparatus evaluates capacitor information included in design information of the printed circuit by comparing the determined impedance and a target impedance.

Abstract: A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or more T-point elements in the PCB layout design, divides the obtained signal line into a plurality of lines according to the one or more T-point elements with unused stubs, and obtains properties of each of the plurality of lines. The system and method further deletes the original layout of the signal line and reconnects the plurality of lines according to the properties of each of the plurality of lines to generate a reconnected signal line, and outputs the reconnected signal line on a display device.

Abstract: This invention discloses a new structure, multiple-connected-microstrip-line, based on microstrip line and the design methods of using this new structure for various electromagnetic components, which transmit, feed-in/feed-out, store/release, and radiate/receive electromagnetic signals with improved characteristics, such as Quality factor, broadband impedance matching, interference immunity, and radiation patterns in the applications, such as transmission lines, impedance transformers, inductors, antennas etc. Comparing with traditional microstrip line, the additional topological parameters of multiple-connected microstrip line allow the designers to improve broadband characteristics without increasing the size of the electromagnetic components.

Abstract: Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit models for such single plane pairs based on multilayer finite difference approximation. Based on the methods, coupling between different layers through electrically large apertures can be modeled very accurately and efficiently.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: A wiring design assisting apparatus includes an input part that has attribute information of a wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics of a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, position information and size information of a pattern removed area, and the degradation degree information; and an extracting process part that extracts, for re-wiring, wiring patterns that have degradation degrees equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: A description is given of a method for the computer-aided construction of flexible printed circuit boards that are arranged in a housing (10) of a device. The method provides a 3D model for determining the fixed points (1 to 4) of the printed circuit board, such as fastening points and connecting points, and a 2D model based on a development of a skeleton model (20) of the printed circuit board, for creating a printed circuit board design (40) comprising a printed circuit board contour and a printed circuit board layout. The two development environments are uniquely assigned to one another.

Abstract: A wiring-model creating apparatus creates a three-dimensional model of a wiring pattern on a printed board based on printed-board information created by an electrical computer-aided design, as a wiring model for a mechanical computer-aided design. A three-dimensional-model creating unit creates the three-dimensional model including holes on the printed board in addition to the wiring pattern, based on the printed-board information.

Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

Abstract: The invention relates to a design method and tool for designing electronic circuits on a printed circuit board, wherein at least one self-contained, pre-composed domain is used, wherein the domain is a module chosen from a pre-composed architecture library, including self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture.