Abstract: A method and system for validating integrated circuit designs that are built with encrypted silicon IP blocks decrypts the encrypted silicon IP blocks in the integrated circuit designs with the keys from IP providers. After decryption, various validation checks on the integrated circuit designs are done, such as design rule check (DRC), layout versus schematic (LVS) check, parasitic resistor capacitor (RC) extraction, circuit simulation, signal electro migration (EM) and voltage drop check, signal integrity (SI) check and static timing check, etc. After validation, any confidential data from the checking results related to the encrypted silicon IP blocks are themselves encrypted to protect the proprietary silicon IP blocks. The method and system work with silicon IP encryption technology to establish a low cost silicon IP usage and verification platform, and to enable a more cost efficient silicon IP business model.

Abstract: Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

Abstract: The present disclosure relates to a computer-implemented method for synthesis of device I/O associated with a printed circuit board (PCB) design. The method may include generating a first programmable device model and a second device model. The method may further include determining one or more pin assignments associated with the first programmable device model and the second device model based upon, at least in part, one or more of a breakout pattern, a breakout location and a fanout location, the one or more pin assignments configured to minimize one or more crossovers.

Abstract: A circuit layout method for a printed circuit board (PCB) is provided. The method includes forming a pair of signal traces on the PCB, and disposing a ground trace between the pair of signal traces. The pair of signal traces and the ground trace are located at a same layer of the PCB, and the ground trace renders the pair of transmission traces to have predetermined impedance. An associated PCB is also provided. The PCB includes a circuit layer, and a ground layer for grounding. The circuit layer includes a pair of signal traces, and a ground grace disposed between the pair of signal traces. The circuit layer is different from the ground layer. Based on the circuit layout method and the associated PCB, an electronic apparatus not only complies with mobile high-definition link (MHL) requirements regarding impedance between signal traces but also offers reduced costs.

Abstract: A plurality of approaches for forming a semiconductor device using an adaptive patterning method is disclosed. Some approaches include placing a semiconductor die unit on a carrier element, calculating trace geometry for a second set of traces, constructing a prestratum comprising a first set of traces, and constructing the second set of traces according to the calculated trace geometry. Forming the semiconductor device may further include electrically connecting at least one of the first set of traces to at least one of the second set of traces, and electrically connecting at least one bond pad of the semiconductor die unit to a destination pad through the at least one of the first set of traces and the at least one of the second set of traces.

Abstract: It is possible to improve workability of a design work by handling electric information between one object and other objects associated with the object. A plurality of objects are inputted and electric information is inputted to the objects. Among the objects, mutually connected objects are virtually made into a single object. According to electric information in each of the objects, i.e., the virtually unified single object and the other objects excluding the virtually unified single object, objects having the common electric information are connected by straight lines. According to the straight lines, a figure connecting the objects is inputted. A condition for connecting the objects in the figure is inputted. According to the condition, circuit parts are built and signal information is set in a terminal of the circuit parts.

Abstract: The invention relates to a method for influencing the selection of a type and form of a circuit implementation in at least one layer in a given integration task for at least one integrated circuit in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. In one embodiment, a plurality of electric or electronic components are spatially arranged and to be electrically connected. Completed solutions x are stored in a database, and each of the completed solutions includes properties for the given integration task. The completed solutions define a destination space from which a solution is selectable by operating elements and determines a type and form of circuit implementation as a result of the given integration task, and aggregates the plurality of electric and electronic components in one of a plurality of integration technologies.

Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.

Abstract: Aspects of the present disclosure relate to determining a layout of a racetrack that forms part of an RF isolation structure of a packaged module and the resulting RF isolation structures. Locations of where the racetrack can be adjusted (for example, narrowed) and/or removed without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, a portion of the racetrack can be removed to create a break and/or a portion of the racetrack can be narrowed in a selected area.

Abstract: A test map classification method includes modifying test data by converting to a test map including a wafer identifier, a coordinate, and data on whether a predetermined failure item occurs; calculating similarities of wafer pairs in the test map; performing similarity filtering to reset all the similarities, except for at least one similarity, on the basis of a predetermined wafer; determining whether there are similar wafers by comparing the filtered similarities with a reference value; and classifying spatial patterns using a similar relationship between the wafer pairs when there are similar wafers.

Abstract: In a computing device, a computerized method and a non-transitory storage medium are applied in checking a stored wiring diagram for high-noise components in close proximity to signal lines. An electronic component is selected in a PCB wiring file. A checking range of the selected electronic component is determined for searching for one or more signal transmission lines which pass within the checking range in the PCB wiring file. Basic information of the one or more signal transmission lines is recorded into a result list which is displayed on a display unit of the computing device.

Abstract: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal.

Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.

Abstract: An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad.

Abstract: Various embodiments of methods and systems for heuristic determination and thermal analysis of component placement on a printed circuit board (“PCB”) for use in a portable computing device (“PCD”) are disclosed. It is an advantage of embodiments that thermal energy generating components, such as processors, may be heuristically selected and arranged on a selected PCB according to varying layouts and combinations and then evaluated for thermal dissipation efficiency under an assortment of use case scenarios. In this way, users of the system and method may quickly narrow down commercially feasible component layouts, identify the most efficient layouts and then heuristically modify the layouts to develop an optimal arrangement.

Abstract: A method includes identifying at a first instantiation of a device design and a second instantiation of the device design, determining a first value of an electrical performance characteristic of the first instantiation and a second value of the electrical performance characteristic of the second instantiation, determining that the first instantiation matches the second instantiation, wherein the determining is based on the first value, the second value, and a tolerance, and in response to determining that the first and second instantiations do not match, then identifying a first feature of the first instantiation and changing the first feature of the first instantiation.

Abstract: A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.

Abstract: Phase compensation in a differential pair of transmission lines, including: identifying, by a phase compensation module, a plurality of direction changes in the differential pair of transmission lines; determining, by the phase compensation module for each direction change in the differential pair of transmission lines, a direction change angle; and determining, by the phase compensation module for each direction change in the differential pair of transmission lines, the geometry of one or more phase correction humps to include in one transmission line of the differential pair of transmission lines in dependence upon the direction change angle.

Abstract: Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on the voltage drop calculations and the voltage and current requirement of the various system components, the layout tool may determine if a given system component will remain within its required operating range. The layout tool may additionally be operable to verify proper spacing between traces that make up a differential signal and to verify that certain pins of integrated circuit are properly connected.

Abstract: A printed circuit board design assisting device includes a frame ground extraction section that extracts a ground pattern that is provided in a surface layer of a printed circuit board and that is to be connected to a metal component from design data on the printed circuit board stored in a design data storage section to store information for specifying the ground pattern in a data storage section, an electrostatic discharge determination section that performs a determination as to electrostatic discharge for the ground pattern specified from the information stored in the data storage section to store a determination result in a determination result storage section, and an output section that outputs the determination result stored in the determination result storage section.

Abstract: An approach is provided in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and identifies one or more electrical properties corresponding to a component assigned to the selected power plane thru pin location. As such, the dynamic thermal relief generator computes a conductive material exclusion amount based upon the identified electrical properties, which indicates an amount of area to exclude conductive material on the selected power plane layer. In turn, the dynamic thermal relief generator creates a thermal relief pattern based upon the computed conductive material exclusion amount that identifies conductive material voids on the selected power plane layer to exclude the substantially conductive material.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Abstract: According to an embodiment an improved Application Specific Integrated Circuit (ASIC) isolation method and system for assigning signal pins in an ASIC package having a plurality of signal pins is disclosed. The method and system comprise identifying an isolation requirement of the ASIC and determining an optimized pattern for substantially diagonal pairing of signal pins in relation to the isolation requirement. The method includes pairing signal pairs substantially diagonally in accordance with the pattern.

Abstract: An approach is described for managing item access in a collaborative workspace. A user interacts with the collaborative workspace through a workspace user interface presentation. The approach entails presenting an item user interface presentation to the user without losing a context associated with the workspace user interface presentation. The user can enter searching and filtering selections into the item user interface presentation to narrow an initial set of items provided by that presentation. Upon locating a desired item, the user can add it to the collaborative workspace using a drag-and-drop operation or other technique.

Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure.

Abstract: The invention relates to a design method and tool for designing electronic circuits on a printed circuit board, wherein at least one self-contained, pre-composed domain is used, wherein the domain is a module chosen from a pre-composed architecture library, including self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture.

Abstract: A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.

Abstract: In a method for detecting equivalent series inductances (ESL) of an electrical component of a printed circuit board (PCB), the electrical component and one or more signal lines connected with the electrical component are selected from a layout diagram of the PCB. The method selects a standard range of the ESL of the selected electrical component, calculates an ESL between each of the signal lines and a via hole corresponding to the signal line, and determines signal lines having ESL value that are not within the standard range. The method locates attribute data of the determined signal lines and the selected electrical component in the layout diagram of the PCB, and displays the attribute data of the determined signal lines and the selected electrical component on a display device.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.

Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.

Abstract: The design aiding device includes a processor that creates assembled model data, representing an assembled model that assumes arrangement of the part on the board, on the basis of the board data and the part data stored in the first storing section and the second storing section, respectively. The processor includes a recognizing section that recognizes a mounting face of a part model defined by the part data, the mounting face being mounted on a board model defined by the board data; and an arrangement processing section that creates the assembled model data by arranging the part model on the board model on the basis of the mounting face recognized by the recognizing section.

Abstract: A collaborative environment for performing physical verification processes on integrated circuit designs. Multiple physical verification results may be stored in a “unified” results database/directory (e.g., unified at least from a user's perspective), where results from various verification processes, such as Design-Rule-Check (DRC) processes, Layout-Versus-Schematic comparison (LVS) processes, Design-For-Manufacturing (DFM) processes Optical Proximity Correction (OPC) processes, and Optical Rule Check (ORC) processes are accessible from the same style of user interface, which may be a graphical user interface. The basic abilities for design team-based interactions can be equally available to each process involved in the physical verification of an integrated circuit design.

Abstract: A method of generating electrical rule file for circuit board by using an electronic device. The electronic device acquires a component file, a wiring file, a wiring group file, a first electrical rule file, and a second electrical rule file from a storage device. The electronic device integrates the component file and the wiring file to be an integrated file according to wire names, acquires group names and inserts the group names into the integrated file according to the wire names, acquires first electrical rules and inserts the first electrical rules into the integrated file according to the group names, acquires second electrical rules and inserts the second electrical rules into the integrated file according to the group names, to complete the integrated file, and saves the completed file to the storage device.

Abstract: The present invention aims to improve accuracy of a planar manufacturing drawing used to instruct manufacture of a three-dimensional structure in a planar form. According to path plan information is acquired by a path plan information acquisition unit 11a and manufacturing requirement information is acquired by a manufacturing requirement information acquisition unit, a layout configuration production unit 11c produces a layout configuration model in which the three-dimensional structure is laid out in a planar manner based on a manufacture layout and distortion of the wire harness. Then, a simulation unit 11d simulates a transformation from the layout configuration model to the mounting configuration model with which the three-dimensional structure is mounted to a mount object. Then, an evaluation item evaluating unit 11e evaluates a predetermined evaluation item by comparing the simulation result and the three-dimensional structure indicated by the path plan information.

Abstract: A computer aided design system comprises an interface creating module, a first calculating module, a dividing module and a second calculating module. The interface module creates a parameter setting interface to display the proposed design on the screen of the device formed with nets and cline segments and select at least one net in response to the user's operation. The first calculating module calculates the length of the cline segments of the potential net in order based on the coordinates of the cline segments and generates a dividing signal. The dividing module divides the cline segments into a first team and a second team based on the compared result with a predetermined width according to the dividing signal. The second calculating module adds the calculated cline segments length in the first team and in the second team to obtain a first length and a second length.

Abstract: The invention discloses a printed circuit board compensation processing method for fabricating a BGA despite a small distance between a line and a pad of the BGA. The method includes compensating a pad and/or a line under a predetermined condition, and removing a portion of the pad facing the line by a second predetermined width when the shortest distance between the compensated line and pad is smaller than a first predetermined distance. The invention further discloses a device for performing the method and a PCB fabricated using the method.

Abstract: A method for removing the effects of metallic objects in an inductively coupled power transfer system by providing a metallic casing around transmitting and/or receiving coils and compensating for their effect in the design of transmitting and/or receiving circuits. Whilst incurring some loss in performance this design reduces variability due to different metallic influences in an operating environment. Power transmitters and receivers and a system including the power transmitter and the power receiver are also disclosed.

Abstract: When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.

Abstract: A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.

Abstract: Creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact in a system. Values are stored by a system simulator corresponding to a galvanic potential or same “net”. According to a set of rule based instructions vias are automatically displayed, correct-by-construction, and via connections between the traces, or the trace and device contact, to short circuit the paths. The via structure will not be created if it will short-circuit a conducting trace not associated with the net in question. By connecting traces on different layers using automatically created via structures so as not to short circuit other net traces, errors are eliminated and design cycles reduced when compared to a manual design scheme of inserting via connections. There is an interactive mode which allows the via to be easily resized by the use of familiar control handles.

Abstract: A computer aided design system comprises a storage module, an interface creating module, and a calculating module. The storage module stores a contact list, one or more programs, and coordinates of each net which is being composed of a plurality of cline segments. The interface module creates a parameter setting interface on the screen of the device to display a design with a plurality of to-be-calculated nets and select at least one net in response to the user's operation. The calculating module calculates the length of each branch of the selected nets.

Abstract: Phase compensation in a differential pair of transmission lines, including: identifying, by a phase compensation module, a plurality of direction changes in the differential pair of transmission lines; determining, by the phase compensation module for each direction change in the differential pair of transmission lines, a direction change angle; and determining, by the phase compensation module for each direction change in the differential pair of transmission lines, the geometry of one or more phase correction humps to include in one transmission line of the differential pair of transmission lines in dependence upon the direction change angle.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting.

Abstract: A computer aided design system comprises a dividing module, a storage, an interface creating module, a selecting module, and a display module. The dividing module divides the names into groups according to a predetermined rule. The group comprises a plurality of the targets set on the different layers. The storage records the relationship between the groups and the targets. The interface creating module creates a user interface base on the groups and selects at least one group in the same user interface from the operation of the user. The selecting module selects targets according to the selected groups. The display module displays the selected targets.

Abstract: A computer aided design system comprises an interface creating module, a reference layer setting module, a detecting module and a signing module. The interface module creates a parameter setting interface to select at least one net being composed of a plurality of cline segments, and set a stack distance. The reference layer setting module sets a reference layer for the layer contained the selected net based on the stack distance. The detecting module obtains a projection of the cline segment of the selected net on the reference layer, sets a region corresponding to the cline segment on the reference layer, detects whether the projection extends out of the set region, and generates a signing signal to sign the cline segment when the projection does extend out of the set region. The signing module signs the cline segment according to the sign signal.

Abstract: An approach for managing permissions in a collaborative workspace involves providing a permissions user interface presentation without loosing a context associated with a collaborative workspace user interface presentation. The permissions user interface presentation visually organizes a set of workspace members into two or more permission level categories. The permissions user interface presentation also allows a user to efficiently add new workspace members from a local system or an alternative system.

Abstract: An approach is in which a dynamic thermal relief generator retrieves a circuit board file that identifies power plane thru pin locations and a power plane layer. The dynamic thermal relief generator selects one of the power plane thru pin locations and creates a thermal relief pattern that includes thermal relief shapes that identify conductive material voids on a power plane layer to exclude substantially conductive material. The dynamic thermal relief generator determines that one of the conductive material voids affects one or more proximate signal tracks and, in turn, automatically adjusts the thermal relief pattern accordingly.

Abstract: An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned.

Abstract: In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.