Abstract: An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes. The reference mesh plane includes spaced mesh lines that are separated by spaces that alternate in a narrow-wide or wide-narrow pattern. A multi-layered ceramic package using the mesh plane with alternating spaces generates significantly lower far-end (FE) noise in the ceramic package than a conventional mesh plane with constant spaces. The noise is further reduced by placing shield lines on opposite sides of signal lines in the signal plane.

Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

Abstract: A method of determining a reinforcement position of a circuit board includes: setting a numerical model of a circuit board in which an electronic component is mounted in a front surface by bumps, and a reinforcing member is attached to a position corresponding to a bump located in a corner part of the electrical component in a back surface; incorporating information about a stud that is located in a periphery of the electronic component and fixes the circuit board to a chassis of the electronic device; performing a simulation for obtaining values of stresses generated in bumps of corner parts when a force is applied to the electronic component from a back side of the circuit board; and determining an arrangement of the reinforcing member in accordance with a position of the stud based on the values of stresses obtained by the simulation.

Abstract: A computer aided design system comprises an interface creating module, a first calculating module, a dividing module and a second calculating module. The interface module creates a parameter setting interface to display the proposed design on the screen of the device formed with nets and cline segments and select at least one net in response to the user's operation. The first calculating module calculates the length of the cline segments of the potential net in order based on the coordinates of the cline segments and generates a dividing signal. The dividing module divides the cline segments into a first team and a second team based on the compared result with a predetermined width according to the dividing signal. The second calculating module adds the calculated cline segments length in the first team and in the second team to obtain a first length and a second length.

Abstract: A wiring-design support device supports wiring design of a printed circuit board. The processor executes a process that includes holding, in the memory, wiring information including information relating to a plurality of signal wires to be wired in parallel between two components on the printed circuit board, generating a wiring route illustrating a wiring area where the plurality of signal wires are wired between the two components and displaying the wiring route on a display unit based on the wiring information held in the holding. And the processor generates, upon or after the wiring route generated, a detailed wiring where each of the plurality of signal wires is wired along the wiring route based on the wiring route and a wiring rule included in the wiring information, and displaying the detailed wiring on the display unit along with the wiring route.

Abstract: A word processing or spreadsheet application is augmented by a plug-in and templates for computer aided design of electronic hardware entities. The plug-in utilizes the application programming interface to provide a menu system and executable code which inserts templates, reads and validates data entered into the template, computes addresses, annotates addresses and error messages back to a word processing document for display in the editor of the word processing document, and upon selection and request, generates output files for target simulators or synthesis tools.

Abstract: A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.

Abstract: A computing system includes a drawing unit and a layout unit. The computing system sets components parameters to components of a circuit diagram of a printed circuit board (PCB). The drawing unit draws the circuit diagram by using the components with the components parameters. If the drawing unit wants to use a component more than once, the computing system copies the component and the corresponding components parameters. The drawing unit uses the copied components and the corresponding parameters. If the circuit diagram has been drawn, the layout unit loads the circuit diagram and wires the PCB according to the components and the components parameters in the circuit diagram.

Abstract: A via design apparatus includes a determination section that determines a value of a shape parameter indicating a shape of a via in a multilayer board. The via has a hole passing through the plurality of layers and a conductive section on a side wall of the hole. The apparatus also includes a calculation section that calculates a value of impedance of the via according to the value of the shape parameter.

Abstract: Methods, apparatus, and products for impedance compensation for a differential pair of conductive paths, including: determining the differential impedance and conductor geometry for the differential pair of conductive paths; determining the path length differential between the conductive paths in the differential pair of conductive paths; determining a centerline path to follow for a shorter conductive path in the differential pair of conductive paths, wherein the centerline path lengths the shorter conductive path such that the length of each conductive path in the differential pair of conductive paths is identical within a predetermined threshold; determining a number of subdivisions of one or more serpentine segments on one of the conductive paths in the differential pair; and determining, in dependence upon the differential impedance at each of the subdivisions of the one or more serpentine segments, a serpentine segment path width for the serpentine segment.

Abstract: A device includes a definition unit which defines a directional graph having a grid point as a node and a line connecting adjacent grid points as a branch, a generation unit which sets a branch connecting a grid pointing a wiring prohibited area in the branches of the directional graph to the capacity of “0”, and which sets another branch to the capacity of “1”, and which connects the starting point or the end point to each grid point of the wiring terminal indicated by wiring information, thereby generating a flow network, a search unit which searches the flow network for a path of a flow having the maximum amount of flow from the starting point to the end point, and a determination unit which determines a wiring path connecting the grid point indicated by the wiring information according to the search result of the path.

Abstract: A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance.

Abstract: In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

Abstract: Methods, systems, and computer program products for using direct memory access (DMA) to initialize a programmable logic device (PLD) are provided. A method includes manipulating a control line of the PLD to configure the PLD in a programming mode, receiving PLD programming data from a DMA control at a DMA speed, and writing the PLD programming data to a data buffer. The method also includes reading the PLD programming data from the data buffer, and transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

Abstract: A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.

Abstract: Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking.

Abstract: In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

Abstract: A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.

Abstract: The present invention aims to improve accuracy of a planar manufacturing drawing used to instruct manufacture of a three-dimensional structure in a planar form. According to path plan information is acquired by a path plan information acquisition unit 11a and manufacturing requirement information is acquired by a manufacturing requirement information acquisition unit, a layout configuration production unit 11c produces a layout configuration model in which the three-dimensional structure is laid out in a planar manner based on a manufacture layout and distortion of the wire harness. Then, a simulation unit 11d simulates a transformation from the layout configuration model to the mounting configuration model with which the three-dimensional structure is mounted to a mount object. Then, an evaluation item evaluating unit 11e evaluates a predetermined evaluation item by comparing the simulation result and the three-dimensional structure indicated by the path plan information.

Abstract: A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations.

Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.

Abstract: The present disclosure relates to a computer-implemented method for assigning pins in an electronic design. The method may include generating a pin list associated with the electronic design, the pin list having a one or more pins that are directly and indirectly connected with at least one of a master partition and a clone partition. The method may further include sorting one or more pins within the pin list based upon, at least in part, a number of local connections to generate a sorted pin list and selecting a first pin having a highest number of local connections of the sorted pin list as a reference pin. The method may also include selecting a partition of the reference pin, as a reference partition and identifying one or more alignment zones for every connected pair of pins in the sorted pin list. The method may further include transforming all alignment zones to the reference partition using a depth-first-search.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: Consistent with an example embodiment, there is an apparatus comprising a circuit (500) board. The circuit board includes a first surface (501a) and a second surface (501b). The first and second surfaces each have at least a component populated thereon; the circuit board has a first surface thereof populated before a second surface thereof and is overmolded. The circuit board has conductive material disposed over areas of the second surface defining at least a feature (504) on the second surface. The at least a feature is defined by the conductive material and other than defined by solder resist (508) disposed on the second surface overlapping the conductive material, wherein the at least a feature is a feature for remaining exposed during a process of populating the first surface other than a fiducial.

Abstract: A computer aided design system comprises an interface creating module, a selecting module, a filling module and a measuring module. The interface module creates a user interface to display the design on the screen of the device with a plurality of to-be-checked patterns. The selecting module selects a pattern. The interface module further creates a parameter setting interface. The parameters comprises a predetermined width, the space value between the adjacent parallel filled lines and the rotation degree of the selected pattern. The filling module draws filled lines in the selected pattern according to the parameters. The measuring module detects whether the length of each filled line is at least the predetermined width value, if the length of the filled line is less than the predetermined width value, the dimension of the selected pattern is unqualified and the measuring module highlights the filled lines.

Abstract: A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Abstract: A method for providing an alternative power source for a graphics card are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of laying a set of gold fingers on a printed circuit board according to an industrial standard bus interface, positioning a wire in a middle layer of the printed circuit board, attaching a first end of the wire to a specific gold finger, and attaching the alternative power source to a second end of the wire, wherein the second end of the wire is an electroplated contact protruded external to the printed circuit board.

Abstract: The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters.

Abstract: First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.

Abstract: In an embodiment, a method to automatically generate a pad ring for a programmable logic device implementation of an integrated circuit is contemplated. The pad ring that will be used in the integrated circuit itself may include pad logic (e.g. to support boundary scan and other forms of testing), custom driver/receiver circuitry, etc. The pad ring in the programmable logic device, on the other hand, may be predetermined as part of the production of the programmable logic device. The generation may include removing the pad logic and other pad-related circuitry from one or more design files that represent the integrated circuit, as well as mapping the input, output, and input/output signals of the integrated circuit to the available programmable logic device pads.

Abstract: A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.

Abstract: The invention concerns a method and devices for analyzing the feasibility of a computer system composed of subsystems, each having functions. After having determined the functional architecture of the computer system comprising at least one subsystem and at least one function, the characteristics of the functions implemented are imported from a database. The user determines the number of subsystems and the number of connectors per subsystem. He then distributes the functions to the subsystems and enters the characteristics of the connectors and the characteristics of the subsystems. The computer system is analyzed in light of the information provided by the user and the characteristics of the functions implemented in order to determine the feasibility of the computer system.

Abstract: In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied.

Abstract: A packaging design aiding device, including a storage unit to store component information that specifies another electronic component to be connected with an electronic component and a constraint that specifies a range of a wiring distance, a wiring determination unit to specify the electronic component and the another electronic component to be connected based on the component information and to determine a wiring there between, a wiring distance calculation unit to calculate the wiring distance between the electronic component, a display form determination unit to determine a display form based on the calculated wiring distance and the constraint, and a display control unit to display the wiring that connects the electronic component and the another electronic component in the determined display form.

Abstract: In a method of managing process factors that influence electrical properties of printed circuit boards (PCBs), n process factors are arranged in an order according to different influence to one kind of electrical property of the PCBs. The different influence is determined by first experiments designed using the Taguchi method. M process factors that have important influence to the electrical property are obtained from the n process factors according to the order to design second experiments. A computing formula for the electrical property is fitted using the m process factors according to simulated results of the second experiments, and a variation range of each of the m process factors is computed according to the computing formula.

Abstract: Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers.

Abstract: An operation analyzing apparatus (100) for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (140), and the simulation analyzing unit (140) includes: a semiconductor characteristics extracting unit (110) that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit (111) that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit (112) that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit (113) that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern

Abstract: In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.

Abstract: An enhanced mechanism for via stub elimination in printed wiring boards (PWBs) and other substrates employs laser resin activation to provide selective via plating. In one embodiment, the resin used in insulator layers of the PWB contains spinel-based non-conductive metal oxide. Preferably, only insulator layers through which vias will pass contain the metal oxide. Those layers are registered and laser irradiated at via formation locations to break down the metal oxide and release metal nuclei. Once these layers are irradiated, all layers of the PWB or subcomposite are laid up and laminated. The resulting composite or subcomposite is subsequently drilled through and subjected to conventional PWB fabrication processes prior to electroless copper plating and subsequent copper electroplating. Because metal nuclei were released only in the via formation locations of the appropriate layers, plating occurs in the via barrels only along those layers and partially plated vias are created without stubs.

Abstract: The invention discloses a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances are compared to the second set of impedances, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described.

Abstract: A method for setting a test point is applied to dispose at least one test point on a circuit board in a trace file, which includes steps of reading the trace file, in which the trace file includes at least one trace; determining whether the trace has an initial test point; and setting a test point on the trace that does not have the initial test point. According to the method for setting a test point, cost and time for manually disposing the test point are saved, and an error rate when the test point is arranged is further reduced, thereby effectively improving production efficiency of the circuit board.

Abstract: A high-frequency device having high-frequency-signal-treating circuits in and on a laminate substrate comprising pluralities of dielectric layers having conductor patterns, the high-frequency-signal-treating circuits having amplifier circuits and switch circuits; terminals including input and output terminals of high-frequency signals, the power supply terminals of the amplifier circuits and the power supply terminals of the switch circuits being formed on one main surface of the laminate substrate; power supply lines each having one end connected to each of the power supply terminals of the amplifier circuits and power supply lines each having one end connected to each of the power supply terminals of the switch circuits being formed on one dielectric layer to constitute a power supply line layer; a first ground electrode being arranged on the side of the main surface with respect to the power supply line layer, the first ground electrode overlapping at least part of the power supply lines in a lamination di

Abstract: A re-routing method for a circuit diagram includes the following steps. At least one pair of the signal lines is obtained from a routed circuit diagram. The routed circuit diagram is adapted to be laid out on a substrate of a Printed Circuit Board (PCB). The substrate includes warp wires and weft wires. At least one pair of the signal lines includes two signal lines in parallel. The pair of signal lines includes several pairs of line segments. It is determined whether at least one pair of parallel line segments exists in the pairs of line segments parallel to the warp or weft wires. If at least one pair of parallel line segments exists, at least one pair of parallel line segments on the routed circuit diagram is replaced with several pairs of 10-degree lines. Respective angle between the 10-degree lines and the warp or weft wires are 10 degrees.

Abstract: A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.

Abstract: An electronic device includes a wiring unit. The wiring unit creates one or more circuit diagrams for a design of a first circuit board, and setting electrical rules for components of the first circuit board in each of the one or more diagrams. Based on the one or more diagrams having the electrical rules, the wiring unit generates a wiring diagram for the design of the first circuit board by executing a wiring application. If a second circuit board desires to use a circuit diagram of the first circuit board, the wiring unit copies the circuit diagram having the electrical rules into the wiring application. Then, based on the copied circuit diagram having the electrical rules and particular circuit diagrams of the second circuit board, and the wiring unit creates a wiring diagram for the design of the second circuit board by executing the wiring application.

Abstract: A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from predetermined design options for custom circuit boards. The hardware description language (HDL) module generates HDL corresponding to the design specifications and outputs the HDL to a circuit board producer.

Abstract: A wiring verification system is provided which is capable of simultaneously solving problems of wiring constraints on each board and of total skew in a wire passing through a plurality of boards. Board data, external connection board data, inter-board connection information, and wiring constraints are inputted in advance. When a system netlist creating unit (including a software means) creates a system netlist showing a theoretical connection relation of each board, an external connection tracing unit (including a software means) extracts external connection information based on the system netlist. An external load producing unit (including a software means) produces an external dummy load converted to a wire length or wire delay of the outside based on extracted external connection information. A wiring verification unit (including a software means) performs verification of a wiring state of an entire board by using the produced external dummy load.

Abstract: According to one embodiment, a design support method includes generating first layout data when first electronic components and first positions of the first electronic components on a printed circuit board are specified, computing temperature distribution data showing a temperature distribution on a surface of the board, acquiring a maximum thermal resistance temperature of the second electronic component when the second electronic component is specified, calculating a first temperature on the surface at a second position based on the temperature distribution data when the second position is specified, determining whether the second electronic component can be arranged at the second position based on the first temperature and the maximum thermal resistance temperature, and prohibiting generation of a second layout data when it is determined that the second electronic component can be arranged at the second position, the second layout data showing the first positions and the second position.

Abstract: Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.