Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: A system includes a computer readable storage medium and a processor. The computer readable storage includes data representing an input/output (“I/O”) cell of a first type for modeling and/or fabricating a semiconductor device. The I/O cell of the first type includes circuitry for providing a first plurality of functions. The processor is in communication with the computer readable storage medium and is configured to select the I/O cell of the first type, arrange a plurality of the I/O cells of the first type on a model of an semiconductor device, and store the model of the semiconductor device including the plurality of the I/O cells of the first type in the computer readable storage medium.

Abstract: In an embodiment, a method to automatically process modifications to a set of design files is contemplated. The design files describe at least a portion of an integrated circuit design, and may be coded in a hardware description language. The modifications may be made to prepare the design files for inclusion in a programmable logic device implementation of the integrated circuit (or portion thereof). Specifically, the modifications may be specified using a set of commands which may be assembled by a user.

Abstract: A pin out designation method for package board codesign has steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns and may use the pin patterns to construct multiple pin blocks, to group the pin blocks around four sides of a chip and to adjust the pin blocks into a minimized package size of the chip.

Abstract: A wiring design assisting apparatus includes an input part that has attribute information of a wiring pattern input thereto; a degradation degree process part that obtains a degradation degree in signal characteristics of a wiring pattern corresponding to attribute information that is input to the input part, based on position information of the wiring pattern corresponding to the attribute information input to the input part, position information and size information of a pattern removed area, and the degradation degree information; and an extracting process part that extracts, for re-wiring, wiring patterns that have degradation degrees equal to or more than a predetermined degree, from wiring patterns for which degradation degrees have been obtained by the degradation degree process part.

Abstract: A method implemented by a computer layout software for setting the width of the printed circuit board trace is disclosed. The method selects one from several traces set on the printed circuit board traces, obtains the corresponding trace name of the selected trace, obtains the device pin connected to the selected trace, acquires the pad corresponding to the device pin, reads the width of the pad, and adjusts the width of the pad.

Abstract: The invention relates to a design method and tool for designing electronic circuits on a printed circuit board, wherein at least one self-contained, pre-composed domain is used, wherein the domain is a module chosen from a pre-composed architecture library, including self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture.

Abstract: A pad layout method for surface mount circuit board and a surface mount circuit board are described. The layout method includes the following steps. Firstly, coefficients of thermal expansion of a circuit board and a surface mounted component are obtained, and the circuit board is supplied with a plurality of predetermined layout positions in advance. Then, an operating temperature for combining the surface mounted component with the circuit board is determined, and a room temperature is measured. A plurality of actual layout positions on the circuit board is determined according to d=(CTEa?CTEb)×(Ts?Tr), where d is an offset distance between the actual layout position and the predetermined layout position. Finally, a plurality of pads is laid out on the actual layout positions, such that the pads are formed on the circuit board.

Abstract: A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.

Abstract: A method, system, and computer program product for exploring and optimizing an electrical design space. A computer receiving a design space assigns a plurality of initial values (random or predetermined) for optimizing the design space. A particle swarm containing a plurality of particles is created and an optimization of the design space is then performed using the assigned initial values. Following completion of optimization, the global best and personal best for each particle are updated. Velocity vectors and position vectors of the design space are then updated before the computer performs the optimization process again. The process loops, continually updating global and personal bests and velocity and position vectors until a termination criteria is reached. Upon reaching the termination criteria, the best fitness of each particle of the swarm is assigned as an optimized design space. In an alternate embodiment, the particle with the worst target fitness may be assigned.

Abstract: It is possible to improve workability of a design work by handling electric information between one object and other objects associated with the object. A plurality of objects are inputted and electric information is inputted to the objects. Among the objects, mutually connected objects are virtually made into a single object. According to electric information in each of the objects, i.e., the virtually unified single object and the other objects excluding the virtually unified single object, objects having the common electric information are connected by straight lines. According to the straight lines, a figure connecting the objects is inputted. A condition for connecting the objects in the figure is inputted. According to the condition, circuit parts are built and signal information is set in a terminal of the circuit parts.

Abstract: A method for designing a coil pattern, whereby the production of an error magnetic field and further an eddy current can be suppressed to improve the quality of a cross-sectional image irrespective of cylindrical cross-sectional shape of the main coil and the shield coil. The difference between the initial values of the target magnetic field and the magnetic field vector is set as a difference target magnetic field. An approximate value of the current potential vector that produces the difference target magnetic field is represented by a polynomial of an eigenvector group of the current potential. The coefficient of each of the terms of the polynomial is determined on the basis of the singular value and the eigenvector group of the magnetic field distribution.

Abstract: A printed circuit board (PCB) block diagram tool for block diagram level editing of a PCB design abstracted from a PCB physical layout tool is disclosed. The PCB block diagram tool includes a plurality of interface objects, a plurality of block objects and interconnect lines. The plurality of interface objects represents interfaces between components. Each of the plurality of interface objects include a plurality of signal, power and ground signal lines without defined physical assignment to pin or pad. The plurality of block objects represents a plurality of physical objects in the PCB physical layout tool. The plurality of blocks are configured to accept the plurality of interface objects. Interconnect lines connect the plurality of interface objects between the plurality of block objects.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: In a method of optimizing parameters of electronic components on printed circuit boards (PCBs), a first experiment table for m variables of one type of parameter of P electronic components on a PCB is designed using n values of each variable and the RSM. P EHs of each first experiment are obtained by simulating, and P EH empirical formulas are computed according to the P EHs. A second experiment table for the m variables is designed using n? values of each variable and the full factorial design, and P EHs of each second experiment are computed using the P EH empirical formulas. Experiments, all the P EHs of which are greater than 1, are filtered from the second experiment tables, and an average EH of each filtered experiment is computed to pick an experiment the average EH of which is the greatest. The values of the m variables in the picked experiment are considered as optimized.

Abstract: An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells.

Abstract: A system and method that can analyze a temperature rise of a printed circuit board (PCB). The system and method receives attribute parameters of the PCB from an input device, and generates a temperature rise formula according to the received attribute parameters. Additionally, the system and method calculates a temperature rise of a local area surrounding each component on the PCB according to the temperature rise formula.

Abstract: Signal tracing across boards and chips can be used to greatly enhance failure analysis of the boards and chips. Concepts are disclosed for tracing one or more signal lines across a board, across a chip boundary, and across a chip. Signals may be traced through active circuitry on a chip along with paths through various logic cones. The result can be graphically and interactively presented.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining the outline information, the boundary information, and the auxiliary line information, when a command for recording position information of points within each of the boundaries is input; obtaining position information of the points within each of the boundaries; setting corresponding height values as height limit of height restriction areas corresponding to the points within each of the boundaries.

Abstract: A computing device and a method selects a signal transmission line from a circuit board, computes an actual length of each line segment of the selected signal transmission line, and computes an actual distance between each line segment of the selected signal transmission line and a corresponding line segment of each neighboring signal transmission line. If each actual length is less than or equal to a corresponding reference length and each actual distance is more than or equal to a corresponding reference distance, the device and method determines a design of the selected signal transmission line satisfies the design standards. Otherwise, if any actual length is more than a corresponding reference length, or if any actual distance is less than a corresponding reference distance, the device and method determines the design of the signal transmission line does not satisfy the design standards.

Abstract: A computing device and a method involves selection of one or more transmission lines from a printed circuit board (PCB) layout file, reading a transmission line from the one or more selected transmission lines, and determining neighboring anti-pads of the read transmission line in the PCB layout file. The computing device and method further determine an actual distance between the read transmission line and a neighboring anti-pad. If the actual distance is less than a preset standard distance, the computing device and method determine that the read transmission line and the neighboring anti-pad do not satisfy design requirements, and highlight the read transmission line and the neighboring anti-pad, to prompt a user to amend design of the read transmission line and the neighboring anti-pad.

Abstract: A computer-implemented method for component arrangement in a PCB layout device is provided. The device includes wiring diagrams. First, generates a PCB encapsulation diagram corresponding to the selected wiring diagram. Then, obtains the coordinates of each electronic component in the selected wiring diagram. Next, generates a prompt to prompt the user to select a reference point in the PCB encapsulation diagram. Then, obtains the coordinates of the reference point. Next, determines an abscissa difference and an ordinate difference between one component in the wiring diagram and the reference point. Then, determines the coordinates of each encapsulated component in the PCB encapsulation diagram according to the abscissa difference, the ordinate difference, and the coordinates of each electronic component in the wiring diagram. And last, moves each encapsulated component to the determined corresponding coordinates of each encapsulated component in the PCB encapsulation diagram.

Abstract: An SSO noise calculating unit estimates the amount of simultaneously operating signal noise caused by simultaneous operations of input/output pins peripheral to a power supply voltage pin as a center. A PLL jitter calculating unit estimates the amount of jitter occurring at the power supply voltage pin by using as an input the estimated amount of simultaneously operating signal noise, and by referencing a correlation between the amount of simultaneously operating signal noise and the amount of jitter, which indicates a correlation calculated beforehand between the amount of simultaneously operating signal noise and the amount of jitter.

Abstract: A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and performing fitting on the combined netlist.

Abstract: A method for merging polygons of a printed circuit board layout system is provided. The system generates PCB files according to the input wiring diagram, and generates polygons and records the profile attributes of each of the generated polygons. The method includes obtaining the profile attributes in response to user input. Then storing the obtained profile attributes and selecting two profile attributes. Then determining whether the polygons are overlapping and recording a new file attribute describing the shape of a new polygon of the two polygons combined shape excluding the lines indicating the overlapping portions of the two polygons. Finally, updating the opened PCB file with the new profile attribute if the polygons are overlapping. A related system is also provided.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining corresponding outlines of selected component and unselected components in response to a user selecting one component; obtaining the range value; generating a reference outline according to the obtained range value and outline of the selected component; performing an intersection operation according to the reference outline and outlines of the unselected components, and determining whether one component is associated within the reference outline; marking and displaying the outlines of the corresponding unselected components when the unselected components are associated within the reference outline.

Abstract: The invention relates to a design method and tool for designing electronic circuits on a printed circuit board, wherein at least one self-contained, pre-composed domain is used, wherein the domain is a module chosen from a pre-composed architecture library, including self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture.

Abstract: A system and method for inspecting layout of a printed circuit board (PCB) provides a graphical user interface (GUI). The GUI displays a layout of the PCB. High side pins of a pulse width modulation (PWM) controller and a component connected to a high side pin are found. If the component is a metallic oxide semiconductor field effect transistor (MOSFET), the system calculate absolute a linear distance and a trace distance between a source pin of the MOSFET and a capacitor pin of a coupling capacitor connected to the source pin. If the linear distance, the trace distance and a capacitance of the coupling capacitor accord with a layout standard, the layout of the PCB is determined to be up to standard.

Abstract: In a routing design method for designing routing of a SiP having first and second routing portions that are connected to each other via bonding wires, whether a DRC error of the first or second routing portion is present or not is determined and the DRC error is selected when the DRC error is present. A plurality of nets associated with the selected DRC error are specified and the routes of the specified nets are removed. Then, bonding wire allocations of the specified nets are changed. Further, the specified nets are rerouted so as not to cause a DRC error and whether the rerouting result is accepted or not is determined.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located at a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is approximately axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is approximately axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: Layout information indicating locations of at least components and conductive layers in a printed circuit board, and layouts of conductive wiring patterns on the respective conductive layers and vias which electrically connect between the conductive layers is obtained from a memory. With reference to the layout information, path information indicating a path of one signal line is generated. With reference to the layout information and path information, a divide portion where a path of a return current corresponding to a signal current of the signal line is divided are detected. With reference to the layout information and path information, information indicating a detour path of the return current in a neighborhood of the divide portion is generated.

Abstract: A description is given of a method for the computer-aided construction of flexible printed circuit boards that are arranged in a housing (10) of a device. The method provides a 3D model for determining the fixed points (1 to 4) of the printed circuit board, such as fastening points and connecting points, and a 2D model based on a development of a skeleton model (20) of the printed circuit board, for creating a printed circuit board design (40) comprising a printed circuit board contour and a printed circuit board layout. The two development environments are uniquely assigned to one another.

Abstract: A wiring design method for a wiring board comprises, if design rule errors are found in the wiring design, selecting one of the design rule errors as a selected design rule error, specifying a predetermined number of the second connection terminals as selected second connection terminals that correspond to the selected design rule error, and moving the selected second connection terminals to predetermined coordinate positions. Each time when the selected second connection terminals are moved to the post-movement coordinate positions, the method comprises connecting the second connection terminals and the first connection terminals, conducting the design rule check, and determining whether no design rule errors are detected newly and the selected design rule error is not detected either.

Abstract: In designing an integrated circuit on a die having a set of die bumps, a method to generate a set of lumped circuit parameter values associated with the set of die bumps, based upon distances between the set of die bumps and the center of the die, the method also based upon a sample-data distribution function of a die bump distance variable and a sample-data distribution function of a lumped circuit parameter variable. Other embodiments are described and claimed.

Abstract: Disclosed is a layout tool that verifies the operability of a printed circuit board design. Electrical parameters may be calculated for wire traces that are laid out for a given design. Based on the voltage drop calculations and the voltage and current requirement of the various system components, the layout tool may determine if a given system component will remain within its required operating range. The layout tool may additionally be operable to verify proper spacing between traces that make up a differential signal and to verify that certain pins of integrated circuit are properly connected.

Abstract: A printed circuit board analyzing system for analyzing the whole circuit of a multilayer printed circuit board to perform circuit analysis of noise propagation in the printed circuit board having structure in which the shapes of stacked conductor planes are different or planes are provided side by side in the same layer by quickly providing an adjacent interference part equivalent circuit model representing noise interference parts causing interference between adjacent opposed planes and by coupling the plane pairs to the adjacent interference part equivalent circuit.

Abstract: A computing system includes a drawing unit and a layout unit. The computing system sets components parameters to components of a circuit diagram of a printed circuit board (PCB). The drawing unit draws the circuit diagram by using the components with the components parameters. If the drawing unit wants to use a component more than once, the computing system copies the component and the corresponding components parameters. The drawing unit uses the copied components and the corresponding parameters. If the circuit diagram has been drawn, the layout unit loads the circuit diagram and wires the PCB according to the components and the components parameters in the circuit diagram.

Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.

Abstract: An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output.

Abstract: A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.

Abstract: A disclosed device includes a simulation apparatus which simulates a shift in signal characteristics occurring in a wiring pattern formed in a printed wiring board including a first database that stores wiring pattern attribute information and wiring pattern positional information, a second database storing solid lack portion size information and solid lack portion positional information, a third database that stores shift amount information relative to positional relationships between the wiring patterns and the solid lack portions, a shift amount processing unit configured to obtain the shift amount of the signal characteristics in the wiring pattern corresponding to the wiring pattern attribute information which is input based on the wiring pattern positional information corresponding to the wiring pattern attribute information which is input, the solid lack portion positional information, the solid lack portion size information, and the shift amount information.

Abstract: A circuit board with double-sided universal circuit layout for laying out electronic components has a first side with a first circuit layout thereon and an opposing second side with a second circuit layout thereon; hence, the first circuit layout and the second circuit layout are disposed on the opposing sides of the circuit board, respectively. The first circuit layout and the second circuit layout feature electronic circuits having the same function, thereby allowing users to selectively install the electronic components at one of the first circuit layout and the second circuit layout as needed and still have access to the electronic circuits having the same function. A layout method for use with the circuit board with double-sided universal circuit layout is further introduced.

Abstract: A printed circuit board with reduced signal distortion, including one or more layers of non-conductive substrate upon which are disposed conductive pathways that conduct signals, the signals characterized by distortion at least partly caused by orientation of the conductive pathways on the layers of the printed circuit board, and a periodically patterned reference plane; each conductive pathway that conducts signals oriented orthogonally or diagonally at forty-five degrees with respect to other conductive pathways that conduct signals on the printed circuit board; the periodically patterned reference plane comprising a conductor having discontinuities arranged in a periodically recurring pattern, the pattern of the discontinuities oriented on a surface of a layer of the printed circuit board at an optimum angle, with respect to the conductive pathways that conduct signals on the printed circuit board, that reduces distortion of the signals.

Abstract: A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided.

Abstract: In a computer aided design (CAD) apparatus, an association-data acquiring unit acquires association data that defines an association between pins of a first connector and those of a second connector to be connected to the first connector, and an assignment of signals to the pins. A part-information acquiring unit acquires information including a symbol of the first connector. A layout-condition acquiring unit acquires a layout condition to lay out the symbol of the first connector on a circuit diagram. A circuit diagram creating/updating unit lays out the symbol of the first connector on the circuit diagram based on the layout condition, and adds a net name indicating a signal assigned to each of the pins to the symbol.

Abstract: A method to avoid malconnections with respect to voltage levels of electronic components of a circuit board during circuit board design is described, comprising the steps of: creation of a Component Specification Library (CSL) comprising at least distinct pinnames and assigned voltage data; creation of groups of pins of components to be connected with each other on a particular voltage level according to the circuit board design; verification of the voltage data of the pins of the components within the particular group.

Abstract: A method implemented by a computer layout software for setting the width of the printed circuit board trace is disclosed. The method selects one from several traces set on the printed circuit board traces, obtains the corresponding trace name of the selected trace, obtains the device pin connected to the selected trace, acquires the pad corresponding to the device pin, reads the width of the pad, and adjusts the width of the pad.

Abstract: A circuit board analyzer includes a storage unit for storing mesh position information on an analyzed mesh-division model and extracted circuit constants in relation to each other; a division-model configuration unit for dividing the layout of a circuit board into meshes to configure a new mesh-division model; an identical-mesh determination unit for making a comparison between mesh position information on the new mesh-division model and mesh position information on the analyzed mesh-division model to determine identical meshes that have identical mesh position information; and a circuit-constant extraction unit for performing analytical processing based on the new mesh-division model to extract new circuit constants and reusing, as a new circuit constant associated with the identical meshes, an extracted circuit constant that is related to the mesh position information on the identical meshes.

Abstract: A method for setting a test point is applied to dispose at least one test point on a circuit board in a trace file, which includes steps of reading the trace file, in which the trace file includes at least one trace; determining whether the trace has an initial test point; and setting a test point on the trace that does not have the initial test point. According to the method for setting a test point, cost and time for manually disposing the test point are saved, and an error rate when the test point is arranged is further reduced, thereby effectively improving production efficiency of the circuit board.

Abstract: A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.