Abstract: Disclosed are an exposure method and a method of manufacturing a mask and a semiconductor device using the same, which minimize time taken by mask data preparation (MDP) to optimize a total exposure process and enhance a quality of a pattern by using an inverse solution concept, based on a multi-beam mask writer. The exposure method includes receiving mask tape output (MTO) design data obtained through optical proximity correction (OPC), preparing mask data, including a job deck, for the MTO design data without a data format conversion, performing complex correction, including proximity effect correction (PEC) of an error caused by an e-beam proximity effect and mask process correction (MPC) of an error caused by an exposure process, on the mask data, generating pixel data, based on data for which the complex correction is performed, and performing e-beam writing on a substrate for a mask, based on the pixel data.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

Abstract: The invention relates to a method for locally deforming an optical element for photolithography in accordance with a predefined deformation form comprising: (a) generating at least one laser pulse having at least one laser beam parameter; and (b) directing the at least one laser pulse onto the optical element, wherein the at least one laser beam parameter of the laser pulse is selected to yield the predefined deformation form.

Abstract: A method for detecting photolithographic hotspots is disclosed. After receiving layout data, an aerial image simulation is conducted to extract aerial image intensity indices. Based on the combination of one or more aerial image intensity indices, various aerial image detectors are generated. The value of aerial image detectors is verified to determine the position and type of the photolithographic hotspots.

Abstract: The invention discloses a method for measuring positions of structures on a mask and thereby determining mask manufacturing errors. It is shown, that from a plurality measurement sites an influence of an optical proximity effect on a position measurement of structures on the mask, is determined with a metrology tool. A rendered image of the data representation of the structures is obtained. Additionally, at least one optical image of the pattern within the area on the mask is captured with the imaging system of the metrology tool. The field of view of the metrology tool is approximately identical to the size of the selected area of the mask design data. Finally, a residual is determined, which shows the manufacturing based proximity effect.

Abstract: A method of efficient simulating imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes the steps of determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and generating the simulated image utilizing the function, where the simulated image represents the imaging result of the target design for the lithographic process.

Abstract: According to a method of preparing a layout of semiconductor circuit elements, a computer processor determines a first value of a distance metric that describes a separation between at least one well of a first type and at least one well of a second type in a first layout of a circuit design represented in a memory coupled to the computer processor. The at least one well of the first type and the at least one well of the second type are rearranged into a second layout. The method determines a second value of the distance metric that describes separation between the at least one well of the first type and the at least one well of the second type in the second layout. The second layout is stored in response to the second value of the distance metric being greater than the first value of the distance metric.

Abstract: A method for generating a pattern of a mask includes obtaining data of a plurality of polygons representing a plurality of pattern elements, grouping polygons which overlap or contact with each other among the plural polygons in one group, not setting an evaluation position for evaluating an image of a pattern of the one group on a line segment of sides which overlap or contact with each other among sides of the polygon of the one group, and setting an evaluation position at a portion except for the line segment, and repeating calculating the image of the pattern of the one group, evaluating the calculated image at the set evaluation position, and correcting the pattern based on a result of the evaluating, and generating the pattern of the mask based on a result of the repeating step.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.

Abstract: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether ?1<?1, wherein ?1 represents model vs. exposure difference and ?1 represents predetermined criteria. The technique further includes completing the model when ?1<?1.

Abstract: A method, apparatus and program product automatically generate a grayscale lithography mask file (76) from a three dimensional (3D) model (72) of a desired topography, e.g., as generated by a three dimensional computer aided design (CAD) tool (70).

Abstract: A method 100, a computer program product and a system of checking an integrated circuit layout for instances of a reference pattern is provided The method 100 comprises the steps of: i) receiving 102 the integrated circuit layout, ii) receiving 104 a drawing of the reference pattern from a user, iii) deducting 106 a basic pattern definition from the drawn reference pattern, iv) determining 108 a set of topological relation based on the drawn reference pattern, v) forming 110 a complex pattern description which is a combination of the deducted basic pattern definition and the set of topological relations, vi) checking 112 the integrated circuit layout for patterns that match the complex pattern description to find instances of the reference pattern in the integrated circuit layout, and vii) storing 114 found instances of the reference pattern.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes inputting DSA target patterns. The DSA target patterns are grouped into groups including a first group and a group boundary is defined around the first group as an initial OPC mask pattern. A circle target is generated around each of the DSA target patterns in the first group to define a merged circle target boundary. The initial OPC mask pattern is adjusted and/or iteratively updated using the merged circle target boundary to generate an output final OPC mask pattern.

Abstract: A semiconductor device includes a semiconductor chip which includes a first circuit and a second circuit that are spaced apart from each other, without internal wirings electrically connecting the first circuit and the second circuit to each other, a substrate on which the semiconductor chip is disposed, and substrate wirings that are arranged on the substrate and electrically connect the first circuit and the second circuit to each other.

Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.

Abstract: A two-stage, passive, RC polyphase filter for mm-wave quadrature LO generation is presented. The filter features an innovative, symmetrical layout structure, which is more robust to parasitics than the conventional layout. Layout parasitics which become important at mm-wave frequencies are identified and a compensated. Impedance variations and transfer functions are evaluated considering these dominant parasitics. More than 15 dB improvement in image rejection ratio is achieved in comparison with conventional layouts. Using the inventive techniques more than 35 dB of image rejection ratio over a bandwidth of 6 GHz is demonstrated in an outphasing transmitter at 60 GHz in 40 nm CMOS.

Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage.

Abstract: A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract: Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: A coating and developing treatment apparatus includes a substrate transfer mechanism; and a defect inspection section. A transfer control part controls transfer of a substrate. A defect classification part classifies a defect based on the state of the defect. A storage part stores a transfer route of the substrate by the substrate transfer mechanism when the substrate has been treated by treatment sections. A defective treatment specification part specifies, based on a kind of the defect classified by the defect classification part and the transfer route of the substrate stored in the storage part, a treatment section which is a cause of occurrence of the classified defect, and judges presence or absence of an abnormality of the specified treatment section. The transfer control part controls the substrate transfer mechanism to transfer a substrate bypassing the treatment section which has been judged to be abnormal by the defective treatment specification part.

Abstract: A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC.

Abstract: A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: A method and system for fracturing or mask data preparation or proximity effect correction is disclosed in which a series of charged particle beam shots is determined, where the series of shots is capable of forming a continuous non-manhattan track on a surface, such that the non-manhattan track has a line width roughness (LWR) which nearly equals a target LWR. A method and system for fracturing or mask data preparation or proximity effect correction is also disclosed in which at least two series of shots are determined, where each series of shots is capable of forming a continuous non-manhattan track on a surface, and where the space between tracks has space width roughness (SWR) which nearly equals a target SWR.

Abstract: The invention relates to a lithography system for patterning a target, said system comprising a feedback control system comprising an actuator for displacing the target, a measurement system for measuring a position of said target, and a control unit adapted for controlling the actuator based on the position measured by the measurement system, said feedback control system having a first latency being a maximum latency between measuring and controlling the actuator based on said measuring, a storage system for storing the measured positions, comprising a receive buffer and a storage unit with a second latency being an average latency between receiving measured positions in the receive buffer and storing said measured positions in the storage unit, wherein the first latency is at least an order of magnitude smaller than the second latency, the feedback control system comprising a unidirectional connection for transmitting said measured positions to the storage system.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation.

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract: A system and method provide semiconductor fabrication mask creation techniques that align the device features patterned with a first core mask with one or more pad features patterned with a subsequent pad mask. Shapes representing the pad features may be included in the core mask by reducing on all sides, the shape of the pad feature in the core mask by the width of the spacer material. A pad mask then may be created to include a shape of the pad feature that may overlap a portion of the spacer material pattern created by the shape of the pad feature in the core mask. Data sets may be generated from a circuit design to create the masks that may be fabricated with the described techniques.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.

Abstract: Systems, methods, and other embodiments associated with dynamically generating jog patches are described. In one embodiment, a method includes determining a virtual edge within metal of a design at a jog rule violation. The design is a design of an integrated circuit and the virtual edge is an edge of a rectangle associated with one or more edges of the jog rule violation. The example method may also include dynamically generating a jog patch by expanding the metal from the virtual edge.

Abstract: Methods and systems for designing a binary spatial filter based on data indicative of a desired exposure condition to be emulated by an inspection system, and for implementing the binary spatial filter in an optical path of the inspection system, thereby enabling emulation of the desired exposure condition by interacting a light beam of the inspection system with the binary spatial filter. The present method and systems enable on-the-fly and on-demand design and implementation/generation of spatial filters for use in inspection systems.

Abstract: In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region.

Abstract: Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region.

Abstract: A method of forming a mask includes creating a difference map between a desired intra-field pattern that is to be formed on substrates and an intra-field signature pattern. The intra-field signature pattern represents a pattern formed on an example substrate by an exposure field using an example E-beam-written mask. Modifications are determined to formation of mask features to be made using an E-beam mask writer if forming a modified E-beam-written mask having mask features modified from that of the example E-beam-written mask that will improve substrate feature variation identified in the difference map. The E-beam mask writer is programmed using the determined modifications to improve the substrate feature variation identified in the difference map. It is used to form the modified E-beam-written mask having the modified mask features. One or more substrates are photolithographically processed using the modified E-beam-written mask.

Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.

Abstract: A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle.

Abstract: A pattern measurement device includes: a storage section storing mask edge data of a circuit pattern and image data obtained by imaging the circuit pattern; an SEM contour extracting section receiving the image data, SEM contour of the circuit pattern, and cause an exposure simulator to generate estimated SEM contour data of an estimated SEM contour on the basis of the mask edge data and SEM contour data of the extracted SEM contour; a shape classifying section receiving the mask edge data, the SEM contour data, and the estimated contour data to classify the SEM contour data and the estimated SEM contour data into a one-dimensionally shaped contour and a two-dimensionally shaped contour; and an SEM contour sampling section receiving the SEM contour data and the estimated SEM contour data to sample the SEM contour data on the basis of types of the one-dimensionally and two-dimensionally shaped contours.

Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.

Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.

Abstract: A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed between the central core and outer pattern portions, and transition region shots are generated so as to produce in the transferred pattern a smooth transition in pattern characteristics such as line edge roughness or period of waviness, from the central core portion of the pattern to the outer portion of the pattern. A pattern determined by the transition region shots is then compared to a reticle pattern created using conventional non-overlapping VSB shots. Methods for forming a semiconductor device layout pattern on a reticle or substrate are also disclosed.