Analysis And Verification (process Flow, Inspection) Patents (Class 716/51)
  • Patent number: 11029610
    Abstract: A method for determining one or more optimized values of an operational parameter of a sensor system configured for measuring a property of a substrate. The method includes: determining a quality parameter for a plurality of substrates; determining measurement parameters for the plurality of substrates obtained using the sensor system for a plurality of values of the operational parameter; comparing a substrate to substrate variation of the quality parameter and a substrate to substrate variation of a mapping of the measurement parameters; and determining the one or more optimized values of the operational parameter based on the comparing.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 8, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Patricius Aloysius Jacobus Tinnemans, Edo Maria Hulsebos, Henricus Johannes Lambertus Megens, Ahmet Koray Erdamar, Loek Johannes Petrus Verhees, Willem Seine Christian Roelofs, Wendy Johanna Martina Van De Ven, Hadi Yagubizade, Hakki Ergün Cekli, Ralph Brinkhof, Tran Thanh Thuy Vu, Maikel Robert Goosen, Maaike Van T Westeinde, Weitian Kou, Manouk Rijpstra, Matthijs Cox, Franciscus Godefridus Casper Bijnen
  • Patent number: 11029609
    Abstract: A method including: simulating an image or characteristics thereof, using characteristics of a design layout and of a patterning process, determining deviations between the image or characteristics thereof and the design layout or characteristics thereof; aligning a metrology image obtained from a patterned substrate and the design layout based on the deviations, wherein the patterned substrate includes a pattern produced from the design layout using the patterning process; and determining a parameter of a patterned substrate from the metrology image aligned with the design layout.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 8, 2021
    Assignee: ASML Netherlands B.V.
    Inventor: Te-Sheng Wang
  • Patent number: 11016395
    Abstract: A method including: obtaining a thin-mask transmission function of a patterning device and a M3D model for a lithographic process, wherein the thin-mask transmission function represents a continuous transmission mask and the M3D model at least represents a portion of M3D attributable to multiple edges of structures on the patterning device; determining a M3D mask transmission function of the patterning device by using the thin-mask transmission function and the M3D model; and determining an aerial image produced by the patterning device and the lithographic process, by using the M3D mask transmission function.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: May 25, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Yu Cao, Yen-Wen Lu, Peng Liu, Rafael C. Howell, Roshni Biswas
  • Patent number: 11017147
    Abstract: System and methods for an edge-based camera are disclosed. Semiconductor layout designs are a representation of an integrated circuit that are used to manufacture the integrated circuit. Parts of the layout design, such as points of Interest (POIs), may be subject to analysis with regard to a downstream application, such as hotspot detection. Unlike pixel-based characterizations, POIs are characterized using topological features indicative of quantized values and dimensional features indicative of analog values. For example, an edge may be characterized using a set of relations, which characterizes corners and polygons (including the polygon on which the POI resides and external polygons). In turn, the set of relations may be used to define image representations, including images in different directions relative to the POI (including cardinal and ordinal image). In this way, the topological/dimensional characterization of the POI may be used to analyze the POI in the layout design.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 25, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Hazem Hegazy, Ahmed Hamed Fathi Hamed, Omar Elsewefy
  • Patent number: 10909294
    Abstract: Methods for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 2, 2021
    Assignee: D2S, Inc.
    Inventor: P. Jeffrey Ungar
  • Patent number: 10867108
    Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bing-Siang Chao
  • Patent number: 10762272
    Abstract: The present disclosure provides a pattern density analysis method for analyzing a local pattern density of a layout, the method comprising: obtaining a pattern attribute of each layout pattern located on a layout region to be analyzed; setting, for each layout pattern, a relevant window for the layout pattern based on the corresponding pattern attribute; calculating the pattern density of each relevant window; and selecting the maximum value of the pattern densities of the relevant windows as the maximum local pattern density of the layout, and selecting the minimum value of the pattern densities of the relevant windows as the minimum local pattern density of the layout.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 1, 2020
    Inventors: Wei Cheng, Zhonghua Zhu, Fang Wei
  • Patent number: 10732499
    Abstract: Aspects of the disclosed technology relate to techniques for achieving optical proximity correction cross-tile consistency. A layout design is divided into a plurality of regions. Optical proximity correction iterations are performed on each of the plurality of regions to generate a modified layout design. Based on the modified layout design and the layout pattern surrounding each of the edge fragments in the modified layout design, a final modified layout design is generated such that the edge fragments in different regions in the plurality of regions in the final modified layout design having the same layout pattern have a same edge adjustment value with respect to the layout design.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Mentor Graphics Corporation
    Inventor: George P. Lippincott
  • Patent number: 10705514
    Abstract: Systems and methods for controlling device performance variability during manufacturing of a device on wafers are disclosed. The system includes a process platform, on-board metrology (OBM) tools, and a first server that stores a machine-learning based process control model. The first server combines virtual metrology (VM) data and OBM data to predict a spatial distribution of one or more dimensions of interest on a wafer. The system further comprises an in-line metrology tool, such as SEM, to measure the one or more dimensions of interest on a subset of wafers sampled from each lot. A second server having a machine-learning engine receives from the first server the predicted spatial distribution of the one or more dimensions of interest based on VM and OBM, and also receives SEM metrology data, and updates the process control model periodically (e.g., to account for chamber-to-chamber variability) using machine learning techniques.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Samer Banna
  • Patent number: 10698320
    Abstract: A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ru-Gun Liu, Shih-Ming Chang, Shuo-Yen Chou, Zengqin Zhao, Chien Wen Lai
  • Patent number: 10691015
    Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-tone mask with a plurality of mask tones is described. The method generates a transmission function matrix based on a setting of the multi-tone mask. The method applies the transmission function matrix to transform a formula for calculating light intensity from Abbe's form to Hopkins' form while maintaining the accuracy of Abbe's form. The method then computes the light intensity using the transformed formula.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: June 23, 2020
    Inventors: Hongbo Zhang, Qiliang Yan
  • Patent number: 10657215
    Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 19, 2020
    Assignee: Arm Limited
    Inventor: Paul Christopher de Dood
  • Patent number: 10634886
    Abstract: In a method for three-dimensionally measuring a 3D aerial image in the region around an image plane during the imaging of a lithography mask, which is arranged in an object plane, a selectable imaging scale ratio in mutually perpendicular directions (x, y) is taken into account. For this purpose, an electromagnetic wavefront of imaging light is reconstructed after interaction thereof with the lithography mask. An influencing variable that corresponds to the imaging scale ratio is included. Finally, the 3D aerial image measured with the inclusion of the influencing variable is output. This results in a measuring method with which lithography masks that are optimized for being used with an anamorphic projection optical unit during projection exposure can also be measured.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Ulrich Matejka, Christoph Husemann, Johannes Ruoff, Sascha Perlitz, Hans-Jürgen Mann
  • Patent number: 10578963
    Abstract: Methods, apparatuses, and systems for determining a binary mask pattern from a pixelated mask pattern include: determining, by a processor, based on a fast marching method (FMM), arrival values for pixels of a portion of the pixelated mask pattern; determining the binary mask pattern based on the arrival values; and updating at least one of the arrival values based on a comparison between a design pattern corresponding to the pixelated mask pattern and a substrate pattern simulated based on the binary mask pattern.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 3, 2020
    Assignee: ASML US, LLC
    Inventors: Yuan He, Jie Lin, Jihui Huang
  • Patent number: 10565702
    Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: February 18, 2020
    Assignee: Dongfang Jingyuan Electron Limited
    Inventors: Zhaoli Zhang, Jie Lin, Hua-yu Liu, Zongchang Yu
  • Patent number: 10551827
    Abstract: An inspection system includes a controller communicatively coupled to a physical inspection device (PID), a virtual inspection device (VID) configured to analyze stored PID data, and a defect verification device (DVD). The controller may receive a pattern layout of a sample including multiple patterns fabricated with selected lithography configurations defining a process window, receive locations of PID-identified defects identified through analysis of the sample with the PID, wherein the PID-identified defects are verified by the DVD, remove one or more lithography configurations associated with the locations of the PID-identified defects from the process window, iteratively refine the process window by removing one or more lithography configurations associated with VID-identified defects identified through analysis of selected portions of stored PID data with the VID, and provide, as an output, the process window when a selected end condition is met.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: February 4, 2020
    Assignee: KLA-Tencor Corporation
    Inventor: Brian Duffy
  • Patent number: 10546773
    Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasunori Uchino, Kenichi Watanabe
  • Patent number: 10545490
    Abstract: There are provided a method of generating an inspection recipe usable for inspecting an inspection area of a specimen and a recipe generating unit. The recipe generating unit is configured: upon obtaining design data informative of design structural elements comprised in a design PoI corresponding to the at least one PoI, to provide global segmentation of a test image captured by an inspection tool unit from the inspection area and comprising at least one test PoI of substantially the same design as the at least one PoI, thereby to obtain segmented structural elements comprised in the test PoI and segmentation configuration data; to associate the segmented structural elements comprised in the test PoI with the design structural elements comprised in the design PoI, thereby to obtain design association data; and to generate an inspection recipe comprising, at least, segmentation configuration data and design association data.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 28, 2020
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Michele Dalla-Torre, Amit Batikoff, Efrat Rozenman, Ron Katzir, Imry Kissos
  • Patent number: 10541978
    Abstract: Generally, embodiments of the invention are directed to methods, computer readable medium, servers, and systems for deidentified access of data. The deidentified access is permitted with the use of an identifier that uniquely indicates an outcome, the coding of the identifier obscures unaided human interpretation of the outcome, and the identifier uniquely identifies data for remediating performance associated with future outcomes.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: January 21, 2020
    Assignee: PEARSON EDUCATION, INC.
    Inventors: Vishal Kapoor, Cole Joseph Cecil, David Earl Rodgers
  • Patent number: 10534891
    Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Woohyun Chung, Gi-Joon Nam, Lakshmi N. Reddy
  • Patent number: 10536433
    Abstract: Generally, embodiments of the invention are directed to methods, computer readable medium, servers, and systems for deidentified access of data. The deidentified access is permitted with the use of an identifier that uniquely indicates an outcome, the coding of the identifier obscures unaided human interpretation of the outcome, and the identifier uniquely identifies data for remediating performance associated with future outcomes.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: January 14, 2020
    Assignee: PEARSON EDUCATION, INC.
    Inventors: Vishal Kapoor, Cole Joseph Cecil, David Earl Rodgers
  • Patent number: 10509217
    Abstract: A microscope has a light source for generating a light beam having a wavelength, ?, and beam-forming optics configured for receiving the light beam and generating a Bessel-like beam that is directed into a sample. The beam-forming optics include an excitation objective having an axis oriented in a first direction. Imaging optics are configured for receiving light from a position within the sample that is illuminated by the Bessel-like beam and for imaging the received light on a detector. The imaging optics include a detection objective having an axis oriented in a second direction that is non-parallel to the first direction. A detector is configured for detecting signal light received by the imaging optics, and an aperture mask is positioned.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 17, 2019
    Assignee: Howard Hughes Medical Institute
    Inventor: Robert E. Betzig
  • Patent number: 10496785
    Abstract: A CMP simulation method includes inputting a chip pattern layout including a plurality of graphic patterns, partitioning the chip pattern layout into targeting grids including a plurality of surrounding grids, and then calculating grid geometry characteristics of the targeting grids. The method also includes generating shifted grids by shifting the targeting grids, calculating weighted average grid geometry characteristics of the targeting grids and the shifted grids, and locating first hot spots on the chip pattern layout by performing a CMP simulation based on the grid geometry characteristics of the targeting grids. Further, the method includes generating optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots, and then locating second hot spots on the chip pattern layout by performing the CMP simulation based on the optimized grid geometry characteristics.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 3, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Zheng Fang Liu, Xue Li
  • Patent number: 10444622
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10363235
    Abstract: The present disclosure provides compositions comprising 15-HEPE and methods of using same for treating and/or preventing fibrosis in a subject in need thereof.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 30, 2019
    Assignee: Afimmune Limited
    Inventors: Jonathan Rowe, Kevin Duffy, John Climax
  • Patent number: 10318697
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Patent number: 10303830
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 28, 2019
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 10222690
    Abstract: A mask optimization method for optimizing a target mask used for a partial coherent system including a plurality of spatial filters is provided. The mask optimization method includes obtaining a trainer mask that is an optimized sample mask by performing a mask optimization on a sample mask, generating a mask optimization estimation model by performing a pixel-based learning using, as a feature vector of each of pixels of the trainer mask, partial signals of each of the pixels of the trainer mask respectively determined based on the spatial filters and using, as a target value, a degree of overlap between each of the pixels and a mask polygon of the trainer mask, and performing a mask optimization on the target mask using the mask optimization estimation model.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Moon-Gyu Jeong
  • Patent number: 10185796
    Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 22, 2019
    Assignee: ARM Limited
    Inventor: Paul Christopher de Dood
  • Patent number: 10140400
    Abstract: Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 27, 2018
    Assignee: Dongfang Jingyuan Electron Limited
    Inventors: Zongchang Yu, Jie Lin, Zhaoli Zhang
  • Patent number: 10113864
    Abstract: A method for determining a registration error of a feature on a mask, including providing a first aerial image that was captured by means of a position measuring device and includes at least the feature, simulating, from pattern specifications of the mask, a second aerial image that includes at least the feature, taking into account at least one effect that causes distortion of the first aerial image, and determining the registration error of the feature as the distance of the position of the feature in the first aerial image from the position of the feature in the second aerial image. Also provided is a method for simulating an aerial image from pattern specifications of a mask and a position measuring device for carrying out the method.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: October 30, 2018
    Assignees: Carl Zeiss SMT GmbH, Carl Zeiss Meditec AG
    Inventors: Michael Arnz, Dirk Seidel, Gerd Klose
  • Patent number: 10067425
    Abstract: Disclosed are techniques for correcting the EUV crosstalk effects. Isolated mask feature component diffraction signals associated with individual layout feature components are determined based on a component-based mask diffraction modeling method such as a domain decomposition method. Mask feature component diffraction signals are then determined based on the isolated mask feature component diffraction signals, layout data and predetermined crosstalk signals. Here, the predetermined crosstalk signals are derived based on mask feature component diffraction signals computed using an electromagnetic field solver and the component-based mask diffraction modeling method, respectively. The mask feature component diffraction signals are then used to process layout designs.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: September 4, 2018
    Assignee: Mentor Graphics Corporation
    Inventor: Michael Lam
  • Patent number: 10025177
    Abstract: A method of making a photomask includes constructing a transmission cross coefficient (TCC) matrix representing an illumination source for supplying light to transmit through the photomask and a pupil for focusing the transmitted light onto a target substrate to produce a set of main features, generating kernels through decomposition of the TCC matrix, selecting ones of the kernels having odd symmetry, generating a field map kernel as a sum of self-convolutions of the odd symmetry kernels, generating a first field map by convolving an area of the photomask corresponding to the set of main features with the field map kernel, and making the photomask corresponding to the first field map. The method may include assigning first sub-resolution assist features (SRAFs) to those portions of the photomask area having corresponding said first field map values exceeding a nonnegative threshold, and making the photomask corresponding to the main features and first SRAFs.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: July 17, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mindy Lee, Jung H. Woo
  • Patent number: 9934350
    Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: April 3, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Hua-Yu Liu
  • Patent number: 9929733
    Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Pratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du
  • Patent number: 9905487
    Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of V0 via opens.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 27, 2018
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9905553
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one metal-short-related failure mode.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: February 27, 2018
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9891421
    Abstract: A microscope has a light source for generating a light beam having a wavelength, ?, and beam-forming optics configured for receiving the light beam and generating a Bessel-like beam that is directed into a sample. The beam-forming optics include an excitation objective having an axis oriented in a first direction. Imaging optics are configured for receiving light from a position within the sample that is illuminated by the Bessel-like beam and for imaging the received light on a detector. The imaging optics include a detection objective having an axis oriented in a second direction that is non-parallel to the first direction. A detector is configured for detecting signal light received by the imaging optics, and an aperture mask is positioned.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 13, 2018
    Assignee: Howard Hughes Medical Institute
    Inventor: Robert E. Betzig
  • Patent number: 9870966
    Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 16, 2018
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9866954
    Abstract: Performance metric based stopping criteria for iterative algorithm techniques are described. In one or more implementations, a training dataset is processed by one or more computing devices using an iterative algorithm having a cost function. The processing includes, for a plurality of iterations of the iterative algorithm, computing a cost for the iterative algorithm using the cost function and a value for each of a plurality of performance metrics that are usable to infer accuracy of the iterative algorithm for a respective one of the iterations. Responsive to the processing, a particular one of the plurality of iterations is identified as a stopping criterion based at least in part on the computed values for the plurality of performance metrics and the stopping criterion is output to configure the iterative algorithm to use the stopping criterion for subsequent processing of data by the iterative algorithm.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: January 9, 2018
    Assignee: ADOBE SYSTEMS INCORPORATED
    Inventors: Francois G. Germain, Gautham J. Mysore
  • Patent number: 9864831
    Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Guoxiang Ning, Guido Ueberreiter, Lloyd C. Litt, Paul Ackmann
  • Patent number: 9858379
    Abstract: According to one embodiment, in a mask data generation system, a first acquisition part is configured to acquire pattern contour data included in each of a plurality of layout candidate data for a first layer. A second acquisition part is configured to acquire pattern contour data included in layout data for a second layer. A superimposing part is configured to superimpose the contour data acquired by the first acquisition part and the contour data acquired by the second acquisition part with each other, for each of the plurality of layout candidate data. An area calculation part is configured to calculate an overlap area between a first pattern in the contour data acquired by the first acquisition part and a second pattern in the contour data acquired by the second acquisition part, based on the superimposed data, for each of the plurality of layout candidate data.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuyoshi Morisaki, Satoshi Usui
  • Patent number: 9859100
    Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 2, 2018
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Kazuyuki Hagiwara, Robert C. Pack
  • Patent number: 9798851
    Abstract: A method for DRC verification of a design layout file comprising off-grid patterns includes identifying an off-grid pattern having one or more off-grid sides, outwardly expanding the one or more off-grid sides to adjacent grids to obtain a first on-grid pattern, inwardly contracting the expanded one or more sides of the first on-grid pattern to adjacent grids to obtain a second on-grid pattern, and performing a DRC verification on the second on-grid pattern using an existing on-grid DRC deck. The method also includes making a backup copy of the design layout file prior to converting the identified off-grid pattern into an on-grid pattern.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 24, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Shaofeng Yu, Yihua Shen, Jian Pan, Fenghua Fu, Yunchu Yu
  • Patent number: 9793253
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one metal-short-related failure mode.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 17, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9785046
    Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
  • Patent number: 9761573
    Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: September 12, 2017
    Assignee: PDF Solutions, Inc.
    Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
  • Patent number: 9734277
    Abstract: A method designs a semiconductor device that includes first and second wirings provided in an uppermost of wiring layers, and a setting part coupled to the first and second wirings and including third and fourth wirings provided in each of the wiring layers, and vias that electrically connect wirings of different wiring layers, wherein each of the third and fourth wirings in each of the wiring layers extends in one of 2 mutually perpendicular directions, and the third and fourth wirings in the wiring layers are arranged and connected so as to turn around using the vias as turn-around points. The method modifies a direction in which the third and fourth wirings extend in one wiring layer specified by layer information, and modifying a connection of the first and second wirings with respect to the third and fourth wirings in a lowermost of the wiring layers.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 15, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Kenta Goshima, Fumitaka Shiraishi, Yoshihiko Masushio, Yasuhiro Yokoi, Hideyuki Shimizu
  • Patent number: 9703922
    Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 11, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: James Word, Nicolas B. Cobb, Patrick J. LaCour
  • Patent number: 9697313
    Abstract: In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 4, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Mark William Bales, Jeffrey Jude Loescher, Paul Furnanz