Abstract: In a method for three-dimensionally measuring a 3D aerial image in the region around an image plane during the imaging of a lithography mask, which is arranged in an object plane, a selectable imaging scale ratio in mutually perpendicular directions (x, y) is taken into account. For this purpose, an electromagnetic wavefront of imaging light is reconstructed after interaction thereof with the lithography mask. An influencing variable that corresponds to the imaging scale ratio is included. Finally, the 3D aerial image measured with the inclusion of the influencing variable is output. This results in a measuring method with which lithography masks that are optimized for being used with an anamorphic projection optical unit during projection exposure can also be measured.

Abstract: Methods, apparatuses, and systems for determining a binary mask pattern from a pixelated mask pattern include: determining, by a processor, based on a fast marching method (FMM), arrival values for pixels of a portion of the pixelated mask pattern; determining the binary mask pattern based on the arrival values; and updating at least one of the arrival values based on a comparison between a design pattern corresponding to the pixelated mask pattern and a substrate pattern simulated based on the binary mask pattern.

Abstract: Methods and systems for inspecting integrated circuits are provided. The method includes monitoring an inspection of integrated circuits to receive inspection data including machine data and defect detection results, storing the inspection data in a database, modifying, via the database, at least one of a plurality of recipe files associated with the inspection based on the machine data, and modifying, via the database, at least one of a plurality of software parameters associated with the inspection based on the defect detection results. The system includes a memory including instructions executable by a processor to monitor an inspection of integrated circuits to receive and store inspection data including machine data and defect detection results in a database, modify, via the database, a recipe file associated with the inspection based on the machine data, and modify, via the database, a software parameter associated with the inspection based on the defect detection results.

Abstract: An inspection system includes a controller communicatively coupled to a physical inspection device (PID), a virtual inspection device (VID) configured to analyze stored PID data, and a defect verification device (DVD). The controller may receive a pattern layout of a sample including multiple patterns fabricated with selected lithography configurations defining a process window, receive locations of PID-identified defects identified through analysis of the sample with the PID, wherein the PID-identified defects are verified by the DVD, remove one or more lithography configurations associated with the locations of the PID-identified defects from the process window, iteratively refine the process window by removing one or more lithography configurations associated with VID-identified defects identified through analysis of selected portions of stored PID data with the VID, and provide, as an output, the process window when a selected end condition is met.

Abstract: There are provided a method of generating an inspection recipe usable for inspecting an inspection area of a specimen and a recipe generating unit. The recipe generating unit is configured: upon obtaining design data informative of design structural elements comprised in a design PoI corresponding to the at least one PoI, to provide global segmentation of a test image captured by an inspection tool unit from the inspection area and comprising at least one test PoI of substantially the same design as the at least one PoI, thereby to obtain segmented structural elements comprised in the test PoI and segmentation configuration data; to associate the segmented structural elements comprised in the test PoI with the design structural elements comprised in the design PoI, thereby to obtain design association data; and to generate an inspection recipe comprising, at least, segmentation configuration data and design association data.

Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: Generally, embodiments of the invention are directed to methods, computer readable medium, servers, and systems for deidentified access of data. The deidentified access is permitted with the use of an identifier that uniquely indicates an outcome, the coding of the identifier obscures unaided human interpretation of the outcome, and the identifier uniquely identifies data for remediating performance associated with future outcomes.

Abstract: Generally, embodiments of the invention are directed to methods, computer readable medium, servers, and systems for deidentified access of data. The deidentified access is permitted with the use of an identifier that uniquely indicates an outcome, the coding of the identifier obscures unaided human interpretation of the outcome, and the identifier uniquely identifies data for remediating performance associated with future outcomes.

Abstract: Techniques that facilitate time-driven placement and/or cloning of components for an integrated circuit are provided. In one example, a system includes an analysis component, a geometric area component and a placement component. The analysis component computes timing information and distance information between a set of transistor components of an integrated circuit. The geometric area component determines at least a first geometric area of the integrated circuit and a second geometric area of the integrated circuit based on the timing information and the distance information. The placement component determines a location for a latch component on the integrated circuit based on an intersection between the first geometric area and the second geometric area.

Abstract: A microscope has a light source for generating a light beam having a wavelength, ?, and beam-forming optics configured for receiving the light beam and generating a Bessel-like beam that is directed into a sample. The beam-forming optics include an excitation objective having an axis oriented in a first direction. Imaging optics are configured for receiving light from a position within the sample that is illuminated by the Bessel-like beam and for imaging the received light on a detector. The imaging optics include a detection objective having an axis oriented in a second direction that is non-parallel to the first direction. A detector is configured for detecting signal light received by the imaging optics, and an aperture mask is positioned.

Abstract: A CMP simulation method includes inputting a chip pattern layout including a plurality of graphic patterns, partitioning the chip pattern layout into targeting grids including a plurality of surrounding grids, and then calculating grid geometry characteristics of the targeting grids. The method also includes generating shifted grids by shifting the targeting grids, calculating weighted average grid geometry characteristics of the targeting grids and the shifted grids, and locating first hot spots on the chip pattern layout by performing a CMP simulation based on the grid geometry characteristics of the targeting grids. Further, the method includes generating optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots, and then locating second hot spots on the chip pattern layout by performing the CMP simulation based on the optimized grid geometry characteristics.

Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.

Abstract: The present disclosure provides compositions comprising 15-HEPE and methods of using same for treating and/or preventing fibrosis in a subject in need thereof.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.

Abstract: A mask optimization method for optimizing a target mask used for a partial coherent system including a plurality of spatial filters is provided. The mask optimization method includes obtaining a trainer mask that is an optimized sample mask by performing a mask optimization on a sample mask, generating a mask optimization estimation model by performing a pixel-based learning using, as a feature vector of each of pixels of the trainer mask, partial signals of each of the pixels of the trainer mask respectively determined based on the spatial filters and using, as a target value, a degree of overlap between each of the pixels and a mask polygon of the trainer mask, and performing a mask optimization on the target mask using the mask optimization estimation model.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: Methods and systems for defect prediction are provided. The method includes receiving feature data of an integrated circuit (IC) and process condition data of a production process associated with the IC, and determining a care area associated with the IC using the feature data, the process condition data, and a defect prediction technique, wherein the care area includes a potential defect and is inspected by a high-resolution inspection system. Based on the provided methods and systems, care areas can be generated incorporating actual process conditions when the inspected IC is being manufactured, and fast and high-resolution IC defect inspection systems can be implemented.

Abstract: A method for determining a registration error of a feature on a mask, including providing a first aerial image that was captured by means of a position measuring device and includes at least the feature, simulating, from pattern specifications of the mask, a second aerial image that includes at least the feature, taking into account at least one effect that causes distortion of the first aerial image, and determining the registration error of the feature as the distance of the position of the feature in the first aerial image from the position of the feature in the second aerial image. Also provided is a method for simulating an aerial image from pattern specifications of a mask and a position measuring device for carrying out the method.

Abstract: Disclosed are techniques for correcting the EUV crosstalk effects. Isolated mask feature component diffraction signals associated with individual layout feature components are determined based on a component-based mask diffraction modeling method such as a domain decomposition method. Mask feature component diffraction signals are then determined based on the isolated mask feature component diffraction signals, layout data and predetermined crosstalk signals. Here, the predetermined crosstalk signals are derived based on mask feature component diffraction signals computed using an electromagnetic field solver and the component-based mask diffraction modeling method, respectively. The mask feature component diffraction signals are then used to process layout designs.

Abstract: A method of making a photomask includes constructing a transmission cross coefficient (TCC) matrix representing an illumination source for supplying light to transmit through the photomask and a pupil for focusing the transmitted light onto a target substrate to produce a set of main features, generating kernels through decomposition of the TCC matrix, selecting ones of the kernels having odd symmetry, generating a field map kernel as a sum of self-convolutions of the odd symmetry kernels, generating a first field map by convolving an area of the photomask corresponding to the set of main features with the field map kernel, and making the photomask corresponding to the first field map. The method may include assigning first sub-resolution assist features (SRAFs) to those portions of the photomask area having corresponding said first field map values exceeding a nonnegative threshold, and making the photomask corresponding to the main features and first SRAFs.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one metal-short-related failure mode.

Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of V0 via opens.

Abstract: A microscope has a light source for generating a light beam having a wavelength, ?, and beam-forming optics configured for receiving the light beam and generating a Bessel-like beam that is directed into a sample. The beam-forming optics include an excitation objective having an axis oriented in a first direction. Imaging optics are configured for receiving light from a position within the sample that is illuminated by the Bessel-like beam and for imaging the received light on a detector. The imaging optics include a detection objective having an axis oriented in a second direction that is non-parallel to the first direction. A detector is configured for detecting signal light received by the imaging optics, and an aperture mask is positioned.

Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract: Performance metric based stopping criteria for iterative algorithm techniques are described. In one or more implementations, a training dataset is processed by one or more computing devices using an iterative algorithm having a cost function. The processing includes, for a plurality of iterations of the iterative algorithm, computing a cost for the iterative algorithm using the cost function and a value for each of a plurality of performance metrics that are usable to infer accuracy of the iterative algorithm for a respective one of the iterations. Responsive to the processing, a particular one of the plurality of iterations is identified as a stopping criterion based at least in part on the computed values for the plurality of performance metrics and the stopping criterion is output to configure the iterative algorithm to use the stopping criterion for subsequent processing of data by the iterative algorithm.

Abstract: According to one embodiment, in a mask data generation system, a first acquisition part is configured to acquire pattern contour data included in each of a plurality of layout candidate data for a first layer. A second acquisition part is configured to acquire pattern contour data included in layout data for a second layer. A superimposing part is configured to superimpose the contour data acquired by the first acquisition part and the contour data acquired by the second acquisition part with each other, for each of the plurality of layout candidate data. An area calculation part is configured to calculate an overlap area between a first pattern in the contour data acquired by the first acquisition part and a second pattern in the contour data acquired by the second acquisition part, based on the superimposed data, for each of the plurality of layout candidate data.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for DRC verification of a design layout file comprising off-grid patterns includes identifying an off-grid pattern having one or more off-grid sides, outwardly expanding the one or more off-grid sides to adjacent grids to obtain a first on-grid pattern, inwardly contracting the expanded one or more sides of the first on-grid pattern to adjacent grids to obtain a second on-grid pattern, and performing a DRC verification on the second on-grid pattern using an existing on-grid DRC deck. The method also includes making a backup copy of the design layout file prior to converting the identified off-grid pattern into an on-grid pattern.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one metal-short-related failure mode.

Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.

Abstract: A method designs a semiconductor device that includes first and second wirings provided in an uppermost of wiring layers, and a setting part coupled to the first and second wirings and including third and fourth wirings provided in each of the wiring layers, and vias that electrically connect wirings of different wiring layers, wherein each of the third and fourth wirings in each of the wiring layers extends in one of 2 mutually perpendicular directions, and the third and fourth wirings in the wiring layers are arranged and connected so as to turn around using the vias as turn-around points. The method modifies a direction in which the third and fourth wirings extend in one wiring layer specified by layer information, and modifying a connection of the first and second wirings with respect to the third and fourth wirings in a lowermost of the wiring layers.

Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: In Integrated Circuit (IC) Physical Design, the shapes and other geometric objects that are used to represent the mask data have physical coordinates expressed in a Cartesian plane. When the designs are hierarchical, each level of physical hierarchy has its own coordinate system. When viewed from the top level of a hierarchical design, lower-level shapes must be transformed in order to understand their location from the point of view of the top block. Users and algorithms that manipulate physical data across these hierarchy boundaries must go through the tedious task of transforming data, sometimes multiple times, as it is being changed.

Abstract: Disclosed are an exposure method and a method of manufacturing a mask and a semiconductor device using the same, which minimize time taken by mask data preparation (MDP) to optimize a total exposure process and enhance a quality of a pattern by using an inverse solution concept, based on a multi-beam mask writer. The exposure method includes receiving mask tape output (MTO) design data obtained through optical proximity correction (OPC), preparing mask data, including a job deck, for the MTO design data without a data format conversion, performing complex correction, including proximity effect correction (PEC) of an error caused by an e-beam proximity effect and mask process correction (MPC) of an error caused by an exposure process, on the mask data, generating pixel data, based on data for which the complex correction is performed, and performing e-beam writing on a substrate for a mask, based on the pixel data.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

Abstract: The invention relates to a method for locally deforming an optical element for photolithography in accordance with a predefined deformation form comprising: (a) generating at least one laser pulse having at least one laser beam parameter; and (b) directing the at least one laser pulse onto the optical element, wherein the at least one laser beam parameter of the laser pulse is selected to yield the predefined deformation form.

Abstract: A method for detecting photolithographic hotspots is disclosed. After receiving layout data, an aerial image simulation is conducted to extract aerial image intensity indices. Based on the combination of one or more aerial image intensity indices, various aerial image detectors are generated. The value of aerial image detectors is verified to determine the position and type of the photolithographic hotspots.

Abstract: The invention discloses a method for measuring positions of structures on a mask and thereby determining mask manufacturing errors. It is shown, that from a plurality measurement sites an influence of an optical proximity effect on a position measurement of structures on the mask, is determined with a metrology tool. A rendered image of the data representation of the structures is obtained. Additionally, at least one optical image of the pattern within the area on the mask is captured with the imaging system of the metrology tool. The field of view of the metrology tool is approximately identical to the size of the selected area of the mask design data. Finally, a residual is determined, which shows the manufacturing based proximity effect.

Abstract: A method of efficient simulating imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes the steps of determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and generating the simulated image utilizing the function, where the simulated image represents the imaging result of the target design for the lithographic process.

Abstract: According to a method of preparing a layout of semiconductor circuit elements, a computer processor determines a first value of a distance metric that describes a separation between at least one well of a first type and at least one well of a second type in a first layout of a circuit design represented in a memory coupled to the computer processor. The at least one well of the first type and the at least one well of the second type are rearranged into a second layout. The method determines a second value of the distance metric that describes separation between the at least one well of the first type and the at least one well of the second type in the second layout. The second layout is stored in response to the second value of the distance metric being greater than the first value of the distance metric.

Abstract: A method for generating a pattern of a mask includes obtaining data of a plurality of polygons representing a plurality of pattern elements, grouping polygons which overlap or contact with each other among the plural polygons in one group, not setting an evaluation position for evaluating an image of a pattern of the one group on a line segment of sides which overlap or contact with each other among sides of the polygon of the one group, and setting an evaluation position at a portion except for the line segment, and repeating calculating the image of the pattern of the one group, evaluating the calculated image at the set evaluation position, and correcting the pattern based on a result of the evaluating, and generating the pattern of the mask based on a result of the repeating step.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.

Abstract: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether ?1<?1, wherein ?1 represents model vs. exposure difference and ?1 represents predetermined criteria. The technique further includes completing the model when ?1<?1.

Abstract: A method, apparatus and program product automatically generate a grayscale lithography mask file (76) from a three dimensional (3D) model (72) of a desired topography, e.g., as generated by a three dimensional computer aided design (CAD) tool (70).