Abstract: A method for resizing a pattern to be written by using lithography technique includes calculating a first dimension correction amount of a pattern for correcting a dimension error caused by a loading effect, for each small region made by virtually dividing a writing region of a target workpiece into meshes of a predetermined size, based on an area density of the each small region, calculating a second dimension correction amount in accordance with a line width dimension of the pattern to be written in the each small region, correcting the first dimension correction amount by using the second dimension correction amount, and resizing the line width dimension of the pattern by using a corrected first dimension correction amount, and outputting a result of the resizing.

Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.

Abstract: A method of forming a photomask includes providing a layout of design patterns, setting an optical proximity correction (OPC) with respect to the layout of design patterns, and forming a layout of correction patterns with respect to the layout of design patterns by using the set OPC. The method also includes collecting verification data about the layout of correction patterns by using a layout of contour patterns based on the layout of correction patterns, and verifying whether the layout of design patterns and the layout of correction patterns are substantially identical to each other by using the verification data.

Abstract: An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask.

Abstract: Data including information related to each area with a graphic disposed therein is inputted to the writing apparatus. The area is delimited with meshes each having a predetermined size. Next, an area value of a graphic lying within each of the meshes and its center-of-gravity position are determined. For every mesh, a check is made whether the area value is less than or equal to a predetermined value. When the area value is less than or equal to the predetermined value, a range allowable for an x coordinate of the center-of-gravity position is determined and a check is made whether an actual x coordinate falls within this range. Next, a range allowable for a y coordinate of the center-of-gravity position is determined and a check is made whether an actual y coordinate falls within this range.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: In one embodiment, a photomask designing method for creating a pattern layout having an assist pattern placed around a design pattern is disclosed. The method can place a plurality of evaluation points around the design pattern and set an evaluation index for imaging properties of the design pattern on an imaging surface. The method can combine a light intensity distribution of the design pattern with light intensity distributions of the evaluation points to obtain a light intensity distribution on the imaging surface and evaluate the light intensity distribution on the imaging surface using the evaluation index to determine a region having an effective evaluation point placed. In addition, the method can determine a placement condition for the assist pattern based on the region where the effective evaluation point is placed and place the assist pattern around the design pattern based on the placement condition to create the pattern layout.

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract: A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative.

Abstract: A solution for improving photomask fabrication time and yield, through the reduction in the number of exposure shots used for a given photomask pattern to be written on the photomask. In one embodiment, non-critical elements can be configured into a shape that the write tool can write with less exposure shots, while maintaining the original intent of the non-critical element. In another embodiment, the pattern of non-critical elements can be configured such that the non-critical elements are aligned with the grid lines of the operational grid of the write tool to further reduce shot count. In another embodiment, the manufacturing parameters and placement of non-critical elements can be modifying, e.g., by identifying which elements are critical and which are non-critical, and then printing non-critical elements with a first exposure parameter (e.g. a single pass exposure) while critical elements are printed with a second exposure parameter (e.g., a multi pass exposure).

Abstract: A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.

Abstract: One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections.

Abstract: A method of manufacture of a mask system includes: providing design data; generating a substantially circular optical proximity correction target from the design data; biasing a segment of the substantially circular optical proximity correction target; and generating mask data based on the shape produced by biasing the segment of the substantially circular optical proximity correction target.

Abstract: Disclosed are techniques for simulating and correcting the mask shadowing effect using the domain decomposition method (DDM). According to various implementations of the invention, DDM signals for an extreme ultraviolet (EUV) lithography mask are determined for a plurality of azimuthal angles of illumination. Base on the DDM signals, one or more layout designs for making the mask may be analyzed and/or modified.

Abstract: A method for improving an optical proximity simulation is disclosed. First, multiple exposure data are determined. An original simulation result corresponding to the exposure result and generated from multiple original simulation parameters is provided. Then, an original deviation value from the original simulation result and the exposure result is verified to determine whether it is within a predetermined range. Next, the original simulation parameters are adjusted to obtain adjusted simulation parameters. The adjusted simulation parameters whose adjusted deviation value is within the predetermined range are collected to obtain an optical proximity correction model for outputting a pattern on a reticle.

Abstract: A character projection charged particle beam writer system is disclosed comprising a variable magnification reduction lens which will allow different shot magnifications on a shot by shot basis. A method for fracturing or mask data preparation or optical proximity correction is also disclosed comprising assigning a magnification to each calculated charged particle beam writer shot. A method for forming a pattern on a surface is also disclosed comprising using a charged particle beam writer system and varying the magnification from shot to shot. A method for manufacturing an integrated circuit using optical lithography is also disclosed, comprising using a charged particle beam writer system to form a pattern on a reticle, and varying the magnification of the charged particle beam writer system from shot to shot.

Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

Abstract: A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques.

Abstract: Aspects of the invention relate to machine-learning-based hotspot detection techniques. These hotspot detection techniques employ machine learning models constructed using two feature encoding schemes. When two-level machine learning methods are also employed, a total four machine learning models are constructed: scheme-one level-one, scheme-one level-two, scheme-two level-one and scheme-two level-two. The four models are applied to test patterns to derive scheme-one hotspot information and scheme-two hotspot information, which are then used to determine final hotspot information.

Abstract: The present invention relates to the field of semiconductor manufacturing, and particularly to a method of making Optical Proximity Correction to an original gate photomask pattern based on different substrate areas. The present invention discloses a method of making OPC to an original gate photomask pattern based on different substrate areas, which makes correction to gate photomask pattern dimension on the AA and to gate photomask pattern dimension on the STI respectively by creating two different optical proximity effect models of the gate, so as to control the finally imaged gate photomask pattern dimensions more accurately; moreover, the error of the correction result of the gate spacing dimension on the STI can be reduced by 4% by separating the patterns and using the gate model based on the STI, so as to avoid the spacing dimension error when the photolithography exposure conditions vary.

Abstract: An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S50). Next, a relative distance between the first pattern and the second pattern after the overlapping margin is corrected is calculated (S60). Next, it is determined whether or not the relative distance satisfies a criterion (S70). Thus, the pattern can be verified under the consideration of the overlapping margin.

Abstract: A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.

Abstract: A method of manufacturing a semiconductor device includes dividing a design pattern layout into a repetitive pattern part and a non-repetitive pattern part, obtaining an optical proximity correction (OPC) bias from an extracted portion, the extracted portion being a partial portion of the repetitive pattern part, applying the OPC bias obtained from the extracted portion equally to the extracted portion and other portions of the repetitive pattern part so as to form a first corrected layout in which corrected layouts of the other portions are the same as that of the extracted portion, and forming a photomask in all portions of the repetitive pattern part according to the first corrected layout.

Abstract: A method for decomposing a target circuit pattern containing features to be imaged into multiple patterns. The process includes the steps of separating the features to be printed into a first pattern and a second pattern; performing a first optical proximity correction process on the first pattern and the second pattern; determining an imaging performance of the first pattern and the second pattern; determining a first error between the first pattern and the imaging performance of the first pattern, and a second error between the second pattern and the imaging performance of said second pattern; utilizing the first error to adjust the first pattern to generate a modified first pattern; utilizing the second error to adjust the second pattern to generate a modified second pattern; and applying a second optical proximity correction process to the modified first pattern and the modified second pattern.

Abstract: The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour.

Abstract: According to a simulation model creating method of an embodiment, a resist pattern is formed by transferring a mask pattern on a first substrate with an exposing amount and a focus value being changed, and a line width of the resist pattern is measured. Next, measurement results which are not within an allowable change range due to an irregularity of the exposing amount, an irregularity of the focus value or pattern feature amount are removed. In addition, measurement results which are not with in an allowable change range due to an irregularity of the line width of the mask pattern are removed. Next, a simulation model is created by using measurement results which are not removed.

Abstract: A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions.

Abstract: A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Abstract: Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, the method comprising: calculating a forward propagating electric field or forward propagating magnetic field resultant from the incident radiation at a depth in the resist layer; calculating a backward propagating electric field or backward propagating magnetic field resultant from the incident radiation at the depth in the resist layer; calculating a radiation field at the depth in the resist layer from the forward propagating electric field or forward propagating magnetic field and from the backward propagating electric field or backward propagating magnetic field while ignoring an interference between the forward propagating electric field or forward propagating magnetic field and the backward propagating electric field or backward propagating magnetic field.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.

Abstract: Aspects of the invention include a computer-implemented method of designing a photomask. In one embodiment, the method comprises: simulating a first photomask patterning process using a first photomask design to create simulated contours; comparing the simulated contours to a desired design; identifying regions not common to the simulated contours and the desired design; creating desired target shapes for a second photomask patterning process subsequent to the first photomask patterning process based upon the identified regions; and providing the desired target shapes for forming of a second photomask design based upon the desired target shapes.

Abstract: A two-dimensional transmission cross coefficient is obtained based on a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of the projection optical system and a pupil function of the projection optical system. Based on the two-dimensional transmission cross coefficient and data of a pattern on an object plane of the projection optical system, an approximate aerial image is calculated by using at least one of plural components of an aerial image on an image plane of the projection optical system. Data of a pattern of an original is produced based on the approximate aerial image.

Abstract: A method of performing an optical proximity effect correction to a first photomask pattern for a wiring of a semiconductor device for use in combination with a second photomask pattern for a via, the wiring including an end portion coupled to the via, the method being performed by a computer including a memory storing layout data of the first photomask pattern and the second photomask pattern, including extracting a pattern of layout data of the first photomask pattern for the wiring corresponding to the end portion of the wiring and layout data of the second photomask pattern for the via.

Abstract: An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask.

Abstract: A mechanism is provided for resolving patterning conflicts. The mechanism performs decomposition with stitches at all candidate locations to find the solution with the minimum number of conflicts. The mechanism then defines interactions between a layout of a first mask and a layout of a second mask through design rules, as well as interactions of mask1/mask2 with top and bottom layers (i.e., contacts, vial, etc.). The mechanism then gives the decomposed layout and design rule definition to any existing design rule fixing or layout compaction tool to solve native conflicts. The modified design rules are that same-layer spacing equals spacing of single patterning, different-layer spacing equals spacing of final layout, and layer overlap equals minimum overlap length.

Abstract: A stencil for character projection (CP) charged particle beam lithography and a method for manufacturing the stencil is disclosed, where the stencil contains two circular characters, where each character is capable of forming patterns on a surface in a range of sizes by using different dosages, and where the size ranges for the two characters is continuous. A method for forming circular patterns on a surface using variable-shaped beam (VSB) shots of different dosages is also disclosed. A method for forming circular patterns on a surface using a set of shots, where all of the shots comprise dosages, is also disclosed.

Abstract: One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent on the local pattern density. In some embodiments, the mask error modeling term can include an edge bias term and a corner rounding term. The edge bias term can be based on the sensitivity of the aerial image intensity to an edge bias, and the corner rounding term can be based on the sensitivity of the aerial image intensity to a corner rounding adjustment.

Abstract: The Hessian (second derivative) of the image log slope (ILS) can be quickly and accurately calculated without the need to use approximate methods from the gradient of the ILS with respect to mask transmission and source intensity. The Hessian has been traditionally calculated using a finite-difference approach. Calculating the Hessian through a finite-difference approach is slow and is an approximate method. The gradient of the ILS improves the speed of calculation of the Hessian, and thus accelerated SMO operation is realized. The results of ILS evaluation can be used in design for manufacturing (DFM) to suggest changes in the design rules to improve imaging. For a fixed illumination, this information can help remove forbidden pitches and help select design rules for 1-D and 2-D patterns on a mask design layout.

Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: A beam dose computing method includes dividing a surface area of a target object into include first, second and third regions of different sizes, the third regions being less in size than the first and second regions, determining first corrected doses of a charged particle beam for correcting fogging effects in the first regions, determining corrected size values for correcting pattern line width deviations occurring due to loading effects in the second regions to create a map of base doses of the beam in respective of said second regions and to prepare a map of proximity effect correction coefficients in respective of said second regions, using the maps to determine second corrected doses of the beam for proximity effect correction in the third regions, and using the first and second corrected doses to determine an actual beam dose at each position on the surface of said object.

Abstract: A method for the reproducible determination of the positions of structures (3) on a mask (2) is disclosed. A pellicle frame (30) is firmly attached to the mask (2). A theoretical model of the bending of the mask (2) with the firmly attached pellicle frame (30) is calculated, wherein material properties of the mask (2), of the pellicle frame (30), and of the attaching means between the pellicle frame (30) and the mask (2) are taken into account in the calculation of the bending of the mask (2). For the calculation of the bending of the mask (2) its contact with three support points is considered. The positions of the structures (3) on the mask (2) are measured with a metrology tool (1). The measured positions of each structure are corrected with the theoretical model of the bending of the mask at the position of the respectively measured structure.

Abstract: Layout design data are decomposed for double dipole lithography based on partial intensity distribution information. The partial intensity distribution information is generated by performing optical simulations on the layout design data. The layout decomposition may further be adjusted during an optical proximity correction process. The adjustment may utilize the partial intensity distribution information.

Abstract: The present invention provides a generation method that obtains a position at which an auxiliary pattern is to be placed and generates a mask pattern (its data), which achieves excellent imaging performance, even when a halftone mask is used as an original.

Abstract: Various embodiments of the present invention relate to particle beam writing to fabricate an integrated circuit on a wafer. In various embodiments, cell projection (CP) cell library information is stored in the form of a data structure. Subsequently, the CP cell library information is referenced by a writing system. The patterns are written on the wafer depending on the referenced CP cell library.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. In some embodiments, characteristics of the continuous track will be within a predetermined tolerance.

Abstract: A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.

Abstract: A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.