Abstract: A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.

Abstract: Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.

Abstract: A method of splitting a lithographic pattern into two sub-patterns, includes generating test structures corresponding to structures of interest in the lithographic pattern, varying the test structures through a selected range of dimensions, simulating an image of the test structures, determining an image quality metric for the simulated image, analyzing the determined image quality metric to determine pitch ranges for which split improves the image quality metric and ranges for which split does not improve the image quality metric, and generating the two sub-patterns in accordance with the determined pitch ranges.

Abstract: A block management method for OPC model calibration includes calculating differences in several different optical functions between first patterns of a first mask and patterns of a second mask corresponding to the first patterns but differing therefrom by a predetermined bias, selecting one or more of the optical functions based on the calculated differences, clustering data of variations in the values of the calculated differences in the selected ones of the optical functions, selecting respective ones of the first patterns in consideration of how the data clusters, and designating the selected first patterns as test patterns.

Abstract: A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Abstract: A method for controlling uniformity of patterns formed in a semiconductor device includes obtaining simulation contours with respect to respective cases while controlling a size of an outermost pattern and determining a size of the outermost pattern in which uniform distribution values (3?) value of patterns included in the simulation contours satisfying specific conditions as a size of target outermost pattern.

Abstract: At least one pattern of a photomask is identified that has a likelihood of causing collapse of a microelectronic device feature that is formed using the photomask, due to surface tension of a solution that is applied to the feature during manufacture of the microelectronic device. The patterns of the photomask are then modified to reduce the likelihood of the collapse. The photomask may be formed and the photomask may be used to manufacture microelectronic devices. Related methods, systems, devices and computer program products are described.

Abstract: The manufacturing of integrated circuits relies on the use of lithography simulation to predict the image of the mask created on the wafer. Such predictions can be used for example to assess the quality of the images, verify the manufacturability of such images, perform using OPC necessary correction of the mask data to achieve images close to the targets, optimize the printing parameters such as the illumination source, or globally optimize the source and the mask to achieve better printability. This disclosure provides a technique based on the association of at least one kernel function per source region or source point. Each kernel function can be directly convoluted with a mask image to create a prediction of the wafer image. As the kernel functions are associated with the source, the source can be easily changed to create new models. The optical system can be fully described by computing the possible kernels for all possible source points and all possible numerical apertures.

Abstract: A method and system for fracturing or mask data preparation for charged particle beam lithography are disclosed in which accuracy and/or edge slope of a pattern formed on a surface by a set of charged particle beam shots is enhanced by use of partially-overlapping shots. In some embodiments, dosages of the shots may vary with respect to each other before proximity effect correction. Particle beam simulation may be used to calculate the pattern and the edge slope. Enhanced edge slope can improve critical dimension (CD) variation and line-edge roughness (LER) of the pattern produced on the surface.

Abstract: A method for automatically generating and prioritizing several design solutions that resolve a double patterning (DP) loop violation in an IC design layout. The method of some embodiments receives a DP loop violation marker and identifies pairs of edges of shapes that form a double patterning loop based on the DP loop violation marker. For each pair of edges that violates the design rule, the method generates one or more design solutions. Each design solution moves a single edge or both edges to resolve the violation. The method of some embodiments computes the cost of applying each design solution to the IC design layout and prioritizes the generated solutions for all the identified pairs of edges based on the computed cost for each solution. The method in some embodiments then selects a solution from the prioritized solutions and applies the selected solution to the design layout.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.

Abstract: The present disclosure describes a method of forming a pattern by an electron beam lithography system. The method includes receiving an integrated circuit (IC) design layout data having a polygon and a forbidden pattern, modifying the polygon and the forbidden pattern using an electron proximity correction (EPC) technique, stripping the modified polygon into subfields, converting the stripped polygon to an electron beam writer format data, and writing the electron beam writer formatted polygon onto a substrate by an electron beam writer. Stripping the modified polygon includes finding the modified forbidden pattern as a reference layer, and stitching the modified polygon to avoid stitching the modified forbidden pattern.

Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.

Abstract: Systems and methods for process aware metrology are provided.

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

Abstract: Methods for approximating simulated contours are provided herein. With some implementations, a function that incorporates a Gaussian proximity kernel to approximate the electron beam exposure effects is used to simulate a printed image. Subsequently, one or more corners of the simulated printed image may be approximated by two or more straight edges. In various implementations, the number of straight edges used to approximate the corner as well as the orientation of the one or more straight edges is determined based upon the characteristics of the corner, such as, the corner having an obtuse angle larger than 135 degrees for example. With various implementations, two straight edges are used to approximate the corner, the orientation of the two straight edges being determined by a first point, a second point, and a shared corner point.

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract: A method of manufacturing semiconductor devices is disclosed. The method includes determining fractured shots that do not overlap each other based on a final pattern; determining overlapping shots that are shots that overlap each other based on the final pattern; generating area difference data by comparing the areas of the overlapping shots and the fractured shots with each other; calculating a radiation influenced pattern based on the area difference data; and correcting the overlapping shots based on the radiation influenced pattern.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.

Abstract: Optical wave data for a semiconductor device design is divided into regions. First wavefront engineering is performed on the wave data of each region, accounting for just the wave data of each region and not accounting for the wave data of neighboring regions of each region. The optical wave data of each region is normalized based on results of the first wavefront engineering. Second wavefront engineering is performed on the wave data of each region, based at least on the wave data of each region as has been normalized. The second wavefront engineering takes into account the wave data of each region and a guard band around each region that includes the wave data of the neighboring regions of each region. The second wavefront engineering can be sequentially performed by organizing the regions into groups, and sequentially performing the second wavefront engineering on the regions of each group in parallel.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: Roughly described, a design rule data set includes rules on derived layers. The rules are checked by traversing the corners of physical shapes, and for each corner, populating a layout topology database with values gleaned from that corner location, including values involving derived layers. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations, including violations of design rules defined on derived layers. Violations are reported in real time during manual editing of the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, scanning in the direction of the edge orientations. Scans stop only at corner positions on physical layers, and populate the layout topology database with what information can be gleaned based on the current scan line, including information about derived layers. The scans need not reach corners simultaneously.

Abstract: A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.

Abstract: The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.

Abstract: A method, system, and computer usable program product for fracturing a continuous mask usable in photolithography are provided in the illustrative embodiments. A first origin point is selected from a set of points on an edge in the continuous mask. A first end point is identified on the edge such that a separation metric between the first origin point and the first end point is at least equal to a threshold value. Several alternatives are determined for fracturing using the first origin point and the first end point. A cost associated with each of the several alternatives is computed and one of the alternatives is selected as a preferred fracturing. Several pairs of origin points and end points are formed from the set of points. Each pair has a cost of a preferred fracturing between the pair. The continuous mask is fractured using a subset of the several pairs.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.

Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.

Abstract: A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.

Abstract: Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes generating, using the flare map generator, a low frequency flare map for the mask from the low frequency component by using fast Fourier transform (FFT).

Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.

Abstract: A method for optical proximity correction (OPC) model accuracy verification for a semiconductor product includes generating a multifeature test pattern, the multifeature test pattern comprising a plurality of features selected from the semiconductor product; exposing and printing the multifeature test pattern on a test wafer under a process condition; generating an OPC model of the semiconductor product for the process condition; and comparing the test wafer to the OPC model to verify the accuracy of the OPC model.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.

Abstract: The present disclosure involves a method. The method includes decomposing a layout of a circuit into a plurality of patterns. The method includes generating a plurality of contours to represent the plurality of patterns after the patterns have been subjected to a manufacturing process. The method includes generating a plurality of polygons that approximate geometries of the contours, respectively. The method includes associating each of the polygons with a respective one of a plurality of pattern elements in a pattern library, wherein the pattern elements each include a shape that resembles the associated polygon and electrical parameters extracted from the shape. The method includes calculating electrical performance of the circuit based on the pattern elements associated with the polygons.

Abstract: A system and methods are provide for modeling the behavior of a lithographic scanner and, more particularly, a system and methods are provide using thresholds of an image profile to characterize through-pitch printing behavior of a lithographic scanner. The method includes running a lithographic model for a target tool and running a lithographic model on the matching tool for a plurality of different settings using lens numerical aperture, numerical aperture of the illuminator and annular ratio of a pattern which is produced by an illuminator. The method then selects the setting that most closely matches the output of the target tool.

Abstract: Obtaining a function by convoluting a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of a projection optical system and a pupil function of the projection optical system. Calculating a Fourier transformed function by Fourier transforming the product of the obtained function and a diffracted light distribution from a pattern on an object plane of the projection optical system. Producing data of the pattern of the mask based on the Fourier transformed function.

Abstract: The present disclosure provides a method and system for modifying a doped region design layout during mask preparation to tune device performance. An exemplary method includes receiving an integrated circuit design layout designed to define an integrated circuit, wherein the integrated circuit design layout includes a doped feature layout; identifying an area of the integrated circuit for device performance modification, and modifying a portion of the doped feature layout that corresponds with the identified area of the integrated circuit during a mask preparation process, thereby providing a modified doped feature layout.

Abstract: A charged particle beam writer system is disclosed comprising a generator for a charged particle beam having a beam blur radius, wherein the beam blur radius may be varied from shot to shot, or between two or more groups of shots. A method for fracturing or mask data preparation or optical proximity correction is also disclosed comprising assigning a beam blur radius variation to each calculated charged particle beam writer shot. A method for forming a pattern on a surface is also disclosed comprising using a charged particle beam writer system and varying the beam blur radius from shot to shot. A method for manufacturing an integrated circuit using optical lithography is also disclosed, comprising using a charged particle beam writer system to form a pattern on a reticle, and varying the beam blur radius of the charged particle beam writer system from shot to shot.

Abstract: In the field of semiconductor device production, a method for manufacturing a surface using two-dimensional dosage maps is disclosed. A set of charged particle beam shots for creating an image on the surface is determined by combining dosage information such as dosage maps for a plurality of shots into the dosage map for the surface. A similar method is disclosed for fracturing or mask data preparation of a reticle image.

Abstract: Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract: A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference in shape between an electron beam exposure pattern formed on a substrate through electron beam exposure on the basis of the electron beam exposure data and a photoexposure pattern formed on the substrate through photoexposure on the basis of the design data of the semiconductor device; determining whether the size of the difference in shape between the electron beam exposure pattern and the photoexposure pattern falls within a predetermined reference value; acquiring shape changed exposure data by changing the shape of the pattern of the electron beam exposure data in accordance with the differential information and updating the electron beam exposure data; and repeating the differential extraction, the determination and the updating when the size of the difference falls outside the predetermined reference value.

Abstract: A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulation of the mask layout, and fed back to correct the designed pattern layout. As a result, problems can be detected in each process and corrected to reduce the process time.

Abstract: A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.

Abstract: Provided is an etch proximity correction method in which an accurate etch bias value is calculated. The etch proximity correction method includes creating an etch bias value from a project area corresponding to an area blocked by a pattern region within a linear distance projected from a target position selected in a target layout to an outermost portion of the proximity region and a non-project area corresponding to an area projected into an edge linear distance from an edge of the pattern region blocked in the linear distance to the outermost portion of the proximity region and correcting the target position in the layout using the etch bias value. Since an etch bias model includes the project area and the non-project area, the accurate etch bias value may be calculated.

Abstract: Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.