Abstract: A weak point detecting method of the present invention designs a target layout, and compensates an optical proximity effect for the target layout, thereafter, verifies the target layout in which the optical proximity effect is compensated by using an NILS of the target layout, thereby, enabling to reduce the time and cost in detecting a weak point for a full chip regardless of the size and form of a pattern.

Abstract: Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

Abstract: A method for optical proximity correction (OPC) model accuracy verification for a semiconductor product includes generating a multifeature test pattern, the multifeature test pattern comprising a plurality of features selected from the semiconductor product; exposing and printing the multifeature test pattern on a test wafer under a process condition; generating an OPC model of the semiconductor product for the process condition; and comparing the test wafer to the OPC model to verify the accuracy of the OPC model.

Abstract: A pattern forming method including modifying design data subjected to a first design rule check in design data of a pattern to be formed in a semiconductor substrate, performing the first design rule check to the modified design data again, outputting the modified design data which does not violate the first design rule as pattern forming design data used in actual pattern formation, and performing a second design rule check having an allowable range wider than that of the first design rule to the modified design data which violates the first design rule, and outputting the modified design data which does not violate the second design rule as the pattern forming design data, and redesigning the pattern to satisfy the second design rule or adjusting the modification guideline such that the modified design data which violates the second design rule satisfies the second design rule.

Abstract: A technique for identifying a defect in an object produced by a controllable process. A first type of data generated as a result of production of the object by the controllable process is obtained. A second type of data generated as a result of production of the object by the controllable process is obtained. The first type of data and the second type of data are jointly analyzed. A defect is identified in the object based on the joint analysis of the first type of data and the second type of data. By way of example, the controllable process comprises a semiconductor manufacturing process such as a silicon wafer manufacturing process and the object produced by the semiconductor manufacturing process comprises a processed wafer. The first type of data comprises tool trace data and the second type of data comprises wafer image data. The tool trace data is generated by a photolithographic tool.

Abstract: A method and system for fracturing or mask data preparation are presented in which overlapping shots are generated to increase dosage in selected portions of a pattern, thus improving the fidelity and/or the critical dimension variation of the transferred pattern. In various embodiments, the improvements may affect the ends of paths or lines, or square or nearly-square patterns. Simulation is used to determine the pattern that will be produced on the surface.

Abstract: A method for compensating proximity effects of particle beam lithography processes is provided. The method includes the following steps. A control pattern is provided. A dissection process is provided. A set of control points are provided. The control pattern is defined as an input pattern of a lithography process. A target pattern is provided. A set of target points are produced. A set of target measurement values are provided. An actual pattern is defined. A set of actual measurement values are provided. A set of comparison values are calculated. An adjusting strategy is provided. A corrected pattern is produced. The corrected pattern is defined as an updated input of the lithography process.

Abstract: A method and system for fracturing or mask data preparation are presented in which overlapping shots are generated to increase dosage in selected portions of a pattern, thus improving the fidelity and/or the critical dimension variation of the transferred pattern. In various embodiments, the improvements may affect the ends of paths or lines, or square or nearly-square patterns. Simulation is used to determine the pattern that will be produced on the surface.

Abstract: A method of forming a layout of a photomask using optical proximity correction (OPC) includes: receiving a layout of a mask pattern; obtaining image parameters of a two-dimensional (2D) layout mask from a simulation; obtaining image parameters of a three-dimensional (3D) layout mask from a simulation; obtaining differences between the image parameters of the 2D and 3D masks; and performing optical proximity correction (OPC) on the 2D mask to compensate for the differences between the image parameters of the 2D and 3D masks by using a visible kernel with respect to the 2D mask.

Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at the center position of a corresponding one of the crystal-grain-defining areas, and wirings which interconnect the thin-film transistors.

Abstract: A system and method are provided for securely manufacturing a device at a foundry. For example, an integrated circuit chip may be securely fabricated at an untrusted foundry by later verifying authenticity of the integrated circuit chip based on a valid usage of an original source code file associated with a semiconductor manufacturing process of the integrated circuit chip. The integrated circuit chip may be authenticated by matching a first set of unique daughter codes generated during fabrication with a second set of unique daughter codes generated independently by some entity other than the foundry. In this way, a trusted electronics integrator may compare the first and second unique daughter codes to nondestructively determine whether the integrated circuit chip is a trusted device or a tampered device.

Abstract: A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.

Abstract: A semiconductor device fabrication method is disclosed. The method includes obtaining an inverse layout of an original circuit layout, reducing the inverse layout in size, thereby obtaining a reduced layout, obtaining a dummy pattern layout having an outline identical to an outline of the reduced layout and a given line width such that the dummy pattern layout is self-assembled to the circuit layout, and transferring the self-aligned or self-assembled dummy pattern layout and circuit layout to a semiconductor substrate.

Abstract: A method for designing a two-dimensional array overlay target set comprises the steps of: selecting a plurality of two-dimensional array overlay target sets having different overlay errors; calculating a deviation of a simulated diffraction spectra for each two-dimensional array overlay target set; selecting a sensitive overlay target set by taking the deviations of the simulated diffraction spectra into consideration; and designing a two-dimensional array overlay target set based on the structural parameters of the sensitive overlay target set.

Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: A method of generating reticle data for producing a reticle, a pattern of the reticle including a main pattern, a first auxiliary pattern, and a second auxiliary pattern, the first auxiliary pattern and the second auxiliary pattern being patterns not to resolve, light having passed through the first auxiliary pattern and light having passed through the main pattern being in phase, and light having passed through the second auxiliary pattern and light having passed through the main pattern having a phase difference of 180° from each other, the method comprising the step of deleting either of the first auxiliary pattern and the second auxiliary pattern or deforming at least either of the first auxiliary pattern and the second auxiliary pattern when the first auxiliary pattern and the second auxiliary pattern overlap each other.

Abstract: Disclosed herein are correcting methods and devices for lithography hotspots of the post-routing layout, used for correcting lithography hotspots detected in the post-routing layout. At least one two-dimensional pattern of changeable size or position of the number of hotspots in the local area is selected and adjusted, so that the simulation value of the aerial image intensity of various local areas is optimized. The simulation value of the aerial image intensity is derived through calculation with respect to a set of optical simulation model cells that can be determined by the numerical value of distribution of the aerial image intensity of a number of basic two-dimensional patterns. After adjustment, the aerial image intensity of the local area can be calculated with respect to a set of optical simulation model cells, and a number of cells in the simulation model cells are selected to synthesize the two-dimensional pattern after the change.

Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manufacturability of a layout. Layouts are created for the set of layout nanopatterns such that the created layouts cover the design space. The layouts for the set of layout nanopatterns are then optimized for manufacturability. A point in the design space is selected where the set of layout nanopatterns are co-optimized for manufacturability. A circuit layout is created based on the selected point in design space using the corresponding set of co-optimized layout nanopatterns. The optimized layouts for the set of layout nanopatterns and the associated circuit layout can be recorded in a digital format on a computer readable storage medium.

Abstract: A method for generating a write pattern to be used in a maskless-lithography process is described. During the method, a computer system determines a one-to-one correspondence between pixels in the write pattern and at least a subset of elements in a spatial-light modulator used in the maskless-lithography process. Furthermore, the computer system generates the write pattern. Note that the write pattern includes features corresponding to at least the subset of elements in the spatial-light modulator, and the generating is in accordance with a characteristic dimension of an element in the spatial-light modulator and a target pattern that is to be printed on a semiconductor wafer during the maskless-lithography process.

Abstract: A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography.

Abstract: Methods of fabricating a photo mask are provided. The method includes collecting sample data, setting a preliminary mask layout, performing an optical proximity correction using the sample data and a preliminary mask layout to obtain an optimized preliminary mask layout, verifying the optimized preliminary mask layout to obtain a final mask layout, and fabricating the photo mask using the final mask layout. Verification of the optimized preliminary mask layout includes operating a verification simulator using the sample data and the optimized preliminary mask layout as input data to obtain verification image data. The verification image data includes a plurality of contours of a pattern at different vertical positions.

Abstract: A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

Abstract: In a flare value calculation method according to an embodiment, an average optical intensity is calculated for each of mask patterns in a case where an exposure process is performed on a substrate using the mask patterns. Then, pattern correction amounts for the mask patterns corresponding to the average optical intensity and information about the dimensions of the mask patterns are calculated for each mask pattern. Then, post-correction mask patterns are prepared by performing pattern correction on each of the mask patterns using the pattern correction amount. Then, a flare value of an optical system of an exposure apparatus is calculated using a pattern average density of the post-correction mask patterns.

Abstract: Improving circuit design robustness is based on identifying process sensitive and design critical devices. Design critical devices are identified using circuit design information. Various model-based simulations may be performed on the layout areas associated with the identified design critical devices to extract process sensitive and design critical devices. To make the circuit design more robust, various techniques may be employed to treat the extracted process sensitive and design critical devices.

Abstract: A computer readable storage medium stores a program for generating reticle data for producing a reticle used in an exposure apparatus, the program including the steps of classifying target patterns to be formed on a substrate into a plurality of direction groups, extracting, for each of the plurality of direction groups, a region suited to resolution of a target pattern belonging to the direction group from an effective light source distribution formed on a pupil of a projection optical system by an illumination optical system, thereby determining the extracted region as a partial light source, executing, for each of a plurality of partial light sources determined in the step of extracting a region, processing of determining a pattern to be placed on a reticle when each partial light source is used as an illumination condition, and merging patterns determined in the step of executing processing.

Abstract: A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

Abstract: The present invention provides a lithographic difficulty metric that is a function of an energy ratio factor that includes a ratio of hard-to-print energy to easy-to-print energy of the diffraction orders along an angular coordinate ?i of spatial frequency space, an energy entropy factor comprising energy entropy of said diffraction orders along said angular coordinate ?i, a phase entropy factor comprising phase entropy of said diffraction orders along said angular coordinate ?i, and a total energy entropy factor comprising total energy entropy of said diffraction orders. The hard-to-print energy includes energy of the diffraction orders at values of the normalized radial coordinates r of spatial frequency space in a neighborhood of r=0 and in a neighborhood of r=1, and the easy-to-print energy includes energy of the diffraction orders located at intermediate values of normalized radial coordinates r between the neighborhood of r=0 and the neighborhood of r=1.

Abstract: A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask.

Abstract: A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting.

Abstract: A circuit design assisting apparatus for assisting designing of a circuit is provided. The apparatus includes a storage unit that stores information regarding a configuration of components used in a design-target circuit and wirings between the components, an acquiring unit that acquires label setting information that associates a label with the configuration information indicating the components of the design-target circuit and the wirings between the components, a selecting unit that selects, from the storage unit, information having a configuration that matches the configuration information included in the acquired label setting information. and a setting unit that sets a label that is associated with the configuration information by the acquired label setting information to the information selected by the selecting unit and registering the set label in the storage unit.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: Provided is a semiconductor device that can be reduced in size while variation in shape among circuit patterns is reduced. The semiconductor device includes multiple circuit patterns and first dummy patterns. The multiple circuit patterns are disposed at regular intervals, and are used as part of the circuit. The multiple circuit patterns consist of two outermost circuit patterns and the other inner circuit patterns. The first dummy patterns are disposed on outer sides of the two outermost circuit patterns, respectively. The distance between each of the outermost circuit patterns and the corresponding first dummy pattern is equal to a distance between any adjacent two of the circuit patterns. A width of each of the first dummy patterns is smaller than a width of any of the circuit patterns, and is equal to a minimum design rule width, for example.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein base dosages for a plurality of exposure passes are different from each other. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, wherein a plurality of charged particle beam exposure passes are used, with base dosage levels being different for different exposure passes.

Abstract: There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substrates before and after chucked on a mask stage of an exposure apparatus, forming a corresponding relation of each mask substrate, the first information and the second information, selecting the second information showing a desired flatness among the second information of the corresponding relation, and preparing another mask substrate having the same surface shape as the surface shape indicated by the first information in the corresponding relation with the selected second information, and forming a desired pattern on the above-mentioned another mask substrate.

Abstract: A method and apparatus for designing a device to operate in a coupling mode, a detection mode, or a reflection mode for incident light. The incident light has a wavelength ? and is incident upon a semiconductor structure of the device at an angle of incidence (?i). A voltage (V) is applied to the device. Each mode may be designed for an ON state and/or OFF state. For the coupling mode and detection mode, the ON state and OFF state is characterized by high and low absorption of the incident light, respectively, by the semiconductor structure in conjunction with the applied voltage V and angle of incidence ?i. For the reflection mode, the OFF state and ON states is characterized by a shift in the optical path length of ?/2 and about zero, respectively, in conjunction with the applied voltage V and angle of incidences ?i.

Abstract: A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.

Abstract: Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns.

Abstract: A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying a rules-based optical proximity correction to the selected region of the mask design shape.

Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

Abstract: An optical proximity correction operation is performed on a layout design, and faults created by the design are identified. If the faults occur where the optical proximity correction was constrained by a mask rule, then the layout design data is edited so that violation of the mask rule is avoided. Once the original layout design has been edited, another optical proximity correction operation is then performed on the edited layout design data. In this subsequent optical proximity correction operation, a simulated image is generated using the edited layout design data, but this simulated image is compared with the target image of the original layout design data rather than the edited layout design data.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: A method of fabricating a photomask used to form a lens. The method includes the steps of generating mask pattern data for each of a plurality of grid cells constituting a mask pattern for the lens, and fabricating the photomask based on the mask pattern data. The step of generating the mask pattern data includes acquiring data which represents a transmitted light distribution required for the photomask to fabricate the lens, in which the transmitted light distribution includes a quantity of transmitted light in each of the plurality of grid cells, and determining whether to place a shield on each of the plurality of grid cells by binarizing the quantity of transmitted light in each of the plurality of grid cells in order of increasing or decreasing distance from a center of the mask pattern using an error diffusion method.

Abstract: A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system.

Abstract: Some embodiments provide a method for decomposing a region of an integrated circuit (“IC”) design layout into multiple mask layouts. The method identifies a number of sets of geometries in the design layout region that must be collectively assigned to the multiple mask layouts. The method assigns the geometries in a first group of collectively-assigned sets to different mask layouts without splitting any of the geometries. The method assigns the geometries in a second group of the collectively-assigned sets to different mask layouts in such a way so as to minimize the number of splits in the geometries of the second group.

Abstract: A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots.