Abstract: A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction.

Abstract: A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

Abstract: A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: This is a method of designing a semiconductor device.

Abstract: Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of a second pattern to image intensity. In some methods of arranging mask patterns, a distribution of functions h(??x) is obtained which represents the contribution of a second pattern to image intensity on a first pattern. Neighboring regions of the first pattern are discretized into finite regions, and the distribution of the functions h(??x) is replaced with representative values h(x,?) of the discretized regions. A position of the second pattern is determined using polygonal regions having the same h(x,?). As described, the term x is the position of the first pattern and the term ? is the position of the assist.

Abstract: A method includes retrieving first layouts of an integrated circuit from a non-transitory computer-readable medium. The first layouts include a via pattern in a via layer, and a metal line pattern in a metal layer immediately over the via layer. The metal line pattern has an enclosure to the via pattern. The enclosure is increased to a second enclosure to generate second layouts of the integrated circuit.

Abstract: The present invention is directed to a technique that avoids occurrence of interference among multiple placement heads, when multiple placement heads simultaneously access a circuit board, and a pallet which is arranged in one direction with respect to the circuit board. When the component placement part 150 having the multiple placement heads simultaneously pick up the components from the pallet 160 and simultaneously place the components on the circuit board, the controller 140 specifies a pair of component groups to be picked up simultaneously from the pallet 160 by the multiple placement heads and places the components on the circuit board, so that an area where the multiple placement heads move in overlapping manner is minimized, and the placement heads respectively pick up the components included in the pair of component groups being specified and place the components on the circuit board.

Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

Abstract: In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.

Abstract: According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.

Abstract: An integrated circuit (IC) design method includes providing IC design layout data; simulating a chemical mechanical polishing (CMP) process to a material layer based on the IC design layout, to generate various geometrical parameters; extracting resistance and capacitance based on the various geometrical parameters from the simulating of the CMP process; and performing circuit timing analysis based on the extracted resistance and capacitance.

Abstract: A pattern dimension calculation method according to one embodiment calculates a taper shape of a mask member used as a mask when a circuit pattern is processed in an upper layer of the circuit pattern formed on a substrate. The method calculates an opening angle facing the mask member from a shape prediction position on the circuit pattern on the basis of the taper shape. The method calculates a dimension of the circuit pattern according to the opening angle formed at the shape prediction position.

Abstract: According to one embodiment, a design layout highly likely to be a dangerous point in a lithography process is set, a coherence map kernel for generating the mask layout is set with respect to the set design layout, the coherence map is created based on the set coherence map kernel and the set design layout, the auxiliary pattern is extracted from the created coherence map and shaped to generate the mask layout, a cost function COST for evaluating an optimization degree of the mask layout is defined, the generated mask layout is evaluated using the cost function, and at least one of parameters of the coherence map kernel and parameters in extracting and shaping the auxiliary pattern from the coherence map are changed until the mask layout evaluated using the cost function is optimized.

Abstract: The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.

Abstract: A pattern measurement apparatus includes a beam intensity distribution creation unit to scan a charged particle beam over a reference pattern having edge portions formed at a right angle to create a line profile of the reference pattern and thus create a reference-beam intensity distribution, an edge width detection unit to determine line profiles for pattern models including edges formed at various inclination angles by use of the reference-beam intensity distribution and calculate edge widths reflecting an influence of a width of a reference beam, and a correspondence table creation unit to calculate correction values for edge positions from the calculated edge widths and the pattern models and create a correspondence table in which the edge widths and the correction values are associated with one another.

Abstract: A method of optimizing a die size in a method of manufacturing devices using a lithographic apparatus, wherein the lithographic apparatus is arranged to expose an image field of variable size in a single exposure step, the image field having a certain maximum size, the method comprising: receiving a desired area for the die; and calculating a target aspect ratio for the die, wherein the target aspect ratio is determined so as to maximize the number of good dies that can be imaged per hour using the lithographic apparatus. Desirably, calculating a target aspect ratio comprises finding a first target aspect ratio that maximizes a figure of merit MF, where MF is the ratio of the number of dies exposed in each image field divided by the number of exposures on each substrate.

Abstract: Evaluating error sources associated with a mask involves: (i) receiving data representative of multiple images of the mask that were obtained at different exposure conditions; (ii) calculating, for multiple sub-frames of each image of the mask, values of a function of intensities of pixels of each sub-frame to provide multiple calculated values; and (iii) detecting error sources in response to calculated values and in response to sensitivities of the function to each error source.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: A system on a chip comprises a plurality of circuit blocks, a programmable processor and a communication circuit. Design information includes connection data including an identification of the direct mutual connection and first and second circuit blocks coupled by the direct mutual connection. An additional register is added to the system on a chip coupled to the direct mutual connection. Verification programs are used includescomprising instructions for the processor to access registers in the second one of the circuit blocks, to use the connection data, or information derived therefrom to select the first one of the circuit blocks, and to issue the standardized call to the interface program of the selected further one of the circuit blocks.

Abstract: Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range.

Abstract: In an electronic design automation technique for optical proximity correction, a mask is represented by a function with an exact analytical form over a mask region. Using the physics of optical projection, a solution based on a spatial frequency analysis is determined. Spatial frequencies above a cutoff are determined by the optical system do not contribute to the projected image. Spatial frequencies below this cutoff affect the print (and the mask), while those above the cutoff only affect the mask. Frequency components in the function below this cutoff frequency may be removed, which will help to reduce computational complexity.

Abstract: Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit.

Abstract: A method of determining an exposure condition and a mask pattern includes: setting the exposure condition and the mask pattern; temporarily determining the mask pattern using a first evaluation function describing indices of quality of an image of the mask pattern, using the set exposure condition; calculating a value of a second evaluation function describing indices of quality of the image of the mask pattern, using the temporarily determined mask pattern and the set exposure condition; changing the exposure condition and the mask pattern based on the value of the calculated second evaluation function; and judging whether to execute a process of repeating the temporarily determining step and the calculating step. In the judging step, the mask pattern temporarily determined in the latest second step, and the exposure condition changed in the latest fourth step are determined as the mask pattern and the exposure condition, respectively.

Abstract: To calculate data of an original, a computer is caused to execute the following steps of converting data regarding an intended pattern to be formed on a substrate into frequency-domain data, calculating a two-dimensional transmission cross coefficient using a function representing an effective light source that an illumination device forms on a pupil plane of a projection optical system when the original is absent on an object plane of the projection optical system and using a pupil function of the projection optical system, calculating a diffracted light distribution from a pattern that is formed on the object plane using both the frequency-domain data and data of at least one component of the calculated two-dimensional transmission cross coefficient, and converting data of the calculated diffracted light distribution into spatial-domain data to determine the data of the original.

Abstract: A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification.

Abstract: A method for designing a two-dimensional array overlay target comprises the steps of: selecting a plurality of two dimensional array overlay targets having different overlay errors; calculating a deviation of a simulated diffraction spectrum for each two-dimensional array overlay target; selecting an error-independent overlay target by taking the deviations of the simulated diffraction spectra into consideration; and designing a two dimensional array overlay target based on structural parameters of the error-independent overlay target.

Abstract: In accordance with some embodiments, a method is provided for creating a photolithographic component, comprising: determining a target pattern for a circuit layout, the target pattern comprising target features; identifying a set of periodic target features within the target pattern; calculating a relationship between feature and pitch for the set of periodic target features; and determining a mask pattern from the target pattern using the relationship, wherein the mask pattern has a set of periodic mask features configured to result in projection of a first subset of the set of periodic target features when exposed to a light source that induces a first phase effect, and configured to result in projection of a second subset of the set of periodic target features when exposed to a light source that induces a second phase effect. In further embodiments, the method outputs the mask pattern as a mask dataset.

Abstract: Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes.

Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.

Abstract: The technology disclosed relates to variable tapers to resolve varying overlaps between adjacent strips that are lithographically printed. Technology disclosed combines an aperture taper function with the variable overlap taper function to transform data and compensate for varying overlaps. The variable taper function varies according to overlap variation, including variation resulting from workpiece distortions, rotor arm position, or which rotor arm printed the last stripe. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged.

Abstract: In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell.

Abstract: A method includes capturing an image of the pattern using one or more scans across a surface of the partially completed wafer. The method includes processing information associated with the captured image of the pattern in a first format (e.g., pixel domain) into a second format, e.g., transform domain. The method includes determining defect information associated with the image of the pattern in the second format and processing the defect information (e.g., wafer identification, product identification, layer information, x-y die scanned) to identify at least one defect associated with a spatial location of a repeating pattern on the partially completed wafer provided by a reticle. The method includes identifying the reticle associated with the defect and a stepper associated with the reticle having the defect and ceasing operation of the stepper. The damaged reticle is replaced, and the process resumes using a replaced reticle.

Abstract: A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semiconductor substrate; generating resized data by enlarging the design data by a resizing quantity; generating first mask data by filling a space area having a space width of a space quantity or less of the resized data; and generating second mask data, to be aligned with the first mask data, having a window portion for selectively exposing an area determined by enlarging the space area by the resizing quantity.

Abstract: An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.

Abstract: A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.

Abstract: A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features.

Abstract: A method for verifying an optical proximity correction includes: performing an optical proximity correction on a target pattern layout; performing a primary verification on the target pattern layout which has undergone the optical proximity correction; performing a secondary verification on defect weak points detected in the primary verification; and performing an additional optical proximity correction on hot spot points which are detected in the secondary verification and which may be generated as defects when transferred to a real wafer.

Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.

Abstract: Method, apparatus, and computer readable medium for designing an integrated circuit (IC) are described. In some examples, layout data describing conductive layers of the integrated circuit is obtained. The layout data is analyzed to identify through die via (TDV) areas. A metal fill pattern is created for each of the TDV areas having a maximum metal density within design rules for the integrated circuit. The metal fill pattern for each of the TDV areas is merged with the layout data.

Abstract: A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values in the second image is determined. The contribution is selected from a set of pre-determined contributions that are a nonlinear function of the values in the region, and the selection is made based at least in part on the values in the region. The contributions are accumulated together to generate a second image. The conversion module may be, for example, part of a design flow for an integrated circuit that connects a mask simulation stage with an optical simulation stage.

Abstract: A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.

Abstract: An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

Abstract: One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer.

Abstract: In one embodiment, a photomask designing method is disclosed. The method includes dividing design pattern data into predetermined regions and obtaining a pattern perimeter for each of the divided regions. The method includes obtaining the pattern perimeter for an entire region of the design pattern data by repeating the obtaining the pattern perimeter for the each of the divided regions. The method includes obtaining a dimension conversion difference for the entire region of the design pattern data using the pattern perimeter for the entire region of the design pattern data and a correlation obtained in advance between a predicted pattern perimeter and a predicted dimension conversion difference. The method includes performing process proximity correction on the design pattern data using a value of the obtained dimension conversion difference, and creating exposure pattern data from the corrected design pattern data.

Abstract: A process for automated via doubling in a layout of a semiconductor device, comprising: selecting at least one cell of the layout for via doubling, wherein the at least one cell comprises at least two metal layers; selecting at least two metal layers of the at least one cell for via doubling; selecting metal/metal intersection areas out of the at least two metal layers, wherein a metal/metal intersection comprises an existing via interconnecting a plurality of metal layers; and dimensionally fitting additional vias into the selected metal/metal intersection areas, wherein the additional vias are placed into the layout.

Abstract: The present invention relates to a photomask and a method for determining a pattern of the photomask. The photomask includes a base and a plurality of square areas, wherein the light transmittancy of the square areas is different from that of the base. The square areas are arranged on the base with an array arrangement, and the gaps between adjacent square areas are not even. Whereby, the photomask has better normalized image log-slope (NILS) or depth of focus (DOF).