Abstract: The present disclosure provides a system and method of designing an integrated circuit. A plurality of devices are selected and properties assigned to each of the plurality of devices. These plural devices having assigned properties are then combined into a macro cell whereby a density gradient pattern is generated for the macro cell. Layout dependent effect (LDE) parameters are determined for the macro cell as a function of the combination of plural devices, and electrical performance characteristics for the macro cell are simulated. A layout distribution of the plurality of devices within the macro cell can then be determined as a function of one or more of the simulated electrical performance characteristics, determined LDE parameters, and generated density gradient pattern. A design layout of an integrated circuit can be generated corresponding to the layout distribution for the macro cell.

Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination shape, projection optics numerical aperture (NA) etc.) fixed. A cross-correlation function is created by multiplying the diffraction order functions of the mask patterns with the eigenfunctions from singular value decomposition (SVD) of a TCC matrix. The diffraction order functions are calculated for the original design rule set, i.e., using the unperturbed condition. ILS is calculated at an edge of a calculated image of a critical polygon using the cross-correlation results and using translation properties of a Fourier transform. Once an optimum separation is calculated, it is incorporated into the design rule to optimize the mask layout for improved ILS throughout the mask.

Abstract: A method and an apparatus for determining the position of a structure on a mask for microlithography, in which the position is determined by comparing an aerial image, measured by a recording device, of a portion of the mask with an aerial image determined by simulation. The position determination includes carrying out a plurality of such comparisons which differ from one another with regard to the input parameters of the simulation.

Abstract: The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.

Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Abstract: A method, system, and computer program product for improving printability of a design of an integrated circuit (IC) using pitch-aware coloring for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A first shape is identified in a layout of the IC corresponding to the design as being apart by a first distance from a second shape. The first distance is a forbidden distance and at least equal to a minimum distance requirement of a lithography system. A determination is made that the first shape and the second shape are colored using a first color. The first shape is changed to a second color, such that even though the first distance is at least equal to the minimum distance requirement of the lithography system, the first and the second shapes are placed on different masks to print the design, thereby improving the printability of the design.

Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.

Abstract: Mask design techniques for sharp corner printing in liquid crystal displays are disclosed using multiple patterns. The viewing angle and color quality of thin film transistor liquid crystal displays are largely dependent upon electrode corner sharpness as patterned in a given metal layer. Depending on design style, critical elements include convex angles, concave angles, or both convex and concave angles. Angle sharpness is dependent upon the resolution limit of a given exposure system. Since critical design element requirements exceed the capabilities of one mask, two or more masks are implemented. The determination of critical pattern features within a given layer identifies angles that are problematic for fabrication. The critical pattern features are decomposed into multiple mask layers. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the needed angles.

Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.

Abstract: A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.

Abstract: Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Abstract: A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.

Abstract: One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.

Abstract: The present invention aims at proposing a library creation method and a pattern shape estimation method in which it is possible, when estimating a shape based on comparison between an actual waveform and a library, to appropriately estimate the shape. As an illustrative embodiment to achieve the object, there are proposed a method of selecting a pattern by referring to a library, a method of creating a library by use of pattern cross-sectional shapes calculated through an exposure process simulation in advance, and a method for selecting a pattern shape stored in the library.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present invention allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present invention allows for free-form optimization, without the constraints required by conventional optimization techniques.

Abstract: A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.

Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.

Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.

Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

Abstract: The present disclosure relates to a method of controlling the manufacturing of integrated circuits, comprising steps of determining parameters that are characteristic of a curve of radiation intensity applied to a semiconductor wafer through a mask, in critical zones of structures to be formed on the wafer, for each of the critical zones, placing a measuring point in a multidimensional space each dimension of which corresponds to one of the characteristic parameters, placing control points in the multidimensional space that are spread around an area delimited by the measuring points, so as to delimit an envelope surrounding the area, for each control point, defining control structures each corresponding to a control point, generating a mask containing the control structures, applying a process involving the generated mask to a semiconductor wafer, and analyzing the control structures transferred to the wafer to detect any defects therein.

Abstract: A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

Abstract: Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. Outer markers are generated in the computing apparatus for at least a subset of the features based on the proximity of the features to one another and spacing requirements. Features are identified in the computing apparatus where the associated outer marker has at least one dimension greater than the dimensions specified for the feature.

Abstract: Computer-implemented methods are disclosed for providing an elastic modulus map of an integrated circuit (IC) chip of a chip/device package, for identifying a probable failure site of the chip/device package from the elastic modulus map of the IC chip, for modifying a connector footprint of the chip/device package based on identifying a probable failure site from the elastic modulus map of the IC chip, and for modifying the IC chip based on identifying a probable failure from the elastic modulus map of the IC chip. Each layer of the IC chip may be mapped, and each grid shape of the mapped layers may comprise a metal area and a dielectric area. Grid shapes from each layer of the IC are vertically aligned to provide a combined spring constant for each grid shape, which are then mapped onto the elastic modulus map to identify possible failure sites in the chip/device package.

Abstract: A method for determining kernels in a sum of coherent systems (SOCS) approximation is provided. Information for an object to be simulated in a manufacturing process is determined. For example, information based on geometries that are included in a layout or mask is determined. A set of kernels from a transmission cross coefficient (TCC) matrix are also determined. The set of kernels may be weighted by importance values in an order of importance. The kernels may then be re-ordered based on the information for the object. These kernels are then re-ordered in the SOCS series to reflect their order of importance. The SOCS series of kernels is then truncated at the number of kernels desired. Accordingly, by re-ordering the kernels that may be more relevant to the object to include higher weights, when the truncation occurs, the kernels that are most relevant may be included in the SOCS approximation.

Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.

Abstract: A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Abstract: The invention relates to a method for influencing the selection of a type and form of a circuit implementation in at least one layer in a given integration task for at least one integrated circuit in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. In one embodiment, a plurality of electric or electronic components are spatially arranged and to be electrically connected. Completed solutions x are stored in a database, and each of the completed solutions includes properties for the given integration task. The completed solutions define a destination space from which a solution is selectable by operating elements and determines a type and form of circuit implementation as a result of the given integration task, and aggregates the plurality of electric and electronic components in one of a plurality of integration technologies.

Abstract: The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width.

Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.

Abstract: A method of optimizing a die size in a method of manufacturing devices using a lithographic apparatus, wherein the lithographic apparatus is arranged to expose an image field of variable size in a single exposure step, the image field having a certain maximum size, the method comprising: receiving a desired area for the die; and calculating a target aspect ratio for the die, wherein the target aspect ratio is determined so as to maximize the number of good dies that can be imaged per hour using the lithographic apparatus. Desirably, calculating a target aspect ratio comprises finding a first target aspect ratio that maximizes a figure of merit MF, where MF is the ratio of the number of dies exposed in each image field divided by the number of exposures on each substrate.

Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Abstract: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation.

Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Abstract: A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.

Abstract: A system and process for utilizing probability distribution information about process parameters to quantify the probability of manufacturing process variation for variants of circuit designs in order to more efficiently analyze and simulate the designs.

Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: A method of calibrating a compact model for a lithographic process is described. In this method, the nominal compact model can be provided. Notably, an input energy effect can be separated from chemical effects and other factors regarding the photoresist. Using a processor, the compact model can be calibrated based on the input energy, thereby generating an energy-sensitive compact model. The energy-sensitive compact model can quickly construct 3D resist profiles capturing resist profile degradation at any horizontal plane. Because this method does not change any form of compact modeling, it can be integrated as is into validation and correction processes. In other embodiments, the energy-sensitive compact model can be further calibrated based on one or more of the chemical effects and/or other factors.

Abstract: A mask blank is provided by forming a plurality of films, including at least a thin film to be a transfer pattern, on a board. At the time of patterning a resist film of the mask blank according to pattern data, film information to check with a pattern is obtained for each of a plurality of the films.

Abstract: A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern.

Abstract: Methods for optimizing conductor patterns for conductors formed by ECP and CMP processes. A method includes receiving layout data for an IC design where electrochemical plating (ECP) processes form patterned conductors in at least one metal layer over a semiconductor wafer; determining from the received layout data a global effects factor corresponding to a global pattern density; determining layout effects factors for unit grid areas corresponding to the pattern density of the at least one metal layer within the unit grid areas, determining local effects factors for each unit grid area; using a computing device, executing an ECP simulator using at least one of the global effects factor and the local effects factors, and using the layout effects factor; outputting an predicted post-ECP hump data map from the ECP simulator; and if indicated by a threshold comparison, modifying the layout data.

Abstract: The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The layout is comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other. An initial set of illumination conditions is provided and a plurality of polygon patterns requiring illumination conditions critical for circuit functionality. For the initial set of illumination conditions a local cost number is calculated, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition. For each polygon pattern the cost numbers are aggregated; and the illumination conditions are varied so as to select an optimal set of illumination conditions having an optimized aggregated cost number.