Including Intermediate Code Patents (Class 717/146)
  • Patent number: 10331836
    Abstract: Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventors: Anup Hosangadi, Sumanta Datta, Aman Gayasen, Ashish Sirasao
  • Patent number: 10325031
    Abstract: Embodiments of methods and/or systems of manipulating tree expressions are disclosed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 18, 2019
    Assignee: Robert T. and Virginia T. Jenkins as Trustees of the Jenkins Family Trust dated Feb. 8, 2002
    Inventor: Jack J. LeTourneau
  • Patent number: 10310969
    Abstract: The present disclosure generally relates to predicting automated software tests for testing units of work delivery in a continuous integration development environment. More particularly, the present disclosure relates to systems and methods for improving the efficiency of code integration by predicting a subset of automated software tests from amongst a set of all available automated software tests, thereby improving testing time and reducing processing loads.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Oracle International Corporation
    Inventors: Abhijit Bhattacharjee, Manoj Dash
  • Patent number: 10268497
    Abstract: Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Hongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu
  • Patent number: 10262438
    Abstract: The representation of content, in a scene representation, is enriched with a view to the adaptive use of the latter according to a set of common parameters. A sub-graph of the scene graph, which is susceptible to variable processing, is identified. For this purpose, two new types of scene element can be defined, one of which allows the identification of the sub-graph and the second enables application of the set of common parameters in relation to the sub-graph. An example of the first type is a node of so-called “AdaptivityControl” type which encompasses the entire sub-graph, a list of the nodes describing the set of common parameters and a group of fields for dynamic updating of the content of this node. An example of the second type is a node of so-called “CompressedImageStrategy” type which comprises information relating to the object to be coded and the coding parameters.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 16, 2019
    Assignees: PROLOGUE, ASSOC. POUR LA RECHERCHE ET LE DEVELOPPEMENT DE METHODES ET PROCESSUS INDUSTRIELS “ARMINES”, INSTITUT MINES-TELECOM
    Inventors: Mihai Petru Mitrea, Bojan Joveski, Ludovico Gardenghi, Iain James Marshall, Francoise Preteux
  • Patent number: 10248545
    Abstract: A method for tracking high-level source attribution of a generated assembly language code includes: receiving commands for compiling or linking a high-level language code; analyzing the received commands to determine whether a command is a compiler command for compiling the high-level language code or a link command for linking the low level object code; when the command is a compiler command: generating assembly language code by compiling the high-level language code, parsing the generated assembly language code to generate an internal representation for the assembly language code, storing the internal representation in a computer memory; and generating associated linker input artifacts for linking; when the command is a link command: updating the internal representation with the associated linker input artifacts; and generating a report file from the updated internal representation.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 2, 2019
    Assignee: PARASOFT CORPORATION
    Inventors: Daniel J. Dominguez, Joshua William Scoggins, Richard Kent Newman, Uwe Samitsch Kronholm
  • Patent number: 10228919
    Abstract: One embodiment of the present invention sets forth a technique for reducing sign-extension instructions (SEIs) included in a computer program, the technique involves receiving intermediate code that is associated with the computer program and includes a first SEI that is included in a loop structure within the computer program, determining that the first SEI is eligible to be moved outside of the loop structure, inserting into a preheader of the loop a second SEI that, when executed by a processor, promotes an original value targeted by the first SEI from a smaller type to a larger type, and replacing the first SEI with one or more intermediate instructions that are eligible for additional compiler optimizations.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 12, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Akella Sastry, Yuan Lin
  • Patent number: 10223291
    Abstract: A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed.
    Type: Grant
    Filed: May 15, 2010
    Date of Patent: March 5, 2019
    Assignee: NXP B.V.
    Inventors: Ernst Haselsteiner, Christian Kirchstaetter
  • Patent number: 10198580
    Abstract: A process transforms compiled software into a semantic form. The process transforms the code into a semantic form. The process analyzes behavior functionality by processing precise programming behavior abstractions stored in a memory and classifies the code as malware based on the code behavior. Another method identifies the starting point of execution of a compiled program. The method calculates a complexity measure by calculating the number of potential execution paths of local functions; identifies the number of arguments passed to local functions; and identifies the starting point of execution of the compiled program. Another method provides interactive, dynamic visualization of a group of related functions wherein a user can explore the rendered graph and select a specific function and display functions that are color coded by their ancestral relation and their function call distance to the selected function.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 5, 2019
    Assignee: UT-BATTELLE, LLC
    Inventors: Kirk D. Sayre, Richard A. Willems, Stephen Lanse Lindberg
  • Patent number: 10191725
    Abstract: Disclosed are ways to flexibly arrange, rearrange, and execute optimization modules for program code in user-customizable sequences. In various embodiments, computer programmers can select an order of multiple standalone optimizers that each perform an optimization function on program code, forming a pipeline of a series of optimization modules. The pipeline can be modified by, for example, adding, removing, rearranging, repeating, and/or replacing optimization modules.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 29, 2019
    Assignee: Facebook, Inc.
    Inventors: Shane Roland Nay, Bertrand Allen Maher
  • Patent number: 10175963
    Abstract: A method is provided for executing a code sequence on a security module. The code sequence comprises codes to be replaced and codes to be interpreted. A temporary replacement takes place of a respective code to be replaced by a partial code sequence that comprises at least one code having an interpretable code value. The replacement taking place is dependent on the code value of the code to be replaced. An interpretation of the codes to be interpreted in the code sequence and in the partial code sequence takes place with the aid of interpretation information for code values. During the replacement step, the partial code sequence for the code value of the code to be replaced is additionally produced in dependence on a piece of selection information.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: January 8, 2019
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY GMBH
    Inventors: Deepen Mantri, Jörn Treger, Christian Dönges
  • Patent number: 10157062
    Abstract: A method is described for operating a microprocessor, in which a conversion software executed in the microprocessor carries out a binary translation, in the course of which a source instruction that is encoded according to a first instruction-set architecture is translated into a target instruction in a binary manner, which is encoded according to a second instruction-set architecture, and the target instruction translated by the translation software into the second instruction-set architecture being replicated, and in this replicated target instruction a memory area which is to be accessed in the course of the execution of the target instruction is replaced by a second memory area, and the target instruction and the copied target instruction is executed by the microprocessor.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 18, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Jaroslaw Topp
  • Patent number: 10152408
    Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 11, 2018
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Craig E. Hampel
  • Patent number: 10152310
    Abstract: A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 11, 2018
    Assignee: Nvidia Corporation
    Inventors: Mahesh Ravishankar, Paulius Micikevicius, Vinod Grover
  • Patent number: 10120664
    Abstract: A computer-implemented method includes receiving a set of complete source instructions to process a source code entity, an incremental build part, and a set of file definitions. The method analyzes the set of complete source instructions. The method identifies, from the set of analyzed source instructions, a set of operations that reference the incremental build subset. The method repeats: (i) determining, for each operation, whether any additional files are affected by the operation, the additional files forming a set of affected files; (ii) creating a combined set of files, the combined set of files consisting of the set of affected files and the incremental build subset; and (iii) updating the set of operations to include those from the analyzed source instructions that reference the combined set of files; until no new files are added to the combined set of files. The method generates a set of incremental source instructions.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Fulton, Gary I. Mazo, Brian W. Svihovec
  • Patent number: 10114877
    Abstract: Certain aspects of the present disclosure relate to a technique to access a data source from a client using a driver. A data source name (DSN) is provided to connect to the data source using the driver. The driver is used to interface between the client and an implementation of a driver interface to access the data source based on the DSN.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Open Invention Network LLC
    Inventor: Marc Todd Yaeger
  • Patent number: 10042645
    Abstract: A method of compiling a first program to output a second program, the method includes: determining a number of arithmetic units to be operated during execution of the second program for each of a plurality of sections in the first program; and creating the second program by adding an instruction to specify the number of arithmetic units to be operated to each of the plurality of sections based on the determining.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: August 7, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Masanori Yamanaka, Masatoshi Haraguchi
  • Patent number: 10042621
    Abstract: In one example embodiment, live migration in a datacenter may include JIT compiling a process that is configured to be executed on both a source instruction set architecture and a destination instruction set architecture, mapping variables and address stacks of the process on both the source instruction set architecture and the destination instruction set architecture into a labeled form thereof, and mapping the labeled form of the variables and address stacks onto the destination instruction set architecture.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 7, 2018
    Assignee: Empire Technology Development LLC
    Inventors: Ezekiel Kruglick, Kevin S. Fine
  • Patent number: 10033387
    Abstract: A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 24, 2018
    Assignee: Altera Corporation
    Inventors: Doris Chen, Deshanand Singh
  • Patent number: 10025574
    Abstract: A digital marketplace stores an installable web application including a first packaged file including a manifest file and a web page. The digital marketplace receives a request for installation of the installable web application from a computing device. The digital marketplaces automatically determines a computing platform type of the computing device, based on the request, and automatically creates a version of an installation file for the installable web application based on the computing platform type. The version of the installation file includes a portion of the first packaged file. The version of the installation file is smaller than the first packaged file. The digital marketplace provides the version of the installation file to computing device.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: July 17, 2018
    Assignee: GOOGLE LLC
    Inventors: Antony John Sargent, Erik Kay
  • Patent number: 9934012
    Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 3, 2018
    Assignees: DENSO CORPORATION, WASEDA UNIVERSITY
    Inventors: Kazushi Nobuta, Noriyuki Suzuki, Hironori Kasahara, Keiji Kimura, Hiroki Mikami, Dan Umeda
  • Patent number: 9916145
    Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Junjuan Xu, Paul Glendenning
  • Patent number: 9906620
    Abstract: An optimizer for messaging systems learns the purpose and context of each message and combines that information with knowledge of the specific client that will be rendering the response, such as a specific HTML browser. Any of a number of optimization factors can be applied, singly or in any combination. Messages are analyzed offline until a configurable threshold is reached, indicating that enough data has been sampled to develop a valid instruction set, to be applied to the responses that a server generates for a particular request. Responses are parsed into tokens and instructions for each type of token are compiled into instruction sets that are stored. These instructions sets continue to be iteratively improved as more data is collected, until the configurable sampling threshold is reached.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: February 27, 2018
    Assignee: Radware, Ltd.
    Inventor: Kent Alstad
  • Patent number: 9904527
    Abstract: Based on source code analysis of an API-invoker program, an expendable set of source code sections of an API-implementer program is identified. The expendable set corresponds to operations which are not expected to be performed on behalf of the API-invoker program at a particular computing environment. An optimized binary version of the API-implementer program is generated, which does not include executable code corresponding to the expendable set. The optimized binary version is transmitted to the computing environment for deployment.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: February 27, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Konrad Jan Miller, Michael Tautschnig
  • Patent number: 9898388
    Abstract: This application discloses a computing system configured to simulate an embedded system including a processor capable of executing embedded software, compile the embedded software into a format capable of execution by the computing system, insert instrumentation code into the compiled embedded software, and execute the compiled embedded software and the instrumentation code. The execution of the compiled embedded software can simulate execution of the embedded software by the processor in the simulated embedded system, while the execution of the instrumentation code can configure the computing system to gather information corresponding to the execution of the compiled embedded software.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 20, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Alex Rozenman, Vladimir Pilko
  • Patent number: 9891900
    Abstract: Generic method specialization represents the ability to specialize generic methods over various types. When implementing generic method specialization an annotated class file may include a generic method declaration that is annotated with specialization metadata indicating elements of the generic method to be adjusted during specialization. The annotated method may be usable directly as an erased method implementation (e.g., to load the method when instantiated with reference types) and may also be usable as a template for specialization. When a generic method is being prepared for execution, such as when it is first invoked during runtime, a specialization method generator function may be used to specialize the generic method based on the specialization metadata in the generic method declaration. The specialization method generator function may use the annotated generic method declaration as a template for specialization.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: February 13, 2018
    Assignee: Oracle International Corporation
    Inventors: Brian Goetz, John R. Rose, Maurizio Cimadamore
  • Patent number: 9875101
    Abstract: Aspects of the disclosure provide a method for identifying an induction variable in a loop during a compiling process. The method includes searching for a phi-function that includes a first operand and a second operand and defines a candidate basic induction variable (BIV), searching for an add/sub instruction that has a first register and a second register wherein the first register is the second operand of the phi-function, or the value in the first register is subsequently stored to the second operand of the phi-function through one or more move instructions, and determining the candidate BIV is a BIV when the second register of the add/sub instruction is the candidate BIV or stores a value that is passed from the candidate BIV through one or more move instructions.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 23, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xinyu Qi, Liping Gao, Haitao Huang, XingXing Pan, Pengfei Li
  • Patent number: 9830268
    Abstract: An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory accesses among the decoded commands, a hardware prefetch controller configured to execute a prefetch in response to a trigger independent of a prefetch command to execute the prefetch, the prefetch being an operation of transferring data stored in a memory to a cache memory in advance, and a controller configured to determine whether an unnecessary prefetch command to transfer the data, which is to be transferred to the cache memory by the hardware prefetch controller, from the memory to the cache memory is registered in the command holding unit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding unit.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shigeru Kimura
  • Patent number: 9754392
    Abstract: Aspects of the subject matter described herein relate to data visualization. In aspects, a caller sends a request to draw a set of shapes that have a shape type common among the shapes. The request may be for a static drawing or 1 of N animation frames. If the device has a graphical processing unit (GPU) that is available, GPU code is generated for the GPU to draw the set of shapes. Otherwise, CPU code is generated to draw the set of shapes. The drawing code is tailored to the constant, data-mapped, and animated attribute values specified by the caller and omits conditional statements that test values that are computable prior to drawing the shapes.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 5, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Roland Lucas Fernandez, Steven M. Drucker
  • Patent number: 9733911
    Abstract: System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: August 15, 2017
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Hojin Kee, Tai A. Ly, David C. Uliana, Adam T. Arnesen, Newton G. Petersen
  • Patent number: 9727604
    Abstract: A computer implemented method for generating code for an integrated data system. A mixed data flow is received. The mixed data flow contains mixed data flow operators, which are associated with multiple runtime environments. A graph is generated containing logical operators based on the mixed data flow in response to receiving the mixed data flow. The logical operators are independent of the plurality of runtime environments. The graph is converted to a model. The logical operators are converted to model operators associated with the multiple runtime environments. The model operators allow for analysis of operations for the mixed data flow. The model is converted into an execution plan graph. The execution plan graph is executable on different runtime environments.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: August 8, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qi Jin, Hui Liao, Sriram K. Padmanabhan, Lin Xu
  • Patent number: 9690604
    Abstract: A language-based model to support asynchronous operations set forth in a synchronous syntax is provided. The asynchronous operations are transformed in a compiler into an asynchronous pattern, such as an APM-based pattern (or asynchronous programming model based pattern). The ability to compose asynchronous operations comes from the ability to efficiently call asynchronous methods from other asynchronous methods, pause them and later resume them, and effectively implementing a single-linked stack. One example includes support for ordered and unordered compositions of asynchronous operations. In an ordered composition, each asynchronous operation is started and finished before another operation in the composition is started. In an unordered composition, each asynchronous operation is started and completed independently of the operations in the unordered composition.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 27, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Niklas Gustafsson, Geoffrey M. Kizer
  • Patent number: 9612737
    Abstract: A device and method for processing virtual worlds. According to embodiments of the present disclosure, information which is measured from the real world using characteristics of a sensor is transferred to a virtual world, to thereby implement an interaction between the real world and the virtual world. The disclosed device and method for processing virtual worlds involve selectively transferring information, from among the measured information, which is different from previously measured information. The disclosed device and method for processing virtual worlds involve transferring the entire measured information in the event that the measured information is significantly different from the previously measured information and for selectively transferring information, from among the measured information, which is different from the measured information in the event that the difference is not significant.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Ju Han, Jae Joon Han, Won Chul Bang, Do Kyoon Kim
  • Patent number: 9602622
    Abstract: A cache management system, method, and computer-readable medium which manage caching of resources are provided. The method includes receiving a request for a resource including a hierarchical resource locator, fetching the resource from a node upon determining that the resource is not stored in a cache, adding an entry for the resource to a mapping table associated with the cache, the entry including the resource locator and dependency information for dependent resources identified from the hierarchical structure of the resource locator, and updating entries in the mapping table for master resources identified from the hierarchical structure of the resource locator, the updated entries including an identifier for the resource.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: March 21, 2017
    Assignee: Neustar, Inc.
    Inventor: Hubert Andre Le Van Gong
  • Patent number: 9594779
    Abstract: Provided are a computer program product, system, and method for generating a view for a schema. A schema provides a definition of elements, wherein at least one of the elements comprises a recursive element of a recursive data type, wherein the recursive data type allows for instances of the recursive element to include instances of that same recursive data type at different levels in a hierarchy. Indication is received to transform the recursive types to non-recursive structures. A view for the schema is generated including information on the indication to transform the recursive types to non-recursive structure, wherein the processing of the data defined by the view causes a parser to generate a structured element for each instance of the recursive element in schema data being parsed, wherein the generated structured element includes a unique identifier of the instance of the recursive element.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey M. Fischer, John C. Holmes, Jeff J. Li, Yong Li
  • Patent number: 9591538
    Abstract: A method of processing a handover request from a base station controller (BSC) of a GSM (Global System for Mobile communication)-type network. The method comprises the steps of passing a handover request with GSM-type parameters from a base station controller (BSC) through a Master Switching Center (MSC) of the GSM-type network to a UMTS core network (CN) and to a Radio Network Controller (RNC) of the UMTS (Universal Mobile Telecommunications System) network, translating the GSM-type parameters to UTRAN parameters in the Radio Network Controller (RNC), and allocating UTRAN resources in response to the translated parameters.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 7, 2017
    Assignee: NEC Corporation
    Inventors: Gina Parmar, Robert Patterson
  • Patent number: 9542211
    Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park
  • Patent number: 9507576
    Abstract: A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Motohiro Kawahito
  • Patent number: 9495140
    Abstract: A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Motohiro Kawahito
  • Patent number: 9477453
    Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Tugrul Ince, Koichi Yamada, Paul Caprioli, Jiwei Lu
  • Patent number: 9459862
    Abstract: Techniques to automatically port applications to a mobile infrastructure using code separation with semantic guarantees are disclosed. Porting enterprise applications from to a target architecture another is effected via separating code into constituent layers of the target architecture. To preserve semantics, code transformations are enforced via an abstract syntax tree structure. The generated code may have various code wrappers and/or infrastructure elements so the ported application will operate in the target architecture. Various techniques are disclosed regarding specific code wrappers and/or infrastructure elements to address operating issues including, but not limited to, architectural issues, network latency, framework changes, regulatory issues.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 4, 2016
    Assignee: ArtinSoft Corporation
    Inventors: Carlos Araya, Iván Sanabria, Federico Zoufaly, Mauricio Rojas, Edgar Infante, Olman Garcia
  • Patent number: 9454401
    Abstract: A resource allocation method and apparatus utilize the GPU resource efficiently by sorting the tasks using General Purpose GPU (GPGPU) into operations and combining the same operations into a request. The resource allocation method of a Graphic Processing Unit (GPU) according to the present disclosure includes receiving a task including at least one operation; storing the at least one operation in unit of request; merging data of same operations per request; and allocating GPU resource according to an execution order the request.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: September 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwonsik Kim, Youngwoo Ahn, Jeongig Song, Inchoon Yeo
  • Patent number: 9442733
    Abstract: Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Bret L. Toll, Robert Valentine, Jesus Corbal, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney
  • Patent number: 9424013
    Abstract: In transactional memory systems, transactional aborts due to conflicts between concurrent threads may cause system performance degradation. A compiler may attempt to minimize runtime abort rates by performing code transformations and/or other optimizations on a transactional memory program in an attempt to minimize store-commit intervals. The compiler may employ store deferral, hoisting of long-latency operations from within a transaction body and/or store-commit interval, speculative hoisting of long-latency operations, and/or redundant store squashing optimizations. The compiler may perform optimizing transformations on source code and/or on any intermediate representation thereof (e.g., parse trees, un-optimized assembly code, etc.). The compiler may preemptively avoid naïve target code constructions.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: August 23, 2016
    Assignee: Oracle America, Inc.
    Inventor: David Dice
  • Patent number: 9389933
    Abstract: Described herein are implementations for providing a platform adaptation layer that enables applications to execute inside a user-mode hardware-protected isolation container while utilizing host platform resources that reside outside of the isolation container. The platform adaptation layer facilitates a system service request interaction between the application and the host platform. As part of the facilitating, a secure services component of the platform adaptation layer performs a security-relevant action.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 12, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andrew A. Baumann, Galen C. Hunt, Marcus Peinado
  • Patent number: 9390260
    Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 12, 2016
    Assignee: Lehigh University
    Inventors: Gang Tan, Ben Niu
  • Patent number: 9384327
    Abstract: A system for managing and exchanging electronic information provides a rules management component for executing conceptual rules, an ontology management component, an information model management component, and a system configuration management component. The ontology management component manages at least one ontology and mappings between members of different ontologies. The ontologies may include a code system and a terminology. The ontology management component may manage a value set that is a subset of the terminology. The information model management component manages one or more information model schemas, each defining an information model and comprising information defining at least one slot within the information model. The system configuration management component manages configuration information on the configuration of each system component.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 5, 2016
    Assignee: Clinerion Ltd.
    Inventors: Tim Snyder, Alan Peter Honey
  • Patent number: 9378013
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a full set of analysis artifacts after incremental analysis of a source code base. One of the methods includes receiving a first full set of analysis artifacts and an incremental set of analysis artifacts for a project. An initial keep graph that is initially equivalent to the full build graph is generated. Any source code file or analysis artifact nodes that also occur in the incremental build graph are removed from the keep graph. Analysis artifacts for source code files in the full build graph that do not occur in the keep graph are deleted from the first full set of analysis artifacts. The analysis artifacts represented by nodes in the incremental build graph are copied into the first full set of analysis artifacts to generate a second full set of analysis artifacts for the project.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 28, 2016
    Inventor: Julian Tibble
  • Patent number: 9361102
    Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 7, 2016
    Assignee: Lehigh University
    Inventors: Gang Tan, Ben Niu
  • Patent number: 9292274
    Abstract: The present invention reduces the time required to apply an update package for generating a new image from an original image within a non-volatile memory device by effectively reducing the number of flash blocks requiring modification by use of whatever free space is available at the end of the image as required. A set of software development guidelines and an improved firmware development tool chain (i.e. compiler, linker, etc.) are utilized to produce new firmware for the client device. A firmware programmer follows or applies this set of guidelines when developing new features and fixes for distribution via a new firmware image. The improved firmware development tool chain executes on a collection of function blocks, available from the development of the original image, used to create new firmware source code, which when complied and linked yields a new image, prior to the delta or differencing processing.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 22, 2016
    Assignee: Smith Micro Software, Inc.
    Inventor: Paul Edmonds