Including Intermediate Code Patents (Class 717/146)
  • Patent number: 11902277
    Abstract: Techniques for providing secure modification of manufacturer usage description (MUD) files based on device applications are provided. In one embodiment, a method for secure modification of MUD files may include obtaining a request for one or more applications from a device. The method also includes providing to the device the one or more applications and a certification that includes an updated MUD identifier determined based on the one or more applications requested. The updated MUD identifier is associated with a concatenated MUD file that comprises individual MUD file portions for each of the one or more applications requested. The device is configured to request an updated device identifier using the certification. The updated device identifier includes the updated MUD identifier that is associated with the concatenated MUD file.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: February 13, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Eliot Lear, Christopher S. Steck, Brian Weis
  • Patent number: 11886847
    Abstract: A system for generating executable code of a software program that is matched with an intermediate representation (IR) of a source code of the software program. The system comprises a processor adapted for adding one or more annotation entries, each for a location in the IR, to program data in the IR. An internal annotation entry is generated for an internal location in the IR that is not referenced by an IR symbol in the global IR symbol table of the IR. The processor is further adapted for compiling the IR to produce a binary object comprising the annotation entries, and providing the binary object to a linker or to a dynamic loader to update in an executable object an executable internal annotation entry associated with an internal annotation entry to reference a run-time location in the executable object.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 30, 2024
    Assignee: Next Silicon Ltd
    Inventor: Itay Bookstein
  • Patent number: 11868759
    Abstract: Shader source code performance prediction is described. In accordance with the described techniques, an update to shader source code for implementing a shader is received. A prediction of performance of the shader on a processing unit is generated based on the update to the shader source code. Feedback about the update is output. The feedback includes the prediction of performance of the shader. In one or more implementations, generating the prediction of performance of the shader includes compiling the shader source code with the update to generate a representation of the shader, inputting the representation of the shader to one or more machine learning models, and receiving the prediction of performance of the shader as an output from the one or more machine learning models.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: January 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit Ben-Moshe, Ian Charles Colbert
  • Patent number: 11829736
    Abstract: The present disclosure relates to a system and a method of optimizing register allocation by a processor. The method comprising receiving an intermediate representation (IR) code of a source code and initializing single instruction multiple data (SIMD) width for the IR code. The method comprising analyzing each basic block of the IR code to classify determine one or more instructions of the IR code as vector instructions, wherein each basic block is one of LOAD, STORE and arithmetic logical and multiply (ALM) instructions. The method comprising dynamically setting the SIMD width for each of the vector instructions.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: November 28, 2023
    Assignee: Blaize, Inc.
    Inventors: Pathikonda Datta Nagraj, Aravind Rajulapudi, Ravi Korsa
  • Patent number: 11829738
    Abstract: A block frequency of a block in an irreducible loop in computer code is statically determined. The statically determining includes splitting an incoming block mass among multiple loop headers of the irreducible loop to provide an initial mass for the block. A bottom-up traversal and a top-down traversal of a plurality of loops of the computer code including the irreducible loop are iteratively performed to update a mass of the block. The iteratively performing commences with propagating the initial mass of the block to one or more blocks of one or more loops of the plurality of loops and continues with propagating and updating masses of select blocks of the plurality of loops until a predefined point is reached providing a resulting mass for the block. The block frequency of the block is determined using the resulting mass and is to be used in processing associated with the computer code.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 28, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeeva Paudel, Shimin Cui
  • Patent number: 11797317
    Abstract: A software development process may support a transition from unverifiable, legacy code to verifiable code that is provably correct by construction. A behavioral model may be developed for legacy software that includes various behavioral criteria. Then, source code implemented in a verifiable language may be verified using the behavioral model to perform verification. Once the source code is complete and verified, a new verified implementation may be compiled. The verified implementation may then be executed, along with the legacy software, to identify differences in behavior which are fed back into the behavioral model and subsequently into the new source code. This process may then be iterated with the verifiable code being deployable once behavioral differences are resolved.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 24, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Sean McLaughlin, Tongtong Xiang, Matthias Schlaipfer, Neha Rungta, Serdar Tasiran, John Byron Cook, Michael William Whalen
  • Patent number: 11783520
    Abstract: This disclosure provides a picture generation method, apparatus, electronic device and storage medium. The picture generation method includes: acquiring a plurality of content elements contained in a design of a target picture, the content elements having respective attribute information, in response to a drawing instruction, parsing the content elements to obtain one or more graphic elements for each of the plurality of content elements, each graphic element having an associated graphic parameter that corresponds to the attribute information of a respective content element, drawing the graphic elements according to the associated graphic parameters to obtain content element pictures for respective content elements, and combining the obtained content element pictures to generate the target picture.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 10, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Ang Li
  • Patent number: 11775268
    Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: October 3, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Preston Pengra Briggs, Ron Diamant, Robert Geva
  • Patent number: 11762640
    Abstract: An information conversion device has one of: a replication necessity analysis unit for specifying where an instruction referred by phi functions is present in one basic block and inserting a transfer instruction therein; an intra-loop constant analysis unit for specifying a closed path in which a phi function reference is circulated and inserting the transfer instruction therein; an inter-instruction dependency analysis unit for specifying where data dependency is present between instructions as a reference destination of the phi functions and inserting the transfer instruction therein; a same instruction reference analysis unit for specifying where the phi functions referring to a result of a same instruction before branching are present and inserting the transfer instruction therein; and a spill out validity analysis unit for storing a value present in a loop processing, loading the value after the loop processing ends, and deleting the transfer instruction.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 19, 2023
    Inventors: Hidetsugu Irie, Shuichi Sakai, Toru Koizumi, Satoshi Nakae, Akifumi Fukuda
  • Patent number: 11762641
    Abstract: A method of allocating variables to computer memory includes determining at compile time when each of the plurality of variables is live in a memory region and allocating a memory region to each variable wherein at least some variables are allocated at compile time to overlapping memory regions to be stored in those memory regions at runtime at non-overlapping times.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 19, 2023
    Assignee: Graphcore Limited
    Inventors: Godfrey Da Costa, Timothy David Hutt
  • Patent number: 11714636
    Abstract: Described herein are embodiments for managing comments in a program code file. A system may select program code and compile it to an intermediary code. The system may compare the intermediary code to a library of intermediary code snippets associated with comments. Based on the comparison, a system may recognize the code to be obsolete. In some embodiments, a system may generate one or more recommendations to update a code. Based on received feedback regarding a recommendation, a system may accordingly update a code.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: August 1, 2023
    Assignee: Capital One Services, LLC
    Inventors: Reza Farivar, Kenneth Taylor, Austin Grant Walters, Fardin Abdi Taghi Abad, Anh Truong, Vincent Pham, Jeremy Edward Goodsitt
  • Patent number: 11681508
    Abstract: Techniques to process a source code program include, by one or more processors, determining an analysis perspective is exhibited by one or more portions of the source code program based at least in part on processing the source code program and an analysis perspective definition collection. The techniques further include storing a mapping of the analysis perspective to event data that is generated by object code when executed by one or more processors of a target computing system, wherein the object code is associated with the one or more source code program portions that exhibit the analysis perspective.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 20, 2023
    Inventor: Pratap Pereira
  • Patent number: 11669311
    Abstract: Systems, methods, and other embodiments associated with the valuation of software code abstractions are described. In one embodiment, the method includes generating a directed acyclic graph (DAG) comprising a vertex node, children nodes, and a plurality of edges, wherein the vertex node includes a software code abstraction. A DAG is generated for each vertex node associated with a software code abstraction. The directed acyclic graph is analyzed to determine inheritance of the software code abstraction from the vertex node to the children nodes. A weight having a numerical value is assigned to the edges located between the vertex node and the children nodes. The numerical values are parsed to determine a cumulative sum of all of the edges associated with a particular vertex node. The cumulative sums are compared to determine an impact of the software code abstraction associated with each of the vertex nodes.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: June 6, 2023
    Assignee: Oracle International Corporation
    Inventor: Swanand Rao
  • Patent number: 11630798
    Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 18, 2023
    Assignee: Google LLC
    Inventor: Russell C. McKown
  • Patent number: 11537372
    Abstract: Methods and systems describe providing a compilable machine code program from dynamic language code. First, the system receives a computer program consisting of code in a dynamic language. For each dynamic instruction within the code, the system: identifies all function calls within the code which may call the dynamic instruction; generates a super slice callgraph for all identified function calls for the dynamic instruction, including dependency relationships for instance variables and static variables within time constraints; and generates a set of slices for the dynamic instruction. The system then compiles and executes each slice to identify one or more values for each dynamic instruction. Next, the system updates the computer program such that each of at least a subset of the dynamic instructions is replaced with machine code instructions based on the corresponding values.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 27, 2022
    Assignee: Manycore Corporation
    Inventor: Nicolas Toper
  • Patent number: 11507361
    Abstract: System to design and/or update programs for the operator interface of machines and/or plants that comprises at least one first calculation device dedicated to the management of a machine and/or plant, which contains at least one application program to manage the human-machine interface (HMI) of the machine and/or plant, and a second calculation device to execute a software, or development environment, to create a project file, wherein on the first calculation device and on the second calculation device respective communication programs are installed, suitable to transfer the project to the first calculation device, where the application program for the management of the HMI interface displays the project by means of a suitable OPC UA standard information model, by means of which it is possible to make modifications to the project dynamically, without interrupting the execution of the human-machine interface program, and so that every modification to the project, and therefore to the human-machine interface pr
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: November 22, 2022
    Assignee: ASEM S.R.L.
    Inventors: Maurizio Fumagalli, Alberto Riccio
  • Patent number: 11487521
    Abstract: A system and method to translate source code in a source language executable in a source computing system to a target language executable in a target computing system. Source code in the source language is parsed to generate a corresponding parse tree containing at least one tree node and at least one leaf. During traversal of the parse tree, at least one mutation script is applied. The mutation script directs at least one of: generating a stream expression comprising at least one token corresponding to values of the at least one node and the at least one leaf of the parse tree; and formulating at least one text output containing a text pattern specified in the mutation script and/or values of the at least one token. Source code in the target language is outputted based on the at least one text output.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 1, 2022
    Assignee: Next Pathway Inc.
    Inventors: Vladimir Antonevich, Badih Schoueri, Qiang Yu
  • Patent number: 11461115
    Abstract: Technologies are provided for generating executable asset bundles using a plug-in module loaded in an integrated development environment (IDE). The IDE can be used to create and edit source code assets and three-dimensional (3D) model assets that can be compiled into an executable program. The plug-in module can be used to generate an executable asset bundle based on a subset of the source code assets. Optionally, the executable asset bundle can include a subset of the 3D model assets. The IDE can be used to generate an executable program based on the remaining source code assets and 3D model assets. The executable program and the executable asset bundle can be distributed separately. The executable program can be executed by a client computing device and used to load the executable asset bundle on the client device. Loading the executable asset bundle can comprise downloading it from a remote server.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: October 4, 2022
    Assignee: SAP SE
    Inventors: Michael Spiess, Jonathan Markgraf
  • Patent number: 11455148
    Abstract: A natural language command from an operator is received. The command regards a task that a software system is to execute. A programming language in which to program the task is determined by analyzing a plurality of factors regarding the task and the software system. Code is output in the programming language that executes the task.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Craig M. Trim, Shikhar Kwatra, Indervir Singh Banipal, Gray Franklin Cannon
  • Patent number: 11442845
    Abstract: A computer-implemented method comprising obtaining a first candidate test associated with a testable component, wherein the first candidate test comprises an input having an input value; generating a second candidate test associated with the testable component by performing a dynamic mutation-based fuzzing of the first candidate test, wherein the second candidate test is based on the first candidate test and comprises a modified input value for the input based on data generated during an execution of the first candidate test or domain knowledge associated with the testable component; and creating a test for the testable component based on the first candidate test or the second candidate test.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 13, 2022
    Assignee: DIFFBLUE LTD
    Inventors: Peter Schrammel, Daniel Kroening
  • Patent number: 11397694
    Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sean S. Eilert, Kenneth Marion Curewitz, Justin M. Eno
  • Patent number: 11314911
    Abstract: High-level synthesis implementation of data structures in hardware can include detecting, within a design and using computer hardware, a data structure and a compiler directive for the data structure. The design may be specified in a high-level programming language. Using the computer hardware and based on the compiler directive, a modified version of the design may be created by, at least in part, generating a modified version of the data structure based on the compiler directive. Using the computer hardware, a circuit design may be generated from the modified version of the design by creating, at least in part, a hardware memory architecture for the circuit design and mapping the modified version of the data structure onto the hardware memory architecture.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 26, 2022
    Assignee: Xilinx, Inc.
    Inventors: Fangqing Du, Sheng Wang, Alain Darte, Alexandre Isoard, Hem C. Neema, Lin-Ya Yu
  • Patent number: 11210071
    Abstract: The present disclosure relates to devices and methods for transforming program source code using a rematerialization operation. The devices and methods may identify at least one hot spot with high register pressure in a program source code for an application and identify a plurality of live variables within the at least one hot spot. The devices and methods may group the plurality of live variables by a basic block that has contained a define or single use of the plurality of live variables. The devices and methods may build a directed acyclic graph (DAG) for each basic block that has a grouped plurality of live variables. The devices and methods may save the DAG as a candidate instruction to move in the program source code and may generate transformed program source code for the application by moving the candidate instruction.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: December 28, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Xiang Li, David McCarthy Peixotto, Michael Alan Dougherty
  • Patent number: 11194307
    Abstract: A controller capable of preventing human mistakes by customizing checking contents upon operations of users to automatically perform customized checking appropriately is provided. A controller that controls an industrial machine includes: a receiving unit that receives a condition of a callback process associated with control of the industrial machine and an action corresponding to the condition; and a designated condition registering unit that registers the condition and the action received by the receiving unit as a callback process.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 7, 2021
    Assignee: FANUC CORPORATION
    Inventor: Daijirou Koga
  • Patent number: 11188656
    Abstract: In one form, a software system includes a first non-transitory computer readable medium storing a source code program, a second computer readable medium, and a compiler. The first non-transitory computer readable medium includes a first function having a return type greater than a native width of a target processor, and a second function that calls the first function and that conditionally branches based on comparing a returned value from the first function to an expected value, wherein the expected value has first and second portions that are not equal to zero and are not equal to each other. The compiler converts the source code program in the first non-transitory computer readable medium into a machine language program for storage in the second computer readable medium. The compiler optimizes the source code program by selectively combining a set of redundant machine language instructions into a smaller set of machine language instructions.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 30, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Steven Jan Anne Ward Cooreman
  • Patent number: 11106434
    Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for generating program code. In one embodiment, a method for generating program code is disclosed, including: acquiring code configuration information that includes code function information indicating a target function and device configuration information of a target device; and generating program code based on the code configuration information, wherein when executed, the program code can cause the target device to implement the target function. Through the embodiments of the present disclosure, the diversity and flexibility of function implementation can be improved, and the workload of developing program code can be significantly reduced.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jinpeng Liu, Jin Li, Jiacheng Ni, Danqing Sha
  • Patent number: 11093229
    Abstract: A failure rate model modeling a failure rate of a training functionality deployment in a training set of functionality deployments is constructed. The failure rate model is configured to receive functionality deployment data and output a corresponding failure rate prediction. Using the failure rate model, a set of functionality deployment failure rates is predicted, a functionality deployment failure rate in the set of functionality deployment failure rates corresponding to an upcoming functionality deployment. Using the set of functionality deployment failure rates, a deployment sequence of the set of upcoming functionality deployments is constructed to minimize a predicted overall failure rate of the set of upcoming functionality deployments. The deployment of each functionality deployment in the set of upcoming functionality deployments is caused, the deployment comprising activating the upcoming functionality program code according to the deployment sequence.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pranshu Tiwari, Harish Bharti, Naveen Narayanaswamy, Ram Prasad Reddy Munagala
  • Patent number: 11082438
    Abstract: Techniques are provided herein for contextual embedding of features of operational logs or network traffic for anomaly detection based on sequence prediction. In an embodiment, a computer has a predictive recurrent neural network (RNN) that detects an anomalous network flow. In an embodiment, an RNN contextually transcodes sparse feature vectors that represent log messages into dense feature vectors that may be predictive or used to generate predictive vectors. In an embodiment, graph embedding improves feature embedding of log traces. In an embodiment, a computer detects and feature-encodes independent traces from related log messages. These techniques may detect malicious activity by anomaly analysis of context-aware feature embeddings of network packet flows, log messages, and/or log traces.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 3, 2021
    Assignee: Oracle International Corporation
    Inventors: Juan Fernandez Peinador, Manel Fernandez Gomez, Guang-Tong Zhou, Hossein Hajimirsadeghi, Andrew Brownsword, Onur Kocberber, Felix Schmidt, Craig Schelp
  • Patent number: 11061653
    Abstract: Implementations of the present disclosure relate a method, system and computer program products that dynamically compile conditional statements. According to the method, a first number of times that a first conditional statement of a plurality of conditional statements has been satisfied during execution of the plurality of conditional statements for a time period is obtained, wherein the plurality of conditional statements are compiled in a first order during the execution. Based on the first number of times and the first order, a determination is made whether the plurality of conditional statements are to be reordered. In response to a determination that the plurality of conditional statements are to be reordered, a second order of the plurality of conditional statements is determined, wherein the second order being different from the first order. The plurality of conditional statements are then compiled in the second order.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wu Song Fang, Li Xiang, Yuan Li, Ren Fu Ma
  • Patent number: 11064056
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve interprocess communication. An example apparatus to improve network transmission efficiency of a sending peer includes a metadata engine to identify a reference element of a composite to a receiving peer, an annotation engine to identify configuration information of the reference element, a deep copy engine to extract an active portion of the reference element based on the configuration information, and a client payload engine to transmit the active portion of the reference element in a binary data format associated with transmission metadata.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Henrik Krogh Moeller, Amol Dhere
  • Patent number: 11036477
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve utilization of a heterogeneous system executing software. The disclosed methods, apparatus, systems and articles of manufacture include an apparatus comprising a variant manager to determine whether an algorithm is a candidate for sub-algorithmic partitioning (SAP) based on at least one of a first size of input data to the algorithm and a second size of output data from the algorithm; a partitioner to partition the algorithm into at least a first tile and a second tile; and a compiler to compile a first variant based on the first tile and a second variant based on the second tile into an executable file, the first variant to be executed on a first processing element of the heterogeneous system, the second variant to be executed on a second processing element of the heterogeneous system.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 15, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Justin Gottschlich
  • Patent number: 11016775
    Abstract: Techniques are disclosed for reordering operations of a neural network to improve runtime efficiency. In some examples, a compiler receives a description of the neural network comprising a plurality of operations. The compiler may determine which execution engine of a plurality of execution engines is to perform each of the plurality of operations. The compiler may determine an order of performance associated with the plurality of operations. The compiler may identify a runtime inefficiency based on the order of performance and a hardware usage for each of the plurality of operations. An operation may be reordered to reduce the runtime inefficiency. Instructions may be compiled based on the plurality of operations, which include the reordered operation.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey T. Huynh, Drazen Borkovic, Jindrich Zejda, Randy Renfu Huang, Ron Diamant
  • Patent number: 10949209
    Abstract: Examples described herein generally relate to generating, from a listing of source code, a plurality of basic blocks for compiling into intermediate language, determining, for a first basic block of the plurality of basic blocks, first heuristics related to applying a first plurality of optimizations to the first basic block, determining, for a second basic block of the plurality of basic blocks, second heuristics related to applying a second plurality of optimizations to the second basic block, and applying, based on the first heuristics and the second heuristics, one of the first plurality of optimizations to the first basic block to schedule first instructions for the first basic block and one of the second plurality of optimizations to the second basic block to schedule second instructions for the second basic block.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 16, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Xiang Li, Michael Alan Dougherty, David McCarthy Peixotto
  • Patent number: 10908884
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 10860298
    Abstract: A computer-implemented method for editing one or more properties of one or more model elements in a block diagram of a technical computing environment. The model elements include blocks and variables in blocks, wherein one or more properties are assigned to each model element. The technical computing environment has a model editor, a data definition tool and a code generator. A processor of a host computer opens a block diagram in the model editor, displays a list of model elements present in the block diagram, receives a selection of one or more model elements, highlights the selected model elements, receives an edit command to set a new value for a chosen property of the selected model elements, and sets the chosen property to the new value. A non-transitory computer readable medium and a computer system is also provided.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Torsten Pietzsch, Wolfgang Trautmann, Christian Witte
  • Patent number: 10853042
    Abstract: Methods and devices for generating program code representations may include receiving program code or edited program code for an application executing on the computer device. The methods and devices may include receiving an identification of a selected pipeline from a plurality of pipelines that defines a plurality of passes of actions to execute on the program code or the edited program code to optimize the program code or the edited program code. The methods and devices may include running the selected pipeline and generate optimizer output with a program code representation of the program code.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 1, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Marcelo Lopez Ruiz, Ivan Nevraev, David M. Peixotto, Xiang Li
  • Patent number: 10824538
    Abstract: A method may include generating, by performing a full analysis of code and for each component of the code, summaries including: a forward summary including a forward flow, and a backward summary including a backward flow, obtaining a modification to a modified component, determining that one of the summaries for the modified component is invalid, and in response to determining that a summary for the modified component is invalid: obtaining the forward flow from the forward summary of the modified component, obtaining the backward flow from the backward summary of the modified component, generating a local flow by performing an incremental analysis of the modified component using the forward flow of the modified component and the backward flow of the modified component, and detecting a defect in the code using the forward flow of the modified component, the local flow, and the backward flow of the modified component.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 3, 2020
    Assignee: Oracle International Corporation
    Inventors: Padmanabhan Krishnan, Rebecca Jane O'Donoghue, Nicholas John Allen, Yi Lu
  • Patent number: 10802806
    Abstract: A reconverging control flow graph is generated by receiving an input control flow graph including a plurality of basic code blocks, determining an order of the basic code blocks, and traversing the input control flow graph. The input control flow graph is traversed by, for each basic code block B of the plurality of basic code blocks, according to the determined order of the basic code blocks, visiting the basic code block B prior to visiting a subsequent block C of the plurality of basic code blocks, and based on determining that the basic code block B has a prior block A and that the prior block A has an open edge AC to the subsequent block C, in the reconverging control flow graph, creating an edge AF between the prior block A and a flow block F1, and creating an edge FC between the flow block F1 and the subsequent block C.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 13, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nicolai Haehnle
  • Patent number: 10795652
    Abstract: Disclosed herein are representative embodiments of tools and techniques for installing, executing, and/or updating managed applications through generation of native code from code in an intermediate language. According to one exemplary technique, a computing device receives machine dependent intermediate language code (MDIL code) generated by an online provider for an application. Additionally, the computing device installs the application on the computing device by generating a native image for the application, which includes binding a portion of the MDIL code with one or more libraries on the computing device. Also, the native image is stored on the computing device for use in loading the application for execution.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sameer Tejani, Adina Magdalena Trufinescu, Yasser Shaaban, Abolade Gbadegesin, Ashish Babbar, Mei-Chin Tsai, Subramanian Ramaswamy, Casimir Lakshan Fernando
  • Patent number: 10783193
    Abstract: A software service execution system includes: a software library storing software services, each obtaining and processing input data from a specified input URI (uniform resource identifier) and outputting the result to a specified output URI; a metadata graph representing the software services, each being identifiable by a predicate defining a relationship between a subject vertex and an object vertex, the subject vertex storing the specified input URI and being linked by a directed edge labelled with the predicate to the object vertex storing the specified output URI; a metadata graph query interface receiving a query requesting a queried vertex, linked by a defined traversal path along one or more edges to a source vertex; a software service execution controller controlling the execution of the software services identified by specified predicates labelling edges on the defined traversal path, in an order determined by the defined traversal path.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: September 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: José Mora López, Victor De La Torre, Masatomo Goto
  • Patent number: 10782943
    Abstract: A method and system encodes data objects and their metadata. An implementation provides a method and system for rewriting a program to encode metadata in the run-time environment of the program. An implementation provides a method for serializing a data object according to the encoding method and a method for deserializing a bit sequence that is generated by the serialization method.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 22, 2020
    Assignee: STENSAL, INC.
    Inventor: Ning Wang
  • Patent number: 10747517
    Abstract: An apparatus includes a processor to: receive a job flow definition; retrieve the most recent versions of a set of task routines for the defined job flow; translate, into an intermediate representation, executable instructions of each task routine implementing an interface for data input and/or output during execution; translate executable instructions of the job flow definition that defines the interface for each task routine into an intermediate representation; compare each intermediate representation from a task routine to the corresponding intermediate representation from the job flow definition to determine if there is a match; and in response to there being a match for each comparison and to the executable instructions of the job flow definition being written in a secondary programming language, translate the executable instructions of the job flow definition into a primary programming language, and store the resulting translated form of the job flow definition in a federated area.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: August 18, 2020
    Assignee: SAS INSTITUTE INC.
    Inventors: Henry Gabriel Victor Bequet, Kais Arfaoui
  • Patent number: 10657039
    Abstract: A control device for a motor vehicle, the control device including at least two processor cores and a global memory, each processor core respectively including a local memory and each processor core being set up to access only its own local memory and being set up to access neither the local memories of the other processor cores nor the global memory, a coordination unit being set up to read in data from the global memory of the control device and to write it to the local memories of the individual processor cores, and to read in data from the local memories of the individual processor cores and to write it to the global memory and/or to the local memory of the other processor cores.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: May 19, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Alexander Biewer, Dieter Thoss, Jens Gladigau, Christian Haubelt
  • Patent number: 10552185
    Abstract: A profiling implementation method for reducing overhead while an application is running with profiling instrumentation inserted but disabled; the method for gathering precise profiling data for a subset of observed values at runtime start; generating an index for each observed value; populating one or more data structures within a hash table with the subset of observed values to count; comparing a corresponding key at the index value of an observed value index; evaluating a value limit of the hash table; incrementing a matched key counter; incrementing an alt-counter; locking the hash table; and updating one or more data structures of the hash table.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Craik, Joseph Devin Micheal Papineau, Nicholas J. Coughlin
  • Patent number: 10540334
    Abstract: A code generator platform may receive source metadata and a target data model. The code generator platform may determine a parameter, of the target data model, that is associated with the attribute. The code generator platform may map, based on the attribute and the source metadata, the data to the parameter of the target data model. The code generator platform may generate, based on mapping the data to the parameter, data transformation code associated with the data and the target data model, wherein the data transformation code, when executed, generates target data that corresponds to the data according to the target data model. The code generator platform may perform an action associated with the data transformation code to permit the data transformation code to be executed in order to update a target database with the target data.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 21, 2020
    Assignee: Capital One Services, LLC
    Inventors: Manigandan Eswaran, Surya Ram Hareesh Vemula, Ramesh Babu Singamsetty, Pratap Kumar Mittapally, Gauri Kelkar, SaiPriya Rayala, Vibha Mohan, Alagushankar Sathasivam
  • Patent number: 10530964
    Abstract: An image forming apparatus includes: a hardware processor that: generates image data for composition; and divides the image data for composition into bands; an output memory; a storage that determines whether image data of each band coincides with image data of another band, secures a unique region, transfers the image data of the band to the unique region and associates the band with the unique region, secures common regions, transfers the image data of one of the bands to the common region and associates any one of the common regions to each of the bands; a reader that reads the image data from the region associated with each band and outputs the image data for composition; a composer that composes the image data for composition with the image data to be printed; and an image former that forms an image based on the composed image data.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 7, 2020
    Assignee: Konica Minolta, Inc.
    Inventor: Takenori Idehara
  • Patent number: 10481950
    Abstract: A method is provided for operating a communication device offering a plurality of features by a plurality of virtual machines, which run on a virtualized representation of a plurality of hardware components. The method includes: obtaining a mapping between at least some features of the plurality of features and corresponding sets of virtual machines of the plurality of virtual machines and hardware components of the plurality of hardware components which are required to enable the features; and upon deciding to activate or deactivate at least one group of features of the plurality of features, switching on or off virtual machines of the plurality of virtual machines and hardware components of the plurality of hardware components depending on the mapping.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: November 19, 2019
    Assignee: ORANGE
    Inventors: Louis-Marie Le Saux, Lorenzo Saino, Elise Vennegues
  • Patent number: 10481883
    Abstract: An information processor including a memory; and a processor coupled to the memory and method thereof. The processor is configured to store first identification information of a first source file corresponding to an object file that is not linked, judge whether second identification information of a second source file specified as a target of compilation is stored in the memory, and generate an object file through compilation on a third source file where the second identification information of the second source file is stored in the memory. The processor is also configured to perform inter-file optimization on the second source file and the third source file to generate a plurality of intermediate files and generate a plurality of object files through compilation on the plurality of generated intermediate files.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kuninori Ishii, Toshihiro Suzuki, Naoki Sueyasu
  • Patent number: 10467001
    Abstract: Technology is disclosed herein for compressing, encoding, and otherwise reducing the size of resource files. In at least one implementation, similarity compression is employed to reduce the size of a resource file. In another implementation, map-less encoding is employed to reduce the number of bytes used to represent a resource string. Bit-level compression is employed in another implementation to reduce the quantity of bits used to encode each character in a string. In addition, implementations are disclosed related to technology for naming strings and accelerated string location and retrieval.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Anatoliy Burukhin, Thomas Gary Moore, Thomas Jeffrey Lavoy, Rory Keary
  • Patent number: 10453167
    Abstract: A computer-implemented method is provided for estimating the performance of a GPU application on a new computing machine having an increased GPU-link performance ratio relative to a current computing machine having a current GPU-link performance ratio. The method includes adding a delay to CPU-GPU communication on the current computing machine to simulate a delayed-communication environment on the current computing machine. The method further includes executing the target GPU application in the delayed-communication environment. The method also includes measuring the performance of the target GPU application in the delayed-communication environment. The method additionally includes estimating the performance of the new computing machine having the increased higher GPU-link performance ratio, based on the measured performance of the target GPU application in the delayed-communication environment.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiyokuni Kawachiya, Yasushi Negishi, Jun Doi