Including Intermediate Code Patents (Class 717/146)
  • Patent number: 11106434
    Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for generating program code. In one embodiment, a method for generating program code is disclosed, including: acquiring code configuration information that includes code function information indicating a target function and device configuration information of a target device; and generating program code based on the code configuration information, wherein when executed, the program code can cause the target device to implement the target function. Through the embodiments of the present disclosure, the diversity and flexibility of function implementation can be improved, and the workload of developing program code can be significantly reduced.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 31, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jinpeng Liu, Jin Li, Jiacheng Ni, Danqing Sha
  • Patent number: 11093229
    Abstract: A failure rate model modeling a failure rate of a training functionality deployment in a training set of functionality deployments is constructed. The failure rate model is configured to receive functionality deployment data and output a corresponding failure rate prediction. Using the failure rate model, a set of functionality deployment failure rates is predicted, a functionality deployment failure rate in the set of functionality deployment failure rates corresponding to an upcoming functionality deployment. Using the set of functionality deployment failure rates, a deployment sequence of the set of upcoming functionality deployments is constructed to minimize a predicted overall failure rate of the set of upcoming functionality deployments. The deployment of each functionality deployment in the set of upcoming functionality deployments is caused, the deployment comprising activating the upcoming functionality program code according to the deployment sequence.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pranshu Tiwari, Harish Bharti, Naveen Narayanaswamy, Ram Prasad Reddy Munagala
  • Patent number: 11082438
    Abstract: Techniques are provided herein for contextual embedding of features of operational logs or network traffic for anomaly detection based on sequence prediction. In an embodiment, a computer has a predictive recurrent neural network (RNN) that detects an anomalous network flow. In an embodiment, an RNN contextually transcodes sparse feature vectors that represent log messages into dense feature vectors that may be predictive or used to generate predictive vectors. In an embodiment, graph embedding improves feature embedding of log traces. In an embodiment, a computer detects and feature-encodes independent traces from related log messages. These techniques may detect malicious activity by anomaly analysis of context-aware feature embeddings of network packet flows, log messages, and/or log traces.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: August 3, 2021
    Assignee: Oracle International Corporation
    Inventors: Juan Fernandez Peinador, Manel Fernandez Gomez, Guang-Tong Zhou, Hossein Hajimirsadeghi, Andrew Brownsword, Onur Kocberber, Felix Schmidt, Craig Schelp
  • Patent number: 11061653
    Abstract: Implementations of the present disclosure relate a method, system and computer program products that dynamically compile conditional statements. According to the method, a first number of times that a first conditional statement of a plurality of conditional statements has been satisfied during execution of the plurality of conditional statements for a time period is obtained, wherein the plurality of conditional statements are compiled in a first order during the execution. Based on the first number of times and the first order, a determination is made whether the plurality of conditional statements are to be reordered. In response to a determination that the plurality of conditional statements are to be reordered, a second order of the plurality of conditional statements is determined, wherein the second order being different from the first order. The plurality of conditional statements are then compiled in the second order.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wu Song Fang, Li Xiang, Yuan Li, Ren Fu Ma
  • Patent number: 11064056
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve interprocess communication. An example apparatus to improve network transmission efficiency of a sending peer includes a metadata engine to identify a reference element of a composite to a receiving peer, an annotation engine to identify configuration information of the reference element, a deep copy engine to extract an active portion of the reference element based on the configuration information, and a client payload engine to transmit the active portion of the reference element in a binary data format associated with transmission metadata.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Henrik Krogh Moeller, Amol Dhere
  • Patent number: 11036477
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed improve utilization of a heterogeneous system executing software. The disclosed methods, apparatus, systems and articles of manufacture include an apparatus comprising a variant manager to determine whether an algorithm is a candidate for sub-algorithmic partitioning (SAP) based on at least one of a first size of input data to the algorithm and a second size of output data from the algorithm; a partitioner to partition the algorithm into at least a first tile and a second tile; and a compiler to compile a first variant based on the first tile and a second variant based on the second tile into an executable file, the first variant to be executed on a first processing element of the heterogeneous system, the second variant to be executed on a second processing element of the heterogeneous system.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 15, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Sridhar Sharma, Mikael Bourges-Sevenier, Justin Gottschlich
  • Patent number: 11016775
    Abstract: Techniques are disclosed for reordering operations of a neural network to improve runtime efficiency. In some examples, a compiler receives a description of the neural network comprising a plurality of operations. The compiler may determine which execution engine of a plurality of execution engines is to perform each of the plurality of operations. The compiler may determine an order of performance associated with the plurality of operations. The compiler may identify a runtime inefficiency based on the order of performance and a hardware usage for each of the plurality of operations. An operation may be reordered to reduce the runtime inefficiency. Instructions may be compiled based on the plurality of operations, which include the reordered operation.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 25, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Jeffrey T. Huynh, Drazen Borkovic, Jindrich Zejda, Randy Renfu Huang, Ron Diamant
  • Patent number: 10949209
    Abstract: Examples described herein generally relate to generating, from a listing of source code, a plurality of basic blocks for compiling into intermediate language, determining, for a first basic block of the plurality of basic blocks, first heuristics related to applying a first plurality of optimizations to the first basic block, determining, for a second basic block of the plurality of basic blocks, second heuristics related to applying a second plurality of optimizations to the second basic block, and applying, based on the first heuristics and the second heuristics, one of the first plurality of optimizations to the first basic block to schedule first instructions for the first basic block and one of the second plurality of optimizations to the second basic block to schedule second instructions for the second basic block.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 16, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Xiang Li, Michael Alan Dougherty, David McCarthy Peixotto
  • Patent number: 10908884
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: February 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Adam Herr, Derek Gerstmann, Justin Gottschlich, Mikael Bourges-Sevenier, Sridhar Sharma
  • Patent number: 10860298
    Abstract: A computer-implemented method for editing one or more properties of one or more model elements in a block diagram of a technical computing environment. The model elements include blocks and variables in blocks, wherein one or more properties are assigned to each model element. The technical computing environment has a model editor, a data definition tool and a code generator. A processor of a host computer opens a block diagram in the model editor, displays a list of model elements present in the block diagram, receives a selection of one or more model elements, highlights the selected model elements, receives an edit command to set a new value for a chosen property of the selected model elements, and sets the chosen property to the new value. A non-transitory computer readable medium and a computer system is also provided.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: December 8, 2020
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Torsten Pietzsch, Wolfgang Trautmann, Christian Witte
  • Patent number: 10853042
    Abstract: Methods and devices for generating program code representations may include receiving program code or edited program code for an application executing on the computer device. The methods and devices may include receiving an identification of a selected pipeline from a plurality of pipelines that defines a plurality of passes of actions to execute on the program code or the edited program code to optimize the program code or the edited program code. The methods and devices may include running the selected pipeline and generate optimizer output with a program code representation of the program code.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 1, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Marcelo Lopez Ruiz, Ivan Nevraev, David M. Peixotto, Xiang Li
  • Patent number: 10824538
    Abstract: A method may include generating, by performing a full analysis of code and for each component of the code, summaries including: a forward summary including a forward flow, and a backward summary including a backward flow, obtaining a modification to a modified component, determining that one of the summaries for the modified component is invalid, and in response to determining that a summary for the modified component is invalid: obtaining the forward flow from the forward summary of the modified component, obtaining the backward flow from the backward summary of the modified component, generating a local flow by performing an incremental analysis of the modified component using the forward flow of the modified component and the backward flow of the modified component, and detecting a defect in the code using the forward flow of the modified component, the local flow, and the backward flow of the modified component.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 3, 2020
    Assignee: Oracle International Corporation
    Inventors: Padmanabhan Krishnan, Rebecca Jane O'Donoghue, Nicholas John Allen, Yi Lu
  • Patent number: 10802806
    Abstract: A reconverging control flow graph is generated by receiving an input control flow graph including a plurality of basic code blocks, determining an order of the basic code blocks, and traversing the input control flow graph. The input control flow graph is traversed by, for each basic code block B of the plurality of basic code blocks, according to the determined order of the basic code blocks, visiting the basic code block B prior to visiting a subsequent block C of the plurality of basic code blocks, and based on determining that the basic code block B has a prior block A and that the prior block A has an open edge AC to the subsequent block C, in the reconverging control flow graph, creating an edge AF between the prior block A and a flow block F1, and creating an edge FC between the flow block F1 and the subsequent block C.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 13, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nicolai Haehnle
  • Patent number: 10795652
    Abstract: Disclosed herein are representative embodiments of tools and techniques for installing, executing, and/or updating managed applications through generation of native code from code in an intermediate language. According to one exemplary technique, a computing device receives machine dependent intermediate language code (MDIL code) generated by an online provider for an application. Additionally, the computing device installs the application on the computing device by generating a native image for the application, which includes binding a portion of the MDIL code with one or more libraries on the computing device. Also, the native image is stored on the computing device for use in loading the application for execution.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 6, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sameer Tejani, Adina Magdalena Trufinescu, Yasser Shaaban, Abolade Gbadegesin, Ashish Babbar, Mei-Chin Tsai, Subramanian Ramaswamy, Casimir Lakshan Fernando
  • Patent number: 10782943
    Abstract: A method and system encodes data objects and their metadata. An implementation provides a method and system for rewriting a program to encode metadata in the run-time environment of the program. An implementation provides a method for serializing a data object according to the encoding method and a method for deserializing a bit sequence that is generated by the serialization method.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: September 22, 2020
    Assignee: STENSAL, INC.
    Inventor: Ning Wang
  • Patent number: 10783193
    Abstract: A software service execution system includes: a software library storing software services, each obtaining and processing input data from a specified input URI (uniform resource identifier) and outputting the result to a specified output URI; a metadata graph representing the software services, each being identifiable by a predicate defining a relationship between a subject vertex and an object vertex, the subject vertex storing the specified input URI and being linked by a directed edge labelled with the predicate to the object vertex storing the specified output URI; a metadata graph query interface receiving a query requesting a queried vertex, linked by a defined traversal path along one or more edges to a source vertex; a software service execution controller controlling the execution of the software services identified by specified predicates labelling edges on the defined traversal path, in an order determined by the defined traversal path.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: September 22, 2020
    Assignee: FUJITSU LIMITED
    Inventors: José Mora López, Victor De La Torre, Masatomo Goto
  • Patent number: 10747517
    Abstract: An apparatus includes a processor to: receive a job flow definition; retrieve the most recent versions of a set of task routines for the defined job flow; translate, into an intermediate representation, executable instructions of each task routine implementing an interface for data input and/or output during execution; translate executable instructions of the job flow definition that defines the interface for each task routine into an intermediate representation; compare each intermediate representation from a task routine to the corresponding intermediate representation from the job flow definition to determine if there is a match; and in response to there being a match for each comparison and to the executable instructions of the job flow definition being written in a secondary programming language, translate the executable instructions of the job flow definition into a primary programming language, and store the resulting translated form of the job flow definition in a federated area.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: August 18, 2020
    Assignee: SAS INSTITUTE INC.
    Inventors: Henry Gabriel Victor Bequet, Kais Arfaoui
  • Patent number: 10657039
    Abstract: A control device for a motor vehicle, the control device including at least two processor cores and a global memory, each processor core respectively including a local memory and each processor core being set up to access only its own local memory and being set up to access neither the local memories of the other processor cores nor the global memory, a coordination unit being set up to read in data from the global memory of the control device and to write it to the local memories of the individual processor cores, and to read in data from the local memories of the individual processor cores and to write it to the global memory and/or to the local memory of the other processor cores.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: May 19, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Alexander Biewer, Dieter Thoss, Jens Gladigau, Christian Haubelt
  • Patent number: 10552185
    Abstract: A profiling implementation method for reducing overhead while an application is running with profiling instrumentation inserted but disabled; the method for gathering precise profiling data for a subset of observed values at runtime start; generating an index for each observed value; populating one or more data structures within a hash table with the subset of observed values to count; comparing a corresponding key at the index value of an observed value index; evaluating a value limit of the hash table; incrementing a matched key counter; incrementing an alt-counter; locking the hash table; and updating one or more data structures of the hash table.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Craik, Joseph Devin Micheal Papineau, Nicholas J. Coughlin
  • Patent number: 10540334
    Abstract: A code generator platform may receive source metadata and a target data model. The code generator platform may determine a parameter, of the target data model, that is associated with the attribute. The code generator platform may map, based on the attribute and the source metadata, the data to the parameter of the target data model. The code generator platform may generate, based on mapping the data to the parameter, data transformation code associated with the data and the target data model, wherein the data transformation code, when executed, generates target data that corresponds to the data according to the target data model. The code generator platform may perform an action associated with the data transformation code to permit the data transformation code to be executed in order to update a target database with the target data.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 21, 2020
    Assignee: Capital One Services, LLC
    Inventors: Manigandan Eswaran, Surya Ram Hareesh Vemula, Ramesh Babu Singamsetty, Pratap Kumar Mittapally, Gauri Kelkar, SaiPriya Rayala, Vibha Mohan, Alagushankar Sathasivam
  • Patent number: 10530964
    Abstract: An image forming apparatus includes: a hardware processor that: generates image data for composition; and divides the image data for composition into bands; an output memory; a storage that determines whether image data of each band coincides with image data of another band, secures a unique region, transfers the image data of the band to the unique region and associates the band with the unique region, secures common regions, transfers the image data of one of the bands to the common region and associates any one of the common regions to each of the bands; a reader that reads the image data from the region associated with each band and outputs the image data for composition; a composer that composes the image data for composition with the image data to be printed; and an image former that forms an image based on the composed image data.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: January 7, 2020
    Assignee: Konica Minolta, Inc.
    Inventor: Takenori Idehara
  • Patent number: 10481950
    Abstract: A method is provided for operating a communication device offering a plurality of features by a plurality of virtual machines, which run on a virtualized representation of a plurality of hardware components. The method includes: obtaining a mapping between at least some features of the plurality of features and corresponding sets of virtual machines of the plurality of virtual machines and hardware components of the plurality of hardware components which are required to enable the features; and upon deciding to activate or deactivate at least one group of features of the plurality of features, switching on or off virtual machines of the plurality of virtual machines and hardware components of the plurality of hardware components depending on the mapping.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: November 19, 2019
    Assignee: ORANGE
    Inventors: Louis-Marie Le Saux, Lorenzo Saino, Elise Vennegues
  • Patent number: 10481883
    Abstract: An information processor including a memory; and a processor coupled to the memory and method thereof. The processor is configured to store first identification information of a first source file corresponding to an object file that is not linked, judge whether second identification information of a second source file specified as a target of compilation is stored in the memory, and generate an object file through compilation on a third source file where the second identification information of the second source file is stored in the memory. The processor is also configured to perform inter-file optimization on the second source file and the third source file to generate a plurality of intermediate files and generate a plurality of object files through compilation on the plurality of generated intermediate files.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kuninori Ishii, Toshihiro Suzuki, Naoki Sueyasu
  • Patent number: 10467001
    Abstract: Technology is disclosed herein for compressing, encoding, and otherwise reducing the size of resource files. In at least one implementation, similarity compression is employed to reduce the size of a resource file. In another implementation, map-less encoding is employed to reduce the number of bytes used to represent a resource string. Bit-level compression is employed in another implementation to reduce the quantity of bits used to encode each character in a string. In addition, implementations are disclosed related to technology for naming strings and accelerated string location and retrieval.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: November 5, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Anatoliy Burukhin, Thomas Gary Moore, Thomas Jeffrey Lavoy, Rory Keary
  • Patent number: 10452367
    Abstract: Improving how a codebase is developed by analyzing the variables in the codebase's source code. Learned characteristics of a codebase are derived by obtaining context for some of the source code's variables. This context represents semantics and/or patterns associated with those variables. Once the learned characteristics are derived, they are then modified, or rather tuned, by incorporating context from second source code. Particular context for a particular variable used within the second source code is then obtained. This particular context represents semantics and/or patterns associated with the particular variable. This particular context is then analyzed using the learned characteristics to generate zero, one or more anticipated variables. Later, a notification regarding these anticipated variables is displayed. In some situations, conducting the analysis is a part of a variable renaming analysis while in other situation the analysis is a part of a variable misuse analysis.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Miltiadis Allamanis, Marc Manuel Johannes Brockschmidt
  • Patent number: 10453167
    Abstract: A computer-implemented method is provided for estimating the performance of a GPU application on a new computing machine having an increased GPU-link performance ratio relative to a current computing machine having a current GPU-link performance ratio. The method includes adding a delay to CPU-GPU communication on the current computing machine to simulate a delayed-communication environment on the current computing machine. The method further includes executing the target GPU application in the delayed-communication environment. The method also includes measuring the performance of the target GPU application in the delayed-communication environment. The method additionally includes estimating the performance of the new computing machine having the increased higher GPU-link performance ratio, based on the measured performance of the target GPU application in the delayed-communication environment.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: October 22, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kiyokuni Kawachiya, Yasushi Negishi, Jun Doi
  • Patent number: 10430182
    Abstract: Technology is disclosed herein for compressing, encoding, and otherwise reducing the size of resource files. In at least one implementation, similarity compression is employed to reduce the size of a resource file. In another implementation, map-less encoding is employed to reduce the number of bytes used to represent a resource string. Bit-level compression is employed in another implementation to reduce the quantity of bits used to encode each character in a string. In addition, implementations are disclosed related to technology for naming strings and accelerated string location and retrieval.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: October 1, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Anatoliy Burukhin, Thomas Gary Moore, Thomas Jeffrey Lavoy, Rory Keary
  • Patent number: 10409574
    Abstract: Methods, systems, and computer program products are provided that enable incremental compilation of source code. Attributes of an intermediate language (IL) representation and a compiled representation of a source code are stored. Modified source code that is a revised version of the first source code is received. An IL representation of the modified source code is generated. Attributes of the revised intermediate IL and the stored attributes of the IL representation are compared to determine a first set of functions changed in the modified source code. A second set of functions in the first source code is determined that includes functions affected the determined first set of functions. The first and second sets of functions are compiled to generate a set of compiled functions. Compiled versions of the first and second sets are replaced in the compiled representation of the first source code with the set of compiled functions.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 10, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Patrick W. Sathyanathan, Ten H. Tzen, Wenlei He, Ankit Asthana, Adrian Militaru
  • Patent number: 10403025
    Abstract: There is provided a method of a graphics processing system, the method including receiving dependency information for a set of interdependent images indicating a dependency across one or more compute shader and graphics workloads, and interleaving processing of the compute shader and graphics workloads for the set of interdependent images in accordance with the dependency information without recompiling a compute shader generating the one or more compute shader workloads.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abhinav Golas, Michael Fertig
  • Patent number: 10387493
    Abstract: The present invention provides a method and system for converting an XML artifact into a Topic Map instance. The method includes consolidating, by a schema consolidation module, an XML schema of the XML artifact; extracting, by an extracting module, a topic map model from the consolidated XML schema; and generating, by a converter, the topic map instance from the topic map model and the xml artifact.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: August 20, 2019
    Assignee: Infosys Limited
    Inventors: Suman Roy, Kiran Prakash Sawant, Olivier Charvin
  • Patent number: 10372467
    Abstract: An information processing apparatus that performs a program installation includes a determiner and a display controller. The determiner determines whether or not a manner of installation in which the installation is performed corresponds to an update installation that updates a first program previously installed with a second program to be installed at this time. When the manner of installation corresponds to the update installation, the display controller selects a first display setting for causing a predetermined display unit to display a first user interface screen corresponding to the first program. When the manner of installation does not correspond to the update installation, the display controller selects a second display setting for causing the display unit to display a second user interface screen corresponding to the second program.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: August 6, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yamada, Kazuki Tadachi
  • Patent number: 10365906
    Abstract: Provided is a compile time interface to run-time libraries that can reduce processing overhead in loops. A compile time interface identifies, at compile time, a loop that contains a library function in response to detecting a compiler hint associated with the library function. The compile time interface generates a bypass structure and modifies the loop to include a call to a planning function for a first pass through the loop and a call to a bypass function for one or more subsequent passes though the loop. The planning function sets the bypass function equal to an optimized library if one or more selected arguments to the library function are loop-invariant.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Dmitry G. Baksheev, Gregory M. Henry
  • Patent number: 10356178
    Abstract: A method of synchronizing data for algorithms of asynchronous computers in an aircraft, the method comprising the steps consisting in: a) generating a sequencing table for each algorithm and, in said table, identifying the number of valid windows for each of which all of the parameters for input to the algorithm are updated at least once; b) distributing the load corresponding to updating the parameters for each algorithm in a send table; and c) instructing the first computer to use the send table.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 16, 2019
    Assignee: Safran Aircraft Engines
    Inventor: Jean Pasquie
  • Patent number: 10338903
    Abstract: A method for analyzing a program may include generating an initial control flow graph (CFG) for the program, identifying merge blocks of the initial CFG, identifying predecessor-merge pairs based on identifying predecessor blocks for each merge block, simulating a duplication of each predecessor-merge pair, determining whether the duplication satisfies a precondition of each of a collection of optimizations, applying, in response to satisfying the precondition, the optimization to the duplication, and generating a simulation result for the predecessor-merge pair corresponding to the duplication. The simulation result may include the optimization and a benefit of applying the optimization to the duplication. The method may further include duplicating, in the initial CFG, a predecessor-merge pair based on the simulation result corresponding to the predecessor-merge pair.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: David Leopoldseder, Thomas Wuerthinger, Lukas Stadler
  • Patent number: 10331836
    Abstract: Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventors: Anup Hosangadi, Sumanta Datta, Aman Gayasen, Ashish Sirasao
  • Patent number: 10325031
    Abstract: Embodiments of methods and/or systems of manipulating tree expressions are disclosed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: June 18, 2019
    Assignee: Robert T. and Virginia T. Jenkins as Trustees of the Jenkins Family Trust dated Feb. 8, 2002
    Inventor: Jack J. LeTourneau
  • Patent number: 10310969
    Abstract: The present disclosure generally relates to predicting automated software tests for testing units of work delivery in a continuous integration development environment. More particularly, the present disclosure relates to systems and methods for improving the efficiency of code integration by predicting a subset of automated software tests from amongst a set of all available automated software tests, thereby improving testing time and reducing processing loads.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Oracle International Corporation
    Inventors: Abhijit Bhattacharjee, Manoj Dash
  • Patent number: 10268497
    Abstract: Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Hongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu
  • Patent number: 10262438
    Abstract: The representation of content, in a scene representation, is enriched with a view to the adaptive use of the latter according to a set of common parameters. A sub-graph of the scene graph, which is susceptible to variable processing, is identified. For this purpose, two new types of scene element can be defined, one of which allows the identification of the sub-graph and the second enables application of the set of common parameters in relation to the sub-graph. An example of the first type is a node of so-called “AdaptivityControl” type which encompasses the entire sub-graph, a list of the nodes describing the set of common parameters and a group of fields for dynamic updating of the content of this node. An example of the second type is a node of so-called “CompressedImageStrategy” type which comprises information relating to the object to be coded and the coding parameters.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 16, 2019
    Assignees: PROLOGUE, ASSOC. POUR LA RECHERCHE ET LE DEVELOPPEMENT DE METHODES ET PROCESSUS INDUSTRIELS “ARMINES”, INSTITUT MINES-TELECOM
    Inventors: Mihai Petru Mitrea, Bojan Joveski, Ludovico Gardenghi, Iain James Marshall, Francoise Preteux
  • Patent number: 10248545
    Abstract: A method for tracking high-level source attribution of a generated assembly language code includes: receiving commands for compiling or linking a high-level language code; analyzing the received commands to determine whether a command is a compiler command for compiling the high-level language code or a link command for linking the low level object code; when the command is a compiler command: generating assembly language code by compiling the high-level language code, parsing the generated assembly language code to generate an internal representation for the assembly language code, storing the internal representation in a computer memory; and generating associated linker input artifacts for linking; when the command is a link command: updating the internal representation with the associated linker input artifacts; and generating a report file from the updated internal representation.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 2, 2019
    Assignee: PARASOFT CORPORATION
    Inventors: Daniel J. Dominguez, Joshua William Scoggins, Richard Kent Newman, Uwe Samitsch Kronholm
  • Patent number: 10228919
    Abstract: One embodiment of the present invention sets forth a technique for reducing sign-extension instructions (SEIs) included in a computer program, the technique involves receiving intermediate code that is associated with the computer program and includes a first SEI that is included in a loop structure within the computer program, determining that the first SEI is eligible to be moved outside of the loop structure, inserting into a preheader of the loop a second SEI that, when executed by a processor, promotes an original value targeted by the first SEI from a smaller type to a larger type, and replacing the first SEI with one or more intermediate instructions that are eligible for additional compiler optimizations.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 12, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Akella Sastry, Yuan Lin
  • Patent number: 10223291
    Abstract: A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed.
    Type: Grant
    Filed: May 15, 2010
    Date of Patent: March 5, 2019
    Assignee: NXP B.V.
    Inventors: Ernst Haselsteiner, Christian Kirchstaetter
  • Patent number: 10198580
    Abstract: A process transforms compiled software into a semantic form. The process transforms the code into a semantic form. The process analyzes behavior functionality by processing precise programming behavior abstractions stored in a memory and classifies the code as malware based on the code behavior. Another method identifies the starting point of execution of a compiled program. The method calculates a complexity measure by calculating the number of potential execution paths of local functions; identifies the number of arguments passed to local functions; and identifies the starting point of execution of the compiled program. Another method provides interactive, dynamic visualization of a group of related functions wherein a user can explore the rendered graph and select a specific function and display functions that are color coded by their ancestral relation and their function call distance to the selected function.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 5, 2019
    Assignee: UT-BATTELLE, LLC
    Inventors: Kirk D. Sayre, Richard A. Willems, Stephen Lanse Lindberg
  • Patent number: 10191725
    Abstract: Disclosed are ways to flexibly arrange, rearrange, and execute optimization modules for program code in user-customizable sequences. In various embodiments, computer programmers can select an order of multiple standalone optimizers that each perform an optimization function on program code, forming a pipeline of a series of optimization modules. The pipeline can be modified by, for example, adding, removing, rearranging, repeating, and/or replacing optimization modules.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 29, 2019
    Assignee: Facebook, Inc.
    Inventors: Shane Roland Nay, Bertrand Allen Maher
  • Patent number: 10175963
    Abstract: A method is provided for executing a code sequence on a security module. The code sequence comprises codes to be replaced and codes to be interpreted. A temporary replacement takes place of a respective code to be replaced by a partial code sequence that comprises at least one code having an interpretable code value. The replacement taking place is dependent on the code value of the code to be replaced. An interpretation of the codes to be interpreted in the code sequence and in the partial code sequence takes place with the aid of interpretation information for code values. During the replacement step, the partial code sequence for the code value of the code to be replaced is additionally produced in dependence on a piece of selection information.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: January 8, 2019
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY GMBH
    Inventors: Deepen Mantri, Jörn Treger, Christian Dönges
  • Patent number: 10157062
    Abstract: A method is described for operating a microprocessor, in which a conversion software executed in the microprocessor carries out a binary translation, in the course of which a source instruction that is encoded according to a first instruction-set architecture is translated into a target instruction in a binary manner, which is encoded according to a second instruction-set architecture, and the target instruction translated by the translation software into the second instruction-set architecture being replicated, and in this replicated target instruction a memory area which is to be accessed in the course of the execution of the target instruction is replaced by a second memory area, and the target instruction and the copied target instruction is executed by the microprocessor.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 18, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Jaroslaw Topp
  • Patent number: 10152408
    Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 11, 2018
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Craig E. Hampel
  • Patent number: 10152310
    Abstract: A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 11, 2018
    Assignee: Nvidia Corporation
    Inventors: Mahesh Ravishankar, Paulius Micikevicius, Vinod Grover
  • Patent number: 10120664
    Abstract: A computer-implemented method includes receiving a set of complete source instructions to process a source code entity, an incremental build part, and a set of file definitions. The method analyzes the set of complete source instructions. The method identifies, from the set of analyzed source instructions, a set of operations that reference the incremental build subset. The method repeats: (i) determining, for each operation, whether any additional files are affected by the operation, the additional files forming a set of affected files; (ii) creating a combined set of files, the combined set of files consisting of the set of affected files and the incremental build subset; and (iii) updating the set of operations to include those from the analyzed source instructions that reference the combined set of files; until no new files are added to the combined set of files. The method generates a set of incremental source instructions.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Fulton, Gary I. Mazo, Brian W. Svihovec
  • Patent number: 10114877
    Abstract: Certain aspects of the present disclosure relate to a technique to access a data source from a client using a driver. A data source name (DSN) is provided to connect to the data source using the driver. The driver is used to interface between the client and an implementation of a driver interface to access the data source based on the DSN.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Open Invention Network LLC
    Inventor: Marc Todd Yaeger