Abstract: An information processor including a memory; and a processor coupled to the memory and method thereof. The processor is configured to store first identification information of a first source file corresponding to an object file that is not linked, judge whether second identification information of a second source file specified as a target of compilation is stored in the memory, and generate an object file through compilation on a third source file where the second identification information of the second source file is stored in the memory. The processor is also configured to perform inter-file optimization on the second source file and the third source file to generate a plurality of intermediate files and generate a plurality of object files through compilation on the plurality of generated intermediate files.

Abstract: Technology is disclosed herein for compressing, encoding, and otherwise reducing the size of resource files. In at least one implementation, similarity compression is employed to reduce the size of a resource file. In another implementation, map-less encoding is employed to reduce the number of bytes used to represent a resource string. Bit-level compression is employed in another implementation to reduce the quantity of bits used to encode each character in a string. In addition, implementations are disclosed related to technology for naming strings and accelerated string location and retrieval.

Abstract: A computer-implemented method is provided for estimating the performance of a GPU application on a new computing machine having an increased GPU-link performance ratio relative to a current computing machine having a current GPU-link performance ratio. The method includes adding a delay to CPU-GPU communication on the current computing machine to simulate a delayed-communication environment on the current computing machine. The method further includes executing the target GPU application in the delayed-communication environment. The method also includes measuring the performance of the target GPU application in the delayed-communication environment. The method additionally includes estimating the performance of the new computing machine having the increased higher GPU-link performance ratio, based on the measured performance of the target GPU application in the delayed-communication environment.

Abstract: Improving how a codebase is developed by analyzing the variables in the codebase's source code. Learned characteristics of a codebase are derived by obtaining context for some of the source code's variables. This context represents semantics and/or patterns associated with those variables. Once the learned characteristics are derived, they are then modified, or rather tuned, by incorporating context from second source code. Particular context for a particular variable used within the second source code is then obtained. This particular context represents semantics and/or patterns associated with the particular variable. This particular context is then analyzed using the learned characteristics to generate zero, one or more anticipated variables. Later, a notification regarding these anticipated variables is displayed. In some situations, conducting the analysis is a part of a variable renaming analysis while in other situation the analysis is a part of a variable misuse analysis.

Abstract: Technology is disclosed herein for compressing, encoding, and otherwise reducing the size of resource files. In at least one implementation, similarity compression is employed to reduce the size of a resource file. In another implementation, map-less encoding is employed to reduce the number of bytes used to represent a resource string. Bit-level compression is employed in another implementation to reduce the quantity of bits used to encode each character in a string. In addition, implementations are disclosed related to technology for naming strings and accelerated string location and retrieval.

Abstract: Methods, systems, and computer program products are provided that enable incremental compilation of source code. Attributes of an intermediate language (IL) representation and a compiled representation of a source code are stored. Modified source code that is a revised version of the first source code is received. An IL representation of the modified source code is generated. Attributes of the revised intermediate IL and the stored attributes of the IL representation are compared to determine a first set of functions changed in the modified source code. A second set of functions in the first source code is determined that includes functions affected the determined first set of functions. The first and second sets of functions are compiled to generate a set of compiled functions. Compiled versions of the first and second sets are replaced in the compiled representation of the first source code with the set of compiled functions.

Abstract: There is provided a method of a graphics processing system, the method including receiving dependency information for a set of interdependent images indicating a dependency across one or more compute shader and graphics workloads, and interleaving processing of the compute shader and graphics workloads for the set of interdependent images in accordance with the dependency information without recompiling a compute shader generating the one or more compute shader workloads.

Abstract: The present invention provides a method and system for converting an XML artifact into a Topic Map instance. The method includes consolidating, by a schema consolidation module, an XML schema of the XML artifact; extracting, by an extracting module, a topic map model from the consolidated XML schema; and generating, by a converter, the topic map instance from the topic map model and the xml artifact.

Abstract: An information processing apparatus that performs a program installation includes a determiner and a display controller. The determiner determines whether or not a manner of installation in which the installation is performed corresponds to an update installation that updates a first program previously installed with a second program to be installed at this time. When the manner of installation corresponds to the update installation, the display controller selects a first display setting for causing a predetermined display unit to display a first user interface screen corresponding to the first program. When the manner of installation does not correspond to the update installation, the display controller selects a second display setting for causing the display unit to display a second user interface screen corresponding to the second program.

Abstract: Provided is a compile time interface to run-time libraries that can reduce processing overhead in loops. A compile time interface identifies, at compile time, a loop that contains a library function in response to detecting a compiler hint associated with the library function. The compile time interface generates a bypass structure and modifies the loop to include a call to a planning function for a first pass through the loop and a call to a bypass function for one or more subsequent passes though the loop. The planning function sets the bypass function equal to an optimized library if one or more selected arguments to the library function are loop-invariant.

Abstract: A method of synchronizing data for algorithms of asynchronous computers in an aircraft, the method comprising the steps consisting in: a) generating a sequencing table for each algorithm and, in said table, identifying the number of valid windows for each of which all of the parameters for input to the algorithm are updated at least once; b) distributing the load corresponding to updating the parameters for each algorithm in a send table; and c) instructing the first computer to use the send table.

Abstract: A method for analyzing a program may include generating an initial control flow graph (CFG) for the program, identifying merge blocks of the initial CFG, identifying predecessor-merge pairs based on identifying predecessor blocks for each merge block, simulating a duplication of each predecessor-merge pair, determining whether the duplication satisfies a precondition of each of a collection of optimizations, applying, in response to satisfying the precondition, the optimization to the duplication, and generating a simulation result for the predecessor-merge pair corresponding to the duplication. The simulation result may include the optimization and a benefit of applying the optimization to the duplication. The method may further include duplicating, in the initial CFG, a predecessor-merge pair based on the simulation result corresponding to the predecessor-merge pair.

Abstract: Implementing a circuit design can include determining a chain of a plurality of loop elements of a circuit design, wherein each loop element includes a bit select node configured to perform a bit assignment operation and a corresponding address calculation node, wherein the address calculation nodes use a common variable to calculate a starting bit location provided to the corresponding bit select node. In response to the determining, the chain is replicated resulting in one chain for each value of the common variable and transforming each chain into a plurality of wires. A multiplexer is inserted into the circuit design. The plurality of wires for each chain is coupled to inputs of the multiplexer and the common variable is provided to the multiplexer as a select signal.

Abstract: Embodiments of methods and/or systems of manipulating tree expressions are disclosed.

Abstract: The present disclosure generally relates to predicting automated software tests for testing units of work delivery in a continuous integration development environment. More particularly, the present disclosure relates to systems and methods for improving the efficiency of code integration by predicting a subset of automated software tests from amongst a set of all available automated software tests, thereby improving testing time and reducing processing loads.

Abstract: Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

Abstract: The representation of content, in a scene representation, is enriched with a view to the adaptive use of the latter according to a set of common parameters. A sub-graph of the scene graph, which is susceptible to variable processing, is identified. For this purpose, two new types of scene element can be defined, one of which allows the identification of the sub-graph and the second enables application of the set of common parameters in relation to the sub-graph. An example of the first type is a node of so-called “AdaptivityControl” type which encompasses the entire sub-graph, a list of the nodes describing the set of common parameters and a group of fields for dynamic updating of the content of this node. An example of the second type is a node of so-called “CompressedImageStrategy” type which comprises information relating to the object to be coded and the coding parameters.

Abstract: A method for tracking high-level source attribution of a generated assembly language code includes: receiving commands for compiling or linking a high-level language code; analyzing the received commands to determine whether a command is a compiler command for compiling the high-level language code or a link command for linking the low level object code; when the command is a compiler command: generating assembly language code by compiling the high-level language code, parsing the generated assembly language code to generate an internal representation for the assembly language code, storing the internal representation in a computer memory; and generating associated linker input artifacts for linking; when the command is a link command: updating the internal representation with the associated linker input artifacts; and generating a report file from the updated internal representation.

Abstract: One embodiment of the present invention sets forth a technique for reducing sign-extension instructions (SEIs) included in a computer program, the technique involves receiving intermediate code that is associated with the computer program and includes a first SEI that is included in a loop structure within the computer program, determining that the first SEI is eligible to be moved outside of the loop structure, inserting into a preheader of the loop a second SEI that, when executed by a processor, promotes an original value targeted by the first SEI from a smaller type to a larger type, and replacing the first SEI with one or more intermediate instructions that are eligible for additional compiler optimizations.

Abstract: A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed.

Abstract: A process transforms compiled software into a semantic form. The process transforms the code into a semantic form. The process analyzes behavior functionality by processing precise programming behavior abstractions stored in a memory and classifies the code as malware based on the code behavior. Another method identifies the starting point of execution of a compiled program. The method calculates a complexity measure by calculating the number of potential execution paths of local functions; identifies the number of arguments passed to local functions; and identifies the starting point of execution of the compiled program. Another method provides interactive, dynamic visualization of a group of related functions wherein a user can explore the rendered graph and select a specific function and display functions that are color coded by their ancestral relation and their function call distance to the selected function.

Abstract: Disclosed are ways to flexibly arrange, rearrange, and execute optimization modules for program code in user-customizable sequences. In various embodiments, computer programmers can select an order of multiple standalone optimizers that each perform an optimization function on program code, forming a pipeline of a series of optimization modules. The pipeline can be modified by, for example, adding, removing, rearranging, repeating, and/or replacing optimization modules.

Abstract: A method is provided for executing a code sequence on a security module. The code sequence comprises codes to be replaced and codes to be interpreted. A temporary replacement takes place of a respective code to be replaced by a partial code sequence that comprises at least one code having an interpretable code value. The replacement taking place is dependent on the code value of the code to be replaced. An interpretation of the codes to be interpreted in the code sequence and in the partial code sequence takes place with the aid of interpretation information for code values. During the replacement step, the partial code sequence for the code value of the code to be replaced is additionally produced in dependence on a piece of selection information.

Abstract: A method is described for operating a microprocessor, in which a conversion software executed in the microprocessor carries out a binary translation, in the course of which a source instruction that is encoded according to a first instruction-set architecture is translated into a target instruction in a binary manner, which is encoded according to a second instruction-set architecture, and the target instruction translated by the translation software into the second instruction-set architecture being replicated, and in this replicated target instruction a memory area which is to be accessed in the course of the execution of the target instruction is replaced by a second memory area, and the target instruction and the copied target instruction is executed by the microprocessor.

Abstract: A compiler and a method of compiling code that reduces memory bandwidth when processing code on a computer are provided herein. In one embodiment, the method includes: (1) automatically identifying a sequence of operations for fusing, wherein the sequence of operations correspond to instructions from a source code, (2) determining subdivisions of a final output of the sequence of operations, (3) determining input data and intermediate operations needed to obtain a final subdivision output for each of the subdivisions and (4) automatically generating code to fuse the sequence of operations employing the subdivisions, wherein the automatically identifying and the automatically generating are performed by a processor.

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Abstract: A computer-implemented method includes receiving a set of complete source instructions to process a source code entity, an incremental build part, and a set of file definitions. The method analyzes the set of complete source instructions. The method identifies, from the set of analyzed source instructions, a set of operations that reference the incremental build subset. The method repeats: (i) determining, for each operation, whether any additional files are affected by the operation, the additional files forming a set of affected files; (ii) creating a combined set of files, the combined set of files consisting of the set of affected files and the incremental build subset; and (iii) updating the set of operations to include those from the analyzed source instructions that reference the combined set of files; until no new files are added to the combined set of files. The method generates a set of incremental source instructions.

Abstract: Certain aspects of the present disclosure relate to a technique to access a data source from a client using a driver. A data source name (DSN) is provided to connect to the data source using the driver. The driver is used to interface between the client and an implementation of a driver interface to access the data source based on the DSN.

Abstract: A method of compiling a first program to output a second program, the method includes: determining a number of arithmetic units to be operated during execution of the second program for each of a plurality of sections in the first program; and creating the second program by adding an instruction to specify the number of arithmetic units to be operated to each of the plurality of sections based on the determining.

Abstract: In one example embodiment, live migration in a datacenter may include JIT compiling a process that is configured to be executed on both a source instruction set architecture and a destination instruction set architecture, mapping variables and address stacks of the process on both the source instruction set architecture and the destination instruction set architecture into a labeled form thereof, and mapping the labeled form of the variables and address stacks onto the destination instruction set architecture.

Abstract: A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.

Abstract: A digital marketplace stores an installable web application including a first packaged file including a manifest file and a web page. The digital marketplace receives a request for installation of the installable web application from a computing device. The digital marketplaces automatically determines a computing platform type of the computing device, based on the request, and automatically creates a version of an installation file for the installable web application based on the computing platform type. The version of the installation file includes a portion of the first packaged file. The version of the installation file is smaller than the first packaged file. The digital marketplace provides the version of the installation file to computing device.

Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.

Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.

Abstract: An optimizer for messaging systems learns the purpose and context of each message and combines that information with knowledge of the specific client that will be rendering the response, such as a specific HTML browser. Any of a number of optimization factors can be applied, singly or in any combination. Messages are analyzed offline until a configurable threshold is reached, indicating that enough data has been sampled to develop a valid instruction set, to be applied to the responses that a server generates for a particular request. Responses are parsed into tokens and instructions for each type of token are compiled into instruction sets that are stored. These instructions sets continue to be iteratively improved as more data is collected, until the configurable sampling threshold is reached.

Abstract: Based on source code analysis of an API-invoker program, an expendable set of source code sections of an API-implementer program is identified. The expendable set corresponds to operations which are not expected to be performed on behalf of the API-invoker program at a particular computing environment. An optimized binary version of the API-implementer program is generated, which does not include executable code corresponding to the expendable set. The optimized binary version is transmitted to the computing environment for deployment.

Abstract: This application discloses a computing system configured to simulate an embedded system including a processor capable of executing embedded software, compile the embedded software into a format capable of execution by the computing system, insert instrumentation code into the compiled embedded software, and execute the compiled embedded software and the instrumentation code. The execution of the compiled embedded software can simulate execution of the embedded software by the processor in the simulated embedded system, while the execution of the instrumentation code can configure the computing system to gather information corresponding to the execution of the compiled embedded software.

Abstract: Generic method specialization represents the ability to specialize generic methods over various types. When implementing generic method specialization an annotated class file may include a generic method declaration that is annotated with specialization metadata indicating elements of the generic method to be adjusted during specialization. The annotated method may be usable directly as an erased method implementation (e.g., to load the method when instantiated with reference types) and may also be usable as a template for specialization. When a generic method is being prepared for execution, such as when it is first invoked during runtime, a specialization method generator function may be used to specialize the generic method based on the specialization metadata in the generic method declaration. The specialization method generator function may use the annotated generic method declaration as a template for specialization.

Abstract: Aspects of the disclosure provide a method for identifying an induction variable in a loop during a compiling process. The method includes searching for a phi-function that includes a first operand and a second operand and defines a candidate basic induction variable (BIV), searching for an add/sub instruction that has a first register and a second register wherein the first register is the second operand of the phi-function, or the value in the first register is subsequently stored to the second operand of the phi-function through one or more move instructions, and determining the candidate BIV is a BIV when the second register of the add/sub instruction is the candidate BIV or stores a value that is passed from the candidate BIV through one or more move instructions.

Abstract: An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory accesses among the decoded commands, a hardware prefetch controller configured to execute a prefetch in response to a trigger independent of a prefetch command to execute the prefetch, the prefetch being an operation of transferring data stored in a memory to a cache memory in advance, and a controller configured to determine whether an unnecessary prefetch command to transfer the data, which is to be transferred to the cache memory by the hardware prefetch controller, from the memory to the cache memory is registered in the command holding unit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding unit.

Abstract: Aspects of the subject matter described herein relate to data visualization. In aspects, a caller sends a request to draw a set of shapes that have a shape type common among the shapes. The request may be for a static drawing or 1 of N animation frames. If the device has a graphical processing unit (GPU) that is available, GPU code is generated for the GPU to draw the set of shapes. Otherwise, CPU code is generated to draw the set of shapes. The drawing code is tailored to the constant, data-mapped, and animated attribute values specified by the caller and omits conditional statements that test values that are computable prior to drawing the shapes.

Abstract: System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

Abstract: A computer implemented method for generating code for an integrated data system. A mixed data flow is received. The mixed data flow contains mixed data flow operators, which are associated with multiple runtime environments. A graph is generated containing logical operators based on the mixed data flow in response to receiving the mixed data flow. The logical operators are independent of the plurality of runtime environments. The graph is converted to a model. The logical operators are converted to model operators associated with the multiple runtime environments. The model operators allow for analysis of operations for the mixed data flow. The model is converted into an execution plan graph. The execution plan graph is executable on different runtime environments.

Abstract: A language-based model to support asynchronous operations set forth in a synchronous syntax is provided. The asynchronous operations are transformed in a compiler into an asynchronous pattern, such as an APM-based pattern (or asynchronous programming model based pattern). The ability to compose asynchronous operations comes from the ability to efficiently call asynchronous methods from other asynchronous methods, pause them and later resume them, and effectively implementing a single-linked stack. One example includes support for ordered and unordered compositions of asynchronous operations. In an ordered composition, each asynchronous operation is started and finished before another operation in the composition is started. In an unordered composition, each asynchronous operation is started and completed independently of the operations in the unordered composition.

Abstract: A device and method for processing virtual worlds. According to embodiments of the present disclosure, information which is measured from the real world using characteristics of a sensor is transferred to a virtual world, to thereby implement an interaction between the real world and the virtual world. The disclosed device and method for processing virtual worlds involve selectively transferring information, from among the measured information, which is different from previously measured information. The disclosed device and method for processing virtual worlds involve transferring the entire measured information in the event that the measured information is significantly different from the previously measured information and for selectively transferring information, from among the measured information, which is different from the measured information in the event that the difference is not significant.

Abstract: A cache management system, method, and computer-readable medium which manage caching of resources are provided. The method includes receiving a request for a resource including a hierarchical resource locator, fetching the resource from a node upon determining that the resource is not stored in a cache, adding an entry for the resource to a mapping table associated with the cache, the entry including the resource locator and dependency information for dependent resources identified from the hierarchical structure of the resource locator, and updating entries in the mapping table for master resources identified from the hierarchical structure of the resource locator, the updated entries including an identifier for the resource.

Abstract: Provided are a computer program product, system, and method for generating a view for a schema. A schema provides a definition of elements, wherein at least one of the elements comprises a recursive element of a recursive data type, wherein the recursive data type allows for instances of the recursive element to include instances of that same recursive data type at different levels in a hierarchy. Indication is received to transform the recursive types to non-recursive structures. A view for the schema is generated including information on the indication to transform the recursive types to non-recursive structure, wherein the processing of the data defined by the view causes a parser to generate a structured element for each instance of the recursive element in schema data being parsed, wherein the generated structured element includes a unique identifier of the instance of the recursive element.

Abstract: A method of processing a handover request from a base station controller (BSC) of a GSM (Global System for Mobile communication)-type network. The method comprises the steps of passing a handover request with GSM-type parameters from a base station controller (BSC) through a Master Switching Center (MSC) of the GSM-type network to a UMTS core network (CN) and to a Radio Network Controller (RNC) of the UMTS (Universal Mobile Telecommunications System) network, translating the GSM-type parameters to UTRAN parameters in the Radio Network Controller (RNC), and allocating UTRAN resources in response to the translated parameters.

Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

Abstract: A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression.