Abstract: A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression.

Abstract: A method for optimizing if statements in a program includes obtaining, by a processing device, for each of conditional expressions of a plurality of if statements in the program, a set of conditional expressions having an inclusion relation; computing, for each of the set, a position with low execution frequency in the program as a move destination of a conditional expression having an inclusion relation, using information of the set in which the conditional expression is included; and moving the conditional expression to the computed move destination of the conditional expression.

Abstract: Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.

Abstract: Techniques to automatically port applications to a mobile infrastructure using code separation with semantic guarantees are disclosed. Porting enterprise applications from to a target architecture another is effected via separating code into constituent layers of the target architecture. To preserve semantics, code transformations are enforced via an abstract syntax tree structure. The generated code may have various code wrappers and/or infrastructure elements so the ported application will operate in the target architecture. Various techniques are disclosed regarding specific code wrappers and/or infrastructure elements to address operating issues including, but not limited to, architectural issues, network latency, framework changes, regulatory issues.

Abstract: A resource allocation method and apparatus utilize the GPU resource efficiently by sorting the tasks using General Purpose GPU (GPGPU) into operations and combining the same operations into a request. The resource allocation method of a Graphic Processing Unit (GPU) according to the present disclosure includes receiving a task including at least one operation; storing the at least one operation in unit of request; merging data of same operations per request; and allocating GPU resource according to an execution order the request.

Abstract: Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.

Abstract: In transactional memory systems, transactional aborts due to conflicts between concurrent threads may cause system performance degradation. A compiler may attempt to minimize runtime abort rates by performing code transformations and/or other optimizations on a transactional memory program in an attempt to minimize store-commit intervals. The compiler may employ store deferral, hoisting of long-latency operations from within a transaction body and/or store-commit interval, speculative hoisting of long-latency operations, and/or redundant store squashing optimizations. The compiler may perform optimizing transformations on source code and/or on any intermediate representation thereof (e.g., parse trees, un-optimized assembly code, etc.). The compiler may preemptively avoid naïve target code constructions.

Abstract: Described herein are implementations for providing a platform adaptation layer that enables applications to execute inside a user-mode hardware-protected isolation container while utilizing host platform resources that reside outside of the isolation container. The platform adaptation layer facilitates a system service request interaction between the application and the host platform. As part of the facilitating, a secure services component of the platform adaptation layer performs a security-relevant action.

Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.

Abstract: A system for managing and exchanging electronic information provides a rules management component for executing conceptual rules, an ontology management component, an information model management component, and a system configuration management component. The ontology management component manages at least one ontology and mappings between members of different ontologies. The ontologies may include a code system and a terminology. The ontology management component may manage a value set that is a subset of the terminology. The information model management component manages one or more information model schemas, each defining an information model and comprising information defining at least one slot within the information model. The system configuration management component manages configuration information on the configuration of each system component.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a full set of analysis artifacts after incremental analysis of a source code base. One of the methods includes receiving a first full set of analysis artifacts and an incremental set of analysis artifacts for a project. An initial keep graph that is initially equivalent to the full build graph is generated. Any source code file or analysis artifact nodes that also occur in the incremental build graph are removed from the keep graph. Analysis artifacts for source code files in the full build graph that do not occur in the keep graph are deleted from the first full set of analysis artifacts. The analysis artifacts represented by nodes in the incremental build graph are copied into the first full set of analysis artifacts to generate a second full set of analysis artifacts for the project.

Abstract: One aspect of the invention provides a method of controlling execution of a computer program. The method comprises the following runtime steps: parsing code to identify one or more indirect branches; creating a branch ID data structure that maps an indirect branch location to a branch ID, which is the indirect branch's equivalence class ID; creating a target ID data structure that maps a code address to a target ID, which is an equivalence class ID to which the address belongs; and prior to execution of an indirect branch including a return instruction located at an address: obtaining the branch ID associated with the return address from the branch ID data structure; obtaining the target ID associated with an actual return address for the indirect branch from the target ID data structure; and comparing the branch ID and the target ID.

Abstract: The present invention reduces the time required to apply an update package for generating a new image from an original image within a non-volatile memory device by effectively reducing the number of flash blocks requiring modification by use of whatever free space is available at the end of the image as required. A set of software development guidelines and an improved firmware development tool chain (i.e. compiler, linker, etc.) are utilized to produce new firmware for the client device. A firmware programmer follows or applies this set of guidelines when developing new features and fixes for distribution via a new firmware image. The improved firmware development tool chain executes on a collection of function blocks, available from the development of the original image, used to create new firmware source code, which when complied and linked yields a new image, prior to the delta or differencing processing.

Abstract: A method, a system, and a non-transitory computer readable medium for parallelizing computer program code including a loop are presented. An intermediate language version of the computer program code is generated based on a parallel type of the loop, wherein the intermediate language version includes information about parallelism in the computer program code. The intermediate language version is optimized at runtime based on the device characteristics where the computer program code is to be executed. The parallel type may include a thread parallel type, wherein the loop is dispatched to multiple threads for execution, or a general parallel type, wherein the loop is dispatched to a single thread and may be vectorized for execution. The intermediate language version may be saved separate from the computer program code.

Abstract: A method for computation of the state variables of a hybrid differential-algebraic process model in succeeding time steps on a process computer with a process interface, the process computer being set up such that, via the process interface, at least one process variable of a physical process can be detected by the process computer and/or one output for influencing the physical process can be output by the process computer. In a computation process, a current mode of the hybrid DAP is determined by evaluating the state variables for a deviation of the current mode of the hybrid DAP from the mode of the hybrid DAP applying beforehand, a mode-specific process model which corresponds to the current mode being chosen from the group of executable mode-specific process models and further computation is based on it. At least one probable future mode of the hybrid DAP is determined in a prediction process.

Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU. The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream.

Abstract: A method is disclosed for translating by a computer system of a COBOL computer program into a translated computer program in a readable and maintainable syntax in an object oriented programming language. The translated program including variable names equivalent to the original COBOL variable names and with attributes described in COBOL syntax. The translating method further providing for memory allocation in the translated computer program for storage of “COBOL” variables compatible with that of the original COBOL program; a description of program flow that is readable, and utilizing arithmetic operators to describe operations between COBOL variables. Also disclosed is a special object oriented run-time library for creating and performing operations between COBOL numeric objects, including maintaining storage of variable content in the original COBOL format, and for enabling readability of the translated source code by allowing arguments for variable type descriptions to be expressed in COBOL syntax.

Abstract: A method for control flow analysis according to an embodiment of the present invention includes: acquiring an original function call tree of a program, wherein nodes of the original function call tree represent functions and a parent/child relation between the nodes represents a calling relation; generating a corresponding function dominator tree from the calling relation, wherein nodes of the function dominator tree represent the functions and a parent/child relation between the nodes represents a dominator relation, wherein a first function dominates a second function if all the invocations to the second function are originated by the first function; and simplifying the original function call tree according to the function dominator tree so as to obtain a simplified function call tree. According to an embodiment of the present invention, the function call tree for control flow analysis can be simplified.

Abstract: A system for the operation of a virtual assistant network, comprising a plurality of virtual assistants stored and operating on network-connected devices, and a plurality of virtual assistant brokers stored and operating on network-connected devices, wherein the virtual assistants receive user requests and send the requests to the virtual assistant brokers, and wherein the virtual assistant brokers delegate the requests to other virtual assistants for fulfillment.

Abstract: A parallel-code optimization system includes a Procedural Concurrency Graph (PCG) generator. The PCG generator produces an initial PCG of a computer program including parallel code, and determines a refined PCG from the initial PCG by applying concurrency-type refinements and interference-type refinements to the initial PCG. The initial PCG and the refined PCG include nodes and edges connecting pairs of the nodes. The nodes represent defined procedures in the parallel code, and each edge represents a may-happen-in-parallel relation, and is associated with a set of lvalues that represents the immediate interference between the corresponding pair of nodes.

Abstract: A method for control flow analysis according to an embodiment of the present invention includes: acquiring an original function call tree of a program, wherein nodes of the original function call tree represent functions and a parent/child relation between the nodes represents a calling relation; generating a corresponding function dominator tree from the calling relation, wherein nodes of the function dominator tree represent the functions and a parent/child relation between the nodes represents a dominator relation, wherein a first function dominates a second function if all the invocations to the second function are originated by the first function; and simplifying the original function call tree according to the function dominator tree so as to obtain a simplified function call tree. According to an embodiment of the present invention, the function call tree for control flow analysis can be simplified.

Abstract: Implementation of a meta-model service of a service oriented architecture industry model repository into a web ontology language representation of at least one topic map meta-model into a plurality of temporal scope topic map meta-models representing states of the at least one topic map meta-model at different times. The implementation includes assigning topics, occurrences, and attributes from the meta-model service to the at least one topic map meta-model. The topics, occurrences, and attributes are assigned from the at least one topic map meta-model to plurality of temporal scope topic map meta-models. The topics, occurrences, and attributes from the plurality of temporal scope topic map meta-models are converted into resource description framework triples; and the resource description framework triples are persisted into the resource description framework repository.

Abstract: The present disclosure relates to a stack overflow protection device and a stack protection method. According to the present disclosure, a stack overflow protection device is provided, which includes a dividing unit configured to divide at least one function in the input codes into a code region with a string operation and a code region without a string operation. The device also includes a stack protection unit configured to set up stack protection in the code region with a string operation. The present disclosure further provides a stack protection method.

Abstract: A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

Abstract: An exemplary embodiment of the present disclosure illustrates a hybrid dynamic code compiling device having a parser, a native code generator, and a dynamic code rewriter, wherein the parser is coupled to the native code generator and the dynamic code rewriter. The parser receives and parses a first dynamic code to divide the first dynamic code into compilable blocks and non-compilable blocks. The native code generator generates a native code according to the compilable blocks. The dynamic code rewriter rewrites the non-compilable blocks to generate a second dynamic code, wherein the second dynamic code has function calls which communicate between the native code and the first dynamic code.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for just in time compilation. In one aspect, a method includes receiving an application on a mobile device, the mobile device including a processor for executing native code and an interpreter for interpreting intermediate code, wherein an application includes at least one machine instruction; receiving data characterizing prior actions of the application on the mobile device; determining a portion of intermediate code to be compiled into native code based at least in part on the data, wherein the portion includes some but not all of the application; sending the portion of intermediate code over a network to a compilation server; receiving native code corresponding to the portion of intermediate code from the compilation server; and executing the native code on the processor.

Abstract: The present invention generally relates to a method for describing network events in a service aware network (“SAN”). In addition, the present invention relates to software that performs the method and has a programming model containing protocol libraries, abstract protocol messages declarations, and network events. The method and software enable a user to define basic as well as complex network events in the application, presentation, session, transport and/or network layers of a communication model, which result in internet protocol (“IP”) level triggers or other triggers. Such triggers will result in actions which may be applicable in all layers of a communication model up to the highest layer. As a result, the method and software allow a user to describe a hierarchy of high level network events through a hierarchy of lower level events. In addition, a development system and an apparatus which utilizes the method and software are also provided.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that allows an application comprising a single code set under the COBOL Programming Language to execute in multiple platforms on the same multi-platform system (such as a mainframe). In one embodiment, a single code set is pre-compiled to determine specific portions of the code set compatible with the host (or prospective) platform. Once the code set has been pre-compiled to determine compatible portions, those portions may be compiled and executed in the host platform. According to these embodiments, an application may be executed from a single code set that is compatible with multiple platforms, thereby potentially reducing the complexity of developing the application for multiple platforms.

Abstract: A mechanism is provided for de-serializing a representation of a source object of a source software component written in a source language into a target software component written in a target language. A representation of the source object is received and a determination is made of a set of candidate types among a plurality of available types that are in the target language for the target software component, each candidate type being compatible with the representation of the source type. A set of match metrics is calculated, each one for a corresponding candidate type, where the match metric being indicative of a difference in information content between the candidate type and the representation of the source object. One of the candidate types is selected according to the match metrics and a mapping of the representation of the source object onto a target object of the selected candidate type is created.

Abstract: In one embodiment, input code is received having a plurality of functional elements that process data elements. At least one criterion for generated code is also received. A first intermediate representation of the input code is built that has a plurality of nodes that represent the functional elements. Block sizes are assigned to two or more nodes of a first intermediate representation. The first intermediate representation is modified to create a second intermediate representation that satisfies the at least one criterion, and organizes at least some of the nodes of the first intermediate representation based on the block sizes.

Abstract: One embodiment of the present invention sets forth a technique for extracting a memory address offset from a 64-bit type-conversion expression included in high-level source code of a computer program. The technique involves receiving the 64-bit type-conversion expression, where the 64-bit type-conversion expression includes one or more 32-bit expressions, determining a range for each of the one or more 32-bit expressions, calculating a total range by summing the ranges of the 32-bit expressions, determining that the total range is a subset of a range for a 32-bit unsigned integer, calculating the memory address offset based on the ranges for the one or more 32-bit expressions, and generating at least one assembly-level instruction that references the memory address offset.

Abstract: Systems and methods for just-in-time (JIT) code compilation by a computer system. An example method may comprise identifying a defined pattern in a byte stream, evaluating a conditional expression associated with the pattern, and compiling the byte stream into a native code, while excluding, in view of the evaluating, a portion of byte stream associated with the pattern.

Abstract: A computer-implemented method for generating one or more build system build files using a unified build system configuration file includes: receiving the unified build system configuration file in a computer system, the unified build system configuration file comprising at least one platform-independent build system configuration; generating, using the computer system, at least one platform-specific build system configuration from the at least one platform-independent build system configuration; selecting at least one template for the unified build system configuration file, the template selected from among templates corresponding to each of multiple platforms; generating the one or more build system build files for at least one of the multiple platforms using the platform-specific build system configuration and the selected template; and providing the generated one or more build system build files in response to the unified build system configuration file.

Abstract: A method and system for providing target code to various computer systems. The target code is provided by a service. The service provides a mechanism for third-party developers to submit initial or base code for distribution to end-user computers as target code. The service converts the initial code to target code that is suitable for execution on the end-user computers. When the service receives the request for target code that matches certain requester-specified characteristics, it selects the intermediate code that best matches the requester-specified characteristics. The service then sends the target code to the requester.

Abstract: Disclosed here are methods, systems, paradigms and structures for optimizing generation of intermediate representation (IR) for a script code by eliminating redundant object reference count operations from the IR. An IR of the script includes (a) a set of first code that increments a reference count of an object when a programming construct refers to the object, and (b) an associated set of second code which decrements the reference count of the object when a reference to the object is removed. The IR is analyzed to identify a subset of the set of second code which, upon execution, does not decrement the reference count of the object to a zero value. The subset of second code and the first code corresponding to the subset is removed from the IR to generate an optimized IR. The optimized IR is further converted to an executable code.

Abstract: Processes in a message passing system may be launched when messages having data patterns match a function on a receiving process. The function may be identified by an execution pointer within the process. When the match occurs, the process may be added to a runnable queue, and in some embodiments, may be raised to the top of a runnable queue. When a match does not occur, the process may remain in a blocked or non-executing state. In some embodiments, a blocked process may be placed in an idle queue and may not be executed until a process scheduler determines that a message has been received that fulfills a function waiting for input. When the message fulfills the function, the process may be moved to a runnable queue.

Abstract: Techniques provided herein facilitate just-in-time compilation of source code, such as a script, during execution. According to some embodiments, a tracelet is limited to a single basic block of code. The data types of variable values provided by one or more variables used in the single basic block of code are known by generalized categories, rather than only being known by specific data types. Accordingly, guard code associated with each tracelet, which ensures that variable values received by the tracelet though the variables are of the data types expected by the tracelet's associated code body, can use generalized data types. The tracelet can contain code body that can handle input values that meet those generalized data types. A generalized data type can be defined according to one or more common characteristics shared by two or more specific data types.

Abstract: A device receives programming code, corresponding to a dynamic programming language, that is to be executed by a computing environment, and executes the programming code. When executing the programming code, the device maintains a program counter that identifies an execution location within the programming code, and select blocks of the programming code based on the program counter. The blocks correspond to segments of the programming code, and are associated with type-based constraints that relate to types of variables that are used by the block. When executing the programming code, the device also compiles the selected blocks, caches the compiled blocks along with the type-based constraints, generates linking information between certain ones of the compiled blocks based on the type-based constraints, and executes the compiled blocks in an order based on the program counter, the type-based constraints, and the linking information.

Abstract: A method for preventing the unauthorized modification of a software or unauthorized modification of runtime data. According to this method, a converter, which is capable of converting the software into a generalized machine code is provided. The converter is designed such that it cannot he reverse engineered, by using a conversion process that causes data loss. An interpreter, which the knowledge of its process method is kept restricted, is also provided. The interpreter interprets the general machine code into a specific machine code, while reconstructing the lost data during the interpretation process.

Abstract: The analysis of an intermediate representation of source or program code. An initial version of an initial representation of the source or program code is accessed and statically analyzed. For one or more portions of this initial version, the analysis component queries an analysis-time resolution component that provides supplemental intermediate representations corresponding to the portion. This supplemental intermediate representation provides further clarity regarding the portion, and is analyzed. If defects are found, they may be reported.

Abstract: A method, apparatus, and program product are disclosed for carrying out the compilation of an original Cobol program that includes a mix of Cobol, C++ or JAVA and optional OpenMP directives in a single source program file so as to provide improved performance during execution of the program and improved convenience and features in programming.

Abstract: This invention relates to a method of encoding a path in layered form so as to allow partial decoding and progressive rendering while decoding. The path is made of an original sequence of original draw commands, each corresponding to an original portion of a drawing. The method of encoding includes transforming at least one original draw command into an approximating draw command according to a geometrical approximation of the corresponding original portion of a drawing, to obtain a reduced sequence, encoding the reduced sequence into an encoded reduced sequence, and encoding a reconstruction information set representing the difference between the reduced sequence and the original sequence.

Abstract: The method includes: —pre-compiling a source code including determining (212), in the source code, the presence of one or a plurality of array computations on one or a plurality of arrays, referred to as input arrays, the result whereof is assigned to an array, referred to as a result array, and modifying (214) the source code according to the array computation(s) for which the presence has been determined; and —compiling (238) the modified source in machine code intended to be executed by a computer system, referred to as a target computer system, having a processor, the compiling (238) of the modified source code including compiling the command instructions in instructions which, when executed by the processor of the target computer system, command a specialised electronic device, different from the processor, to carry out each array computation detected.

Abstract: Systems and methods for replacing inferior code segments with optimal code segments. Systems and methods for making such replacements for programming languages using Message Passing Interface (MPI) are provided. For example, at the compiler level, point-to-point code segments may be identified and replaced with all-to-all code segments. Programming code may include X10, Chapel and other programming languages that support parallel for loop.

Abstract: The present invention provides a method and system for optimization of an intermediate representation in a graphical modeling environment. A first intermediate representation is provided. At least one optimization technique is applied to the first intermediate representation. A second intermediate representation is generated responsive to the application of the at least one optimization technique to the first intermediate representation.

Abstract: A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.

Abstract: A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Abstract: A method, an apparatus, and a computer program product which capture and use analytics data relating to the internal activity of software programs executing in a message-passing runtime environment, such as that provided by Objective-C. The invention exploits the well documented interfaces of these environments together with their dynamic runtime capabilities to insert data collection and analysis code into an application without modification of the target application.

Abstract: In one embodiment, the invention is a method and apparatus for use of vectorization instruction sets. One embodiment of a method for generating vector instructions includes receiving source code written in a high-level programming language, wherein the source code includes at least one high-level instruction that performs multiple operations on a plurality of vector operands, and compiling the high-level instruction(s) into one or more low-level instructions, wherein the low-level instructions are in an instruction set of a specific computer architecture.

Abstract: Systems and methods are provided for converting Sequential Function Chart (SFC) logic to function block logic for execution by a programmable controller. In one embodiment, a method includes receiving Sequential Function Chart (SFC) logic comprising Steps and Transition on a physical computing device, converting the Steps and Transitions of the Sequential Function Chart logic to function block logic on the physical computing device, and uploading the function block logic from the physical computing device to a controller.