Static (source Or Intermediate Level) Patents (Class 717/152)
  • Patent number: 7627864
    Abstract: A method to optimize speculative parallel thread execution comprises selecting a plurality of partition candidate pairs for speculative parallel thread execution, transforming each partition candidate pair of the plurality of partition candidate pairs to improve the expected performance gain of each pair, and selecting a set of one or more transformed partition candidate pairs that do not interfere with each other and produce a maximum expected performance gain.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: December 1, 2009
    Assignee: Intel Corporation
    Inventors: Zhao Hui Du, Tin-fook Ngai, Chu-cheow Lim
  • Patent number: 7624387
    Abstract: A complier, program product, compilation device, communication terminal device and compilation method that enables parts of a source program having a large number of executions, or parts having a high possibility of a large number of executions, to be extracted with good precision and compiled preferentially. A loop having a multi-nested structure or a single-nested structure is searched for in a main program, and another program that is being called from within this loop is detected. Additionally, a loop having a multi-nested structure or a single-nested structure is searched for in the callee program, and the total number of nests in the loops detected so far is calculated as the loop depth. In other words, the degree of multiplicity in all of the loops forming a multi-nested structure over programs having a calling relationship is calculated as the loop depth.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: November 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Takehiro Yoshida, Takuji Kawamoto
  • Publication number: 20090254893
    Abstract: A mechanism and functionality are provided for generating and using compiler optimized function variants. These variants may be used, for example, in situations where return values of functions called by code are not thereafter used by the code calling the functions. In particular, for a function called by computer code, at least two variants for the function may be generated. A function call, for calling the function, within original computer code may be analyzed to determine which variant of the at least two variants to use for the function call. The function call may be modified in the original computer code, to generate modified computer code, based on results of the analysis identifying which variant of the at least two variants to use for the function call.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 8, 2009
    Applicant: International Business Machines Corporation
    Inventors: Manish Ahuja, Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Patent number: 7600223
    Abstract: In a managed code execution environment in which resources are constrained, resources may be managed in accordance with weak references for which semantics are extended.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: October 6, 2009
    Assignee: Microsoft Corporation
    Inventors: Davide Massarenti, Donald R. Thompson
  • Patent number: 7581210
    Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically scheduling a redundant operation on one of the functional units that would otherwise be idle during a cycle.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: August 25, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dale John Shidla, Andrew Harvey Barr, Ken Gary Pomaranski
  • Patent number: 7577936
    Abstract: A compiler optimizing conversion of a character coding system for a character stored in a string variable in a target program to be optimized has a conversion instruction generation section which generates a conversion instruction to convert a character from a first character coding system to a second character coding system and to store the converted character in the string variable, the conversion instruction being generated before each of a plurality of procedures by which the character in the string variable written in the first character coding system is read out and is used in the second character coding system, and a conversion instruction removal section which removes each of conversion instructions generated by the conversion instruction generation section if a character in the second character coding system is stored in the string variable in each of the execution paths executed before the conversion instruction.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: August 18, 2009
    Assignee: International Business Machines Corporation
    Inventors: Akira Koseki, Michiaki Tatsubori, Kazuaki Ishizaki, Hideaki Komatsu
  • Patent number: 7574703
    Abstract: A method and apparatus for reducing instruction dependencies in extended SSA form instructions includes examining a first instruction of a worklist. The worklist contains instructions in the extended SSA form that have a source, a previous link and a write mask and further produce an output. The method and apparatus further includes examining at least one second instruction of the worklist, where the at least one second instruction is a source of the first instruction. Lastly, the method and apparatus includes translating the plurality of instructions in the worklist into a second plurality of instructions in the extended SSA form where the second plurality of instructions contains less instruction dependencies such as previous links.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 11, 2009
    Assignee: Broadcom Corporation
    Inventor: Gang Chen
  • Publication number: 20090187896
    Abstract: Compiler device for optimizing program which manipulates a character string includes append instruction detection unit, store code generation unit, and append code generation unit. The append instruction detection unit detects an append instruction which appends a character string to a string variable for storing a character string, in the program. The store code generation unit generates, a substitute for each of a plurality of the append instructions detected by the append instruction detection unit, a store code for storing data of an appendant character string to be appended to the string variable by the append instruction into a buffer. The append instructions append the character strings to the same string variable. The append code generation unit generates append code for appending a plurality of the appendant character strings to the string variable, at a position executed before an instruction to refer to the string variable in the program.
    Type: Application
    Filed: November 10, 2008
    Publication date: July 23, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takeshi Ogasawara, Tamiya Onodera, Mikio Takeuchi
  • Patent number: 7549146
    Abstract: Techniques for execution-driven loop splitting and load-safe code hosting are provided. Compiled code includes statements associated with an original loop and statements associated with an alternative loop. The alternative loop reproduces the original loop except for conditional load-safe invariant expressions that appeared in the original loop and that are separated out of the alternative loop. During processing, once the conditional load-safe invariant expressions are computed and referenced for a first time within the original loop, processing dynamically switches to the alternative loop where the conditional load-safe invariant expressions are computed outside of the alternative loop and referenced from within the alternative loop.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: June 16, 2009
    Assignee: Intel Corporation
    Inventors: Xinmin Tian, Milind B. Girkar
  • Patent number: 7516481
    Abstract: A program development supporting apparatus that groups a plurality of events each executed in an information processor to divide the events into a plurality of parallel execution units to be executed in parallel with each other has a directional graph acquisition section that acquires directional graph data expressing each of the plurality of events as a vertex and a restriction on the execution order between two of the plurality of events as a directional branch, an inverse chain partial set extraction section that traces the directional branch from each event in the forward direction to extract from the directional graph data an inverse partial set that is a combination of the events having such a relationship that any one of the events cannot be reached from the other events, and a parallel execution unit assignment section that assigns the plurality of events belonging to the inverse partial set to units different from each other in the parallel execution units.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 7, 2009
    Assignee: International Business Machines Corporation
    Inventor: Toshiyuki Fujikura
  • Patent number: 7506326
    Abstract: An improved method, apparatus, and computer instructions for generating instructions to process multiple similar expressions. Parameters are identified for the expressions in the original instructions, to form a set of identified parameters typically including the operations performed, the types of data used, and the data sizes. Each type of execution unit that can execute the instructions needed to process the expressions using the set of identified parameters is identified, wherein a set of identified execution unit types is formed. An execution unit type from the set of identified execution unit types is selected to meet a performance goal. The new instructions are generated for the selected execution unit type to process the expressions, and the original instructions for the expressions are discarded.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 17, 2009
    Assignee: International Business Machines Corporation
    Inventor: Ronald Ian McIntosh
  • Patent number: 7493607
    Abstract: A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the speculative static information in an instruction set architecture of a processor, and executing a compiled computer program using the speculative static information, wherein executing supports static speculation driven mechanisms and controls.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: February 17, 2009
    Assignee: BlueRISC Inc.
    Inventor: Csaba Andras Moritz
  • Patent number: 7493609
    Abstract: A method and apparatus for automatic second-order predictive commoning is provided by the present invention. During an analysis phase, the intermediate representation of a program code is analyzed to identify opportunities for second-order predictive commoning optimization. The analyzed information is used by the present invention for apply transformations to the program code, such that the number of memory access and the number of computations are reduced for loop iterations and performance of program code is improved.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Arie Tal, Dina Tal
  • Patent number: 7472375
    Abstract: In one embodiment, the present invention includes a method for generating an assembly that is usable in a managed environment. More specifically, the assembly may be an all-inclusive object file that contains a native code module, a managed wrapper and prototype information in a single assembly. The method may include forming an object file from a native code module, where the object file includes prototype information, generating a managed code wrapper using the prototype information, and creating a single assembly including the managed code wrapper and the native code module. In some embodiments, the managed code wrapper may be automatically created, reducing burden on a developer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Jinyun Ye, Zhikai Song, Gururaj Nagendra
  • Patent number: 7458071
    Abstract: The compilation method, which allows a programmer to perform programming without minding about pass-by-reference, and offers efficiency in generating codes even in the case of using “pass by value”, includes the following: generating intermediate codes from a source program; optimizing the intermediate codes by converting a procedure that calls a procedure with pass-by-value argument into a procedure that calls a procedure with pass-by-reference argument, in the case where there is no procedure that may indirectly call the procedure with pass-by-value argument, and the pass-by-value is not updated within the definition according to the procedure with pass-by-value argument; and converting the optimized intermediate codes into object codes.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventor: Shinobu Asao
  • Patent number: 7458069
    Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: November 25, 2008
    Assignee: Intel Corporation
    Inventors: Ronny Ronen, Alexander Peleg, Nathaniel Hoffman
  • Patent number: 7458070
    Abstract: The present invention is a method, system and apparatus for reducing the run-time cost of invoking a server page. The system can include a server page translation unit configured to translate a server page document into program code. The system also can include a program code compiler configured to compile the program code into a program object. Finally, the system can include an optimization processor programmed to modify the program code to permit direct invocation of the program object by external program objects bypassing a server engine typically used to invoke the server page. Notably, in a preferred aspect of the invention the server page can be a JSP. Similarly, the program code can be Java source code and the program object can be a Java class. Finally, the external program objects can be servlets.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: November 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Martin J. Presler-Marshall, Scott H. Snyder
  • Patent number: 7448029
    Abstract: An error handling operation for checking of an array access in program code is modified during compilation thereof. A sequentially arranged null checking operation and array bounds checking operation for the array access are located. The array bounds checking operation has a corresponding error handling operation operable for setting an array bounds error. The located sequentially arranged null checking operation is removed. The corresponding error handling operation for the located sequentially arranged array bounds checking operation is modified to perform the removed null checking operation during execution of the program code.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventor: Allan Henry Kielstra
  • Patent number: 7444626
    Abstract: An apparatus and method for removing stores to local variables that are not aliased by other variables or to variables which have already been removed by previous optimizations prior to performing dead store elimination optimization are provided. With the method and apparatus, instructions that include a memory reference to a local variable that is not modified by other instructions are identified. For these instructions, an identifier of the variable referenced is maintained in a data structure along with the location of the store instruction in the procedure (for a store instruction) or a load indicator (for a load instruction). The data structure is then traversed to see if there are any store instructions referencing a variable that does not have a corresponding load instruction referencing the same variable. Such store instructions are eliminated prior to performing traditional dead store elimination.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 28, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ronald Ian McIntosh, Mark Peter Mendell
  • Patent number: 7434213
    Abstract: Platform independent processing of the source code is performed, such as lexical analysis, semantic analysis, syntax analysis, and platform independent optimization, and an intermediate representation of the source code is generated. This intermediate representation is carried forward into the next stage of processing, which is platform dependent processing. The intermediate representation undergoes machine specific analysis and an executable representation (i.e., executable code) of the source code for a particular platform is generated. However, the intermediate representation, which has not been converted to a machine specific representation, is included with the executable representation. The source code can essentially be ported to a different platform by extracting the intermediate representation and performing platform dependent processing on the intermediate representation.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 7, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Raj Prakash, Kurt J. Goebel, Fu-Hwa Wang
  • Patent number: 7426723
    Abstract: A classfile modification method is described. The classfile modification method entails converting a classfile into a collection of objects whose organization is derived from the classfile's organization. The collection of objects comprise unique objects for each method information structure found in the classfile. Each of the unique objects reference other objects in the organization. The other objects represent their corresponding unique object's method information structure's byte code instructions. The classfile modification method also entails adding at least one additional other object to an arrangement of other objects that are referenced to a unique object. The at least one additional other object corresponds to at least one byte code instruction that causes a plug-in module's handler method to provide output function treatment for the unique object's method. The classfile modification method also entails converting the resulting collection of objects into a modified version of the classfile.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: September 16, 2008
    Assignee: SAP AG
    Inventor: Nikolai G. Nikolov
  • Patent number: 7426720
    Abstract: A system and method for dynamic preloading of classes through memory space cloning of a master runtime system process is presented. A master runtime system process is executed. A representation of at least one class is obtained from a source definition provided as object-oriented program code. The representation is interpreted and instantiated as a class definition in a memory space of the master runtime system process. The memory space is cloned as a child runtime system process responsive to a process request and the child runtime system process is executed, inheriting the memory state of the parent, which reflects the data structures and state corresponding to the preloaded classes.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: September 16, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Nedim Fresko
  • Patent number: 7406418
    Abstract: In a voice-extensible markup-language-enabled voice application deployment architecture, an application logic for determining which portions of a voice application for deployment are cached at an application-receiving end system or systems has a processor for processing the voice application according to sequential dialog files of the application, a static content optimizer connected to the processor for identifying files containing static content, and a dynamic content optimizer connected to the processor for identifying files containing dynamic content. The application is characterized in that the optimizers determine which files should be cached at which end-system facilities, tag the files accordingly, and prepare those files for distribution to selected end-system cache facilities for local retrieval during consumer interaction with the deployed application.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: July 29, 2008
    Assignee: Apptera, Inc.
    Inventor: Leo Chiu
  • Patent number: 7401329
    Abstract: A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at which arbitrary selection between further vertices C, D to be added must be made. This data flow graph with these small clusters is then scheduled such that the clusters do not overlap with other clusters or with vertices outside of clusters. This starting point scheduled data flow graph is then subject to iterative processing whereby a window of timestamps is analysed to see if a candidate cluster formed by the parallel execution of the vertices within that window will result in faster execution whilst avoiding exceeding architectural constraints, such as register occupancy. If the rescheduled vertices do improve performance without exceeding architectural constraints, then this new schedule is adopted and the following vertices are subject to an adjustment in their timestamps to account for this.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: July 15, 2008
    Assignee: ARM Limited
    Inventor: Bert De Rijck
  • Patent number: 7392245
    Abstract: A pre-pass and direct call mechanism which replaces the interpreter. The mechanism moves static decisions out of the repeated runtime path into a pre-pass operation. Advantageously, the mechanism reduces runtime overhead and improves overall performance of the DBMS during runtime, while maintaining the considerable investment in opcode generation and plan representation.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ian R. Finlay, Douglas James Doole
  • Patent number: 7392516
    Abstract: There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In accordance with an embodiment of the invention, a heuristic function is used to obtain a ranking of nodes in the DDG after setting delays at all identified by-pass pairs of nodes in the DDG to 0. From among a list of identified by-pass pairs of nodes, a node that is identified as being the least important to schedule early is marked as “bonded” to its successor, and the corresponding delay for that identified node is set to 0. Node rankings are re-computed and the bonded by-pass pair of nodes are scheduled in consecutive execution cycles with a delay of 0 to increase the likelihood that a by-pass can be successfully taken during run-time execution.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Alexander Vasilevskiy, Marcel Mitran
  • Patent number: 7389501
    Abstract: The construction of Static Single Assignment form (SSA) is used as a dynamic conflict graph so that while constructing SSA in linear time, the program being analyzed is simultaneously register allocated. When allocating a register for the symbol, the conflict set is examined so that the register chosen for the symbol is not used by a symbol in the conflict set. When a symbol is register-allocated, the symbol is added to all the conflict set of all live symbols. A live symbol is determined by keeping two counters, called herein a use counter and a use threshold counter. Both counters are initialized when a definition of a symbol is encountered in a block. Both counters are incremented when a use of the symbol is encountered when traversing a block in a depth-first downward traversal. The use count is decremented when a use is detected when traversing the block in an upward traversal.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: June 17, 2008
    Assignee: Microsoft Corporation
    Inventors: Karim T. Farouki, James J. Radigan
  • Patent number: 7367026
    Abstract: A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Kai-Ting Amy Wang, Peng Wu
  • Patent number: 7356802
    Abstract: A method and computer readable medium for automatic replacement of object classes in a library with custom classes to improve program efficiency. The method begins with static analysis preformed on a program containing a plurality of objects in order to determine type-correctness constraints and to detect unused functionality in one or more of the objects to be replaced. The plurality of objects is instrumented to detect usage patterns of functionality in one or more objects. Customized classes are generated based upon the static analysis and usage patterns detected. Bytecode is rewritten which is used for generating classes. The present invention provides transparency in the replacement of the objects.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Bjorn de Sutter, Julian Dolby, Frank Tip
  • Patent number: 7350199
    Abstract: A technique for converting XML code to a binary format involves identifying code elements that appear in the XML code and storing them in an element palette. The XML code is then encoded by selecting predefined commands that represent the XML text-based instructions and associating the predefined commands with references to corresponding code elements in the element palette. The commands and associated references form fixed-length tokens that can be further compressed. During conversion, data is extracted and stored in an uncompressed format. The conversion produces a binary output that contains the element palette, the data, and the tokens (compressed or uncompressed). When the binary form of the XML code is loaded for execution, the tokens are decoded into instructions that operate on the elements referenced in the element palette.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: March 25, 2008
    Assignee: Microsoft Corporation
    Inventors: Yuichi Ito, Paul L. Bleisch
  • Patent number: 7337437
    Abstract: A method, apparatus, and computer program product for determining, in a computer environment, the equivalence, if any, of two algebraic expressions. The expressions are recast into a form of one or more token pairs arranged sequentially in a string, such that each token pair includes an operator followed by an operand. The strings are reduced in accordance with a set of predetermined simplifying rules. The reduced strings are compared by matching, to detect equivalence of the two algebraic expressions. The source code is compiled into object code, wherein the source code includes the two algebraic expressions, and wherein the compiling includes the recasting, the reducing, and the comparing. The method, apparal us, and computer program product may be used in compiler optimisation of source code and like computing tasks.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventor: Rajendra Kumar Bera
  • Publication number: 20080034359
    Abstract: Various technologies and techniques are disclosed that provide software transactional protection of managed pointers. A software transactional memory system interacts with and/or includes a compiler. At compile time, the compiler determines that there are one or more reference arguments in one or more code segments being compiled whose source cannot be recovered. The compiler executes a procedure to select one or more appropriate techniques or combinations thereof for communicating the sources of the referenced variables to the called code segments to ensure the referenced variables can be recovered when needed. Some examples of these techniques include a fattened by-ref technique, a static fattening technique, a dynamic ByRefInfo type technique, and others. One or more combinations of these techniques can be used as appropriate.
    Type: Application
    Filed: August 4, 2006
    Publication date: February 7, 2008
    Applicant: Microsoft Corporation Microsoft Patent Group
    Inventors: John Joseph Duffy, Michael M. Magruder, Goetz Graefe, David Detlefs
  • Patent number: 7313787
    Abstract: Different optimizing methods are applied in response to such a memory hierarchy to which a program mainly accesses when the program is executed. A memory hierarchy to which a program mainly accesses is designated by a user with employment of either a compiler option designation or a designation statement contained in the program. In a compiler, a memory hierarchy designation is analyzed, and an optimizing process according to the designated memory hierarchy is carried out.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: December 25, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Keiko Motokawa, Ichiro Kyushima, Shinichi Ito
  • Publication number: 20070288899
    Abstract: Static and dynamic code analyses are seamlessly, iteratively performed. A software analysis tool integrates the results of dynamic and static analysis and iteratively utilizes results from a previous analysis, or analyses, to augment a current analysis. During a debugging process, information collected at runtime is integrated with static code analysis results. This information is generated and stored as part of the results of the testing and debugging processes. The stored information is subsequently utilized to provide improved analysis results. The software analysis tool eliminates the need for software developers to separately perform static analysis and dynamic analysis.
    Type: Application
    Filed: June 13, 2006
    Publication date: December 13, 2007
    Applicant: Microsoft Corporation
    Inventors: Michael C. Fanning, Nicholas Guerrera
  • Patent number: 7305383
    Abstract: A processing system wherein a bitmap array is first used to obtain an index. The index is used to obtain a value from an array. A predefined default value is used to improve compression and speed in cases where a single default value is often encountered. In this embodiment the size of each entry in the bitmap array is one bit. In another approach, a bitmap array having two bit entries is provided. The use of two bits allows four different entry values. Two values are used to indicate two different default values. A third value is used for a “repeat” indicator to when the last-used next-state value should be re-used. The fourth value is used to indicate indexing into a pointer table, similarly to the embodiment using single-bit entries in the bitmap array.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: December 4, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Blaine Kubesh, Gerald Lathem, Mohit Jaggi, Amit Sinha, Michael Hall
  • Patent number: 7284241
    Abstract: An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: October 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Taketo Heishi, Toshiyuki Sakata, Hajime Ogawa, Ryoko Miyachi, Shuji Miyasaka, Tomokazu Ishikawa
  • Patent number: 7278136
    Abstract: A method, for use in a processor, includes mapping a first data access having less than a predetermined memory footprint to a first memory area, and mapping a second data access having greater than the predetermined memory footprint to a second memory area. The method may also include compiling computer code, inserting annotations into an intermediate representation of the computer code generated during compiling, propagating the annotations from the intermediate representation to a low-level representation of the computer code generated during compiling, and inserting instructions into the low-level representation, the instructions controlling mapping of the first data and the second data.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: October 2, 2007
    Assignee: University of Massachusetts
    Inventors: Csaba Andras Moritz, Mani Krishna, Israel Koren, Osman Sabri Unsal, Saurabh Chheda, Raksit Ashok
  • Patent number: 7275242
    Abstract: The present disclosure relates to whole program analysis and, more particularly, short data optimization obtained through whole program analysis. In one embodiment, short data optimization is achieved by analyzing the program to estimate the size of existing short data and the size of any linkage tables, providing the size estimates to a compiler that is to compile the program, and compiling the program with the compiler in view of the size estimates such that a relatively large amount of data is allocated to a short data area.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 25, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shin-Ming Liu, Dmitry Mikulin, Muralitharan Vijayasundaram, David Xinliang Li
  • Patent number: 7269827
    Abstract: The method and apparatus for compiling high level code is described. A method may be utilized that may include integrating the allocation of registers, scheduling instructions, and selecting code functions to produce an intermediate representation of a high level code segment with scheduled instructions. Additionally, a modular conflict handler may be utilized to resolve register and/or scheduler conflicts as may be required or useful in compiling the high level code. Also, a modular transformation interface may be utilized to invoke analyzers as may be required or useful to generate a compiled version of the high level code.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventor: Markus T. Metzger
  • Patent number: 7269719
    Abstract: Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will execute only if the predicate bit of every register containing a source or destination operand is true, where the predicate bit of the destination register is set to the logical AND of the source registers' predicatest for most instructions. Similarly, in a non-programmable processor synthesized with predicated operand support, an operator will perform the associated function depending on the state of inputs' predicates and the output predicate, which is normally evaluated as the logical AND of the inputs' predicates.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: September 11, 2007
    Assignee: STMicroelectronics, Inc.
    Inventors: Osvaldo Colavin, Davide Rizzo
  • Patent number: 7263693
    Abstract: The present invention is a new method and apparatus to perform combined compilation and verification of platform independent bytecode instruction listings into optimized machine code. More specifically, the present invention creates a new method and apparatus in which bytecode compilation instructions are combined with bytecode verification instructions, producing optimized machine code on the target system in fewer programming steps than traditionally known. The new method, by combining the steps required for traditional bytecode verification and compilation, increases speed and applicability of platform independent bytecode instructions.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: August 28, 2007
    Assignee: Esmertec AG
    Inventor: Beat Heeb
  • Patent number: 7263687
    Abstract: One embodiment of the present invention provides a system that facilitates use of an object-oriented enumerated type within a computer program. During operation, the system receives source code for the computer program, wherein the source code contains a declaration for an enumerated type. This declaration specifies a fixed number of enumeration constants that comprise the enumerated type. Next, the system defines the enumerated type using a class defined within an object-oriented programming language, wherein the class includes a constant for each enumeration constant specified in the declaration. If the declaration additionally contains one or more method declarations, these methods are present on the defined class.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: August 28, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Joshua J. Bloch, Neal M. Gafter
  • Patent number: 7257809
    Abstract: An arrangement is provided for estimating type-cast sets of a program. Type-cast sets of a program are computed with respect to the declared types contained in the program.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Rakesh Ghiya, David C. Sehr
  • Patent number: 7257807
    Abstract: The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: August 14, 2007
    Assignee: LSI Corporation
    Inventors: Andrey A. Nikitin, Alexander E. Andreev
  • Patent number: 7254810
    Abstract: A code optimizer is used to optimize a computer program that references a database by determining the characteristics of the database and making suitable optimizations based on the characteristics of the database. By taking into account the characteristics of a database referenced in the computer program, the optimizer may make suitable optimizations to the computer program. Such optimizations include, without limitation, removing unnecessary calls to the database, removing unnecessary loops, removing unnecessary database operations, providing compile-time errors, and replacing dynamic calls with static data.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Eric Lawrence Barsness, Richard Dean Dettinger, John Matthew Santosuosso
  • Patent number: 7237235
    Abstract: A distribution system for distributing an application from a distribution server to a user terminal through a communication network, in which the distribution server optimizes a program code of the application in question based on execution data indicative of execution conditions of the application in question at the user terminal in question to distribute the obtained application to the user terminal and the user terminal includes a unit for obtaining a program code and execution data of an application from the distribution server to execute the obtained program code based on execution conditions of the application in question indicated in the execution data, and a unit for obtaining execution data of an application being executed to transmit the execution data to the distribution server.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: June 26, 2007
    Assignee: NEC Corporation
    Inventor: Naoto Maeda
  • Patent number: 7210122
    Abstract: A computer system and method for compiling a program, where the program executes pointer assignments from a source object to a destination object, each source object being addressable through a first pointer and each destination object being addressable through a second pointer. The system and method eliminate write barrier code from association with compiled program code when the first pointer points to a source object whose type is prolific, eliminate write barrier code from association with compiled program code when the second pointer points to a destination object whose type is non-prolific, and associate write barrier code with compiled program code when the source object is non-prolific and the destination object is prolific. Additionally, the system and method can determine not to associate write barrier code with a compiled program code if the second pointer points to a destination object whose type is non-prolific and if the first pointer points to a source object whose type is prolific.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: April 24, 2007
    Assignee: International Business Machines, Corporation
    Inventors: Yefim Shuf, Manish Gupta, Rajesh Bordawekar
  • Patent number: 7203935
    Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: April 10, 2007
    Assignee: NEC Corporation
    Inventors: Srimat Chakradhar, Jörg Henkel, Venkata Jakkula, Haris Lekatsas, Murugan Sankaradass
  • Patent number: 7194734
    Abstract: A threaded interpreter executes a program having a series of program instructions stored in a memory. For the execution of a program instruction the threaded interpreter includes a preparatory unit for executing a plurality of preparatory steps making th program instruction available in the threaded interpreter, and an execution unit with one or more machine instructions emulating the program instruction. The threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions. Machine instructions implement a first one of the preparatory steps for execution in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: March 20, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jan Hoogerbrugge, Alexander Augusteijn
  • Patent number: 7185330
    Abstract: A method and system for optimizing computer source code is provided. Prior to compiling the source code, the code is analyzed to determine the occurrence of repeating patterns of code. The repeating patterns of code are replaced with a programming loop that executes a single instance of the pattern multiple times using appropriate array indices and loop increments. In this manner, source code size is reduced making transfer, storage and compiling more efficient.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: February 27, 2007
    Assignee: Xilinx, Inc.
    Inventor: Arthur H. Khu