Abstract: A &PHgr; function provides a mechanism for static single assignment in the presence of predicated code. Guards placed on each source operand of the &PHgr; function indicate the condition under which the corresponding source operand is live and provide correct materialization of the &PHgr; functions after code reordering. For control functions &PHgr;c representing a confluence of live reaching definitions at a join point in the control flow graph, the guards indicate the basic block which is the source of the edge associated with the source operand. The &PHgr;c operands are paired with the source basic block of the incoming edge(s) along which they are live. The operands are also ordered according to a topological ordering of their associated block. This ordering is maintained through subsequent code transformations. In the topological ordering, the source of the edge from which the definition was passed is defined.

Abstract: A method and apparatus for quickly and efficiently generating approximate cross-reference information from source code uses a fuzzy parser in a first pass to process all source code files linearly to resolve cross-references where possible and provide a list of unresolved cross-references and other accumulated knowledge to a separate type resolver. Fast pattern matching is used for the parsing. In a second pass, the type resolver uses this accumulated knowledge which is essentially a class hierarchy, to resolve the type of identifiers using heuristics to make best guesses when required. Separating the fuzzy parser from the type resolver facilitates the process. The method trades absolute accuracy for robustness and speed. This permits the method to be used to parse very large bodies of software.

Abstract: An optimization information attaching apparatus 100 stores a source program including class definitions and a class instruction. The class definitions each include a class, a virtual function and a base class, and the call instruction calls one of the virtual functions. The optimization information attaching apparatus detects a class that is not inherited by another class, and attaches optimization information to the class definition including the detected class. A compiling apparatus 110 reads the call instruction from the source program, judges whether the virtual function belongs to a class that is not inherited by another class by referring to the optimization information in the source program, and generates an executable instruction group for calling the virtual function directly.

Abstract: In general, the invention relates to a method for optimized execution of a computer program including detecting a preservable static field in said computer program with a compiler, comprising detecting at least one selected from the group consisting of a getstatic instruction and a putstatic instruction, annotating said preservable static field to create an annotation indicating whether said field is preservable, compiling said computer program to produce an output using said annotation, wherein said output includes information about said field, encoding said output if backward compatibility is required, loading said output, and executing said output in an environment.

Abstract: An automated method and apparatus for stripping unnecessary information from source code. Processing software receives the source code to be stripped and identifies the code elements and the comment elements to be stripped, which are identified by preprocessor macros and comment flags, respectively. The processing software strips the unnecessary code and comment elements and generates stripped source code that may be provided to a build process for generating release versions of the source code.

Abstract: The present invention eliminates redundant array range checks. A two-phased check is performed, namely a wide range check is performed by combining a plurality of array range checks, and a strict range check is unsuccessful, so as to reduce the number of range checks at execution time and allow execution at high speed. For instance, it is possible with a processor such as PowerPC, by using a flag, to invalidate a code for performing an array range check at high speed without increasing a code size. Consequently, the number of array range checks to be executed can be reduced so as to allow execution at high speed. Also, for instance, a plurality of array range checks can be combined without considering existence of instructions which cause a side effect. Consequently, the number of array range checks to be executed can be reduced so as to allow execution at high speed.

Abstract: The present invention is directed to a system, method and instructions for handling path flow exception and finalization processing in an object oriented programming language. Initially, each instrumentation method is checked for a code to indicated an exception being thrown. A hook is inserted before the exception code and identifies the method throwing the exception. Methods must also be checked for exception tables. When an exception table is found, then a hook is inserted at the entry point of each exception handler for every entry in the exception table. This hook identifies the method which catches the exception.

Abstract: In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow information in SSA form. The scheduler-assigner also includes a rotating register allocator that designates live ranges of loop-variant variables in the first software-pipelined instruction schedule as being allocated to rotating registers, when available. The first software-pipelined instruction schedule may be a modulo schedule. When a rotating register is not available, the software-pipelined instruction scheduler may generate a second software-pipelined instruction schedule having an initiation interval greater than the initiation interval of the first software-pipelined instruction schedule.

Abstract: In accordance with methods and systems consistent with the present invention, a system that automatically generates Fortran 90 interfaces to Fortran 77 code is provided. These interfaces provide for the use of optional parameters and, because they are written in Fortran 90, also allow for parameter checking. These interfaces are automatically generated to allow a programmer to reap the benefits of Fortran 90 calling without having to rewrite the Fortran 77 underlying code. When generating the interfaces, the method performs an optimization that saves a significant amount of processing time as well as a significant amount of memory. This optimization involves generating the interfaces in such a way as to prevent the compiler from performing a gather and a scatter.

Abstract: The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is performed by Just-In-Time compiler. For instance, the instructions lining in order from instruction E1 which was moved forward to instruction S2which had been located before E1 is registered as interrupt inhibited section R1, and from instruction S4 which was moved forward to instruction S3 which had been located before S4 is registered as interrupt inhibited section R2 (S is an instruction which has an affect observable from the outside at the execution, and E is an instruction which may cause an exception). Also, in FIG. 7, S4 which was an instruction behind E1 in the original order is registered as R1's instruction invalid at an exception. If E1 causes an exception, an interrupt handler is activated and the instructions of interrupt inhibited section R1 are copied to another area.

Abstract: There is provided a method for enhancing source code for execution on a computer platform that has a capability to employ a memory file. The method includes the steps of recognizing an occurrence of a first instruction in the source code that does not utilize the capability, and supplementing the source code with a second instruction that utilizes the capability.

Abstract: An instruction string optimization apparatus is provided which estimates the size of a constant to be resolved as an address difference before linking instructions. The apparatus comprises code dividing means (202) for dividing a serial assembler code (201) into basic blocks, size dependence relation generation means (204) for analyzing size dependence relations among the sizes of the instruction string between basic blocks, estimation order determining means (206) for determining the order of basic blocks in which the size of a constant to be resolved as an address difference is determined and size determining means (208) for determining the size of the constant in each basic block according to the determined order, whereby the size of a constant to be resolved as an address difference can be estimated to be a value close to and not less than its actual size, the number of codes can be reduced, and the process speed by a linker can be improved.

Abstract: A method and system for customizing the transformation of an object-oriented database to and from a grammatical form. A grammatical form is an expression of an object-oriented database in a textual form according to a grammar. The transformation customizer is a plug-in which provides translation of primitive data types to and from complex data types for compilation and serialization processes. A complex data type is defined in terms of one or more primitive data types. One or more values in the object-oriented database are expressed in terms of the complex data type. During serialization, the plug-in module is invoked. The plug-in understands both the complex data type and the primitive data types. The values from the object-oriented database are translated from the complex data type to the primitive data types. For customizing compilation, one or more values expressed in terms of the primitive data types are translated to the complex data type when the plug-in is invoked.

Abstract: An output translator provides for cross module representations of components within a heterogeneous program by translating modifying a platform-neutral intermediate representation (IR) of the program into platform-specific instructions for different architectures. The intermediate representation is hierarchy of base elements that correspond to instructions, code blocks, procedures and components within the program. Blocks of instructions that were originally written for one architecture can be translated from the intermediate representation into platform-specific instructions for a different architecture. The output translator provides any necessary code to interface contiguous code blocks that are emitted in different instruction sets.

Abstract: An embodiment of the invention includes, parsing a source code, performing a plurality of optimizations on the parsed code, generating a plurality of configuration instruction sets based on the optimized source code and automatically selecting one of the plurality of generated configuration instruction sets according to a user defined criteria, the selected configuration instruction set being used to configure hardware.

Abstract: A method and system for serializing a transient object-oriented database into a persistent form. The persistent form is a grammatical form, an expression of an object-oriented database in a textual form according to a grammar. The grammatical form is human-readable and human-editable. The grammar is designed to be platform-independent and programming-language-independent and therefore descriptive of any hierarchical object-oriented database. An object-oriented database is expressed as a plurality of entries in a transient, hierarchical, object-oriented form. The tree of entries is navigated and each entry is written to the persistent form as text according to the grammar. The serialized form stores only the key state of the database, not a “snapshot” of memory. Therefore, the persistent, serialized form is smaller than the in-memory, transient form of the object-oriented database.

Abstract: Embodiments of the invention generally provide a method, article of manufacture, and apparatus for code transformation. In one embodiment, the invention provides a method of transforming source code. The method determines if a source code statement includes a first operation that receives input from a result of a second operation, where the second operation acts on a plurality of arguments. If the source code includes the first operation, then the method transforms the source code into a plurality of statements that include the first operation acting on one of the arguments.

Abstract: A method and system for compiling a grammatical form of an object-oriented database into an intermediate form of that database. The grammatical form is a persistent form of an object-oriented database expressed in a human-readable and human-editable textual form according to a grammar. The textual form is parsed into a series of tokens. The tokens are compiled into a plurality of entries. The plurality of entries are expressed in an intermediate form. The intermediate form comprises an array of intelligent entry objects which encapsulate data with methods for manipulating that data. The methods include creating a database entry, creating a property associated with an entry, creating an attribute associated with an entry or property, querying the last entry, property, or attribute created, and finalizing entry storage. The intermediate form lacks the infrastructure of the database, but the intermediate form can be used to populate the object-oriented database with entries.

Abstract: An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.

Abstract: An assembly code performance evaluation apparatus is provided which includes a host computer, a target digital signal processor (DSP) compiler, and a performance estimation program. The host computer includes processing circuitry, memory and a host compiler to use test sequences and generate dynamic information. The target digital signal processor compiler communicates with the processing circuitry. The performance estimation program is implemented on the host processing circuitry and is operative to annotate application source code and to generate an estimation of an optimized assembly code. A method is also provided.

Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.

Abstract: An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.

Abstract: This invention provides for the implementation of dynamic “event to method” adapter class generation. Event to method adapter classes and objects are automatically and dynamically generated and wired to source and target objects as required using a runtime environments language such as the Beans Markup Language (BML). Adapter classes and objects are automatically and dynamically generated as required while the application program loads and runs. Dynamically generated classes and objects need to exist only at the time that a running application calls for the adapters use, and can be dynamically modified or exchanged in order to optimize the running application or modify application functionality.

Abstract: The invention provides a method and apparatus for optimizing code. Embodiments of the present invention comprise, for each expression in an intermediate program representation, transparently forwarding definitions of variables in said expression as said expression is being parsed by a term rewriter, the intermediate program representation being left unchanged; determining whether a term rewriting rule exists in the term rewriter for said expression; and rewriting said expression in the intermediate program representation according to said rule.

Abstract: Consider a set of functions, each of whose calculations are almost identical. A common example is the set of trigonometric functions sine, cosine, and tangent. Each of these functions is computed by first performing argument reduction and some preliminary calculations, which are identical for all members of the set. A few unique instructions are performed at the end for each of the functions in the set. Normally, when such functions are encountered, a separate sequence of instructions is called for each function even if the functions appear in close proximity. This results in duplicate instructions being performed which increases execution time and length of compiled program. Specialized functions exists to minimize execution, but programs with such specialized function calls suffer from non-portability. The present invention includes a method and a system to optimize function calls for faster execution while maintaining portability.

Abstract: A compare sequence is executed at least once, and the results of that execution are used to modify the compare sequence for a subsequent execution of the compare sequence. In a preferred embodiment, the compare sequence is modified by placing the TRUE compare statement of the previous execution at the beginning of the compare sequence. In another preferred embodiment, the compare sequence is reordered in descending order of the number of TRUE compares associated with each compare statement. The compare sequence may be immediately modified after each successful compare, or the customer may define external sampling periods for modification of the compare sequences. The modification may be a single program modification of compare structures for delayed modification or a global modification of programs for delayed modification.

Abstract: A method and apparatus for optimizing scheduling of a block of program instructions to remove a condition resolving instruction from the critical path where the resolution of a condition controls the selection between input results, generated by predecessor operations, by a merge operation which passes the selected result to a successor operation. In a preferred embodiment, the successor operation is “unzipped” by duplicating the successor operations, providing predecessor results directly to the, duplicated successor operations, and scheduling the duplicated successor operations prior to the merge.

Abstract: A compiler includes a real register allocation stage, an optimization stage and a final code stage. The real register allocation stage is configured to generate intermediate code from a basic block of source code. Physical registers, instead of virtual registers, are allocated to operands from the generated intermediate code, and the operands are stored in the physical registers. Then, the intermediate code is optimized, and machine readable code is generated from the intermediated code using the optimized registers in the final code stage. By allocating physical registers in the front-end of the compiler, instead of just prior to generating the machine-readable code, compiling time and memory needed for compiling source code is reduced.

Abstract: The instructions in a computer program are converted into a form of weakest precondition so as to produce a verification condition that is to be evaluated by a theorem prover. In generating the weakest precondition, labels are introduced for values of variables at control join points. In two preferred embodiments, the computer program is converted into a set of guarded commands prior to the application of weakest precondition operators. In one embodiment, as part of the process of generating the verification condition, assignment commands that assign values to variables are removed from the program through use of a “dynamic single assumption” technique. In another embodiment, the weakest precondition is expressed in terms of strongest postconditions. In both embodiments, a simplified verification condition is produced in which duplications of sets of instructions following a choice operator is avoided.

Abstract: A method and several variants for using information about the scope of access of objects acted upon by mutual exclusion, or mutex, locks to transform a computer program by eliminating locking operations from the program or simplifying the locking operations, while strictly performing the semantics of the original program. In particular, if it can be determined by a compiler that the object locked can only be accessed by a single thread it is not necessary to perform the “acquire” or “release” part of the locking operation, and only its side effects must be performed. Likewise, if it can be determined that the side effects of a locking operation acting on a variable which is locked in multiple threads are not needed, then only the locking operation, and not the side effects, needs to be performed.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Improved techniques for representing Java objects as strings are disclosed. An inventive Java Bytecode instruction suitable for execution by a Java virtual machine is disclosed. The inventive Java Bytecode instruction can be executed by a Java virtual machine to represent Java objects as strings. Moreover, Java objects can be represented as strings without invoking the Java “to_string” method which is conventionally used. This means that the costly overhead associated with repeatedly invoking Java method “to_string” is avoided. In other words, operations that are conventionally performed each time the Java “to_string” method is invoked need not be performed. As a result, the performance of virtual machines, especially those operating with limited resources (e.g., embedded systems) can be improved.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.

Abstract: The inventive mechanism operates to optimize program efficiency in a two phase process. In the first phase, the mechanism conducts a dependency analysis on the instructions to determine dependency relationships between the various instructions in an instruction window. The mechanism thereby identifies candidates for register renaming and instruction speculation, and provisionally performs the renaming and speculation operations, while preserving information which is preferably used to reverse these operations in the second phase if it is determined that the operations may be effectively rescheduled. In the second phase, the mechanism determines whether the optimizing operations, renaming and speculation, were beneficial in each case. Each instruction for which the mechanism finds the optimizing operation to be beneficial will generally remain in optimized form. Optimizing operations found not be beneficial are generally reversed by the mechanism.

Abstract: Register allocation during computer program code compilation is accomplished by determining a set of spill candidates, by evaluating a cost function for each spill candidate using a plurality of spill strategies, and by selecting the spill candidate having the lowest cost function value. Preferably, the set of possible spill candidates is determined by the Chaitin method of constructing an interference graph of all live ranges of symbolic registers, and iteratively removing nodes and placing them on a stack. Preferably, multiple spill strategies are represented as varying numbers of deaths N of live ranges of other symbolic registers, a spill strategy N signifying that spill code is introduced whenever the number of deaths occurring between two successive uses of a symbolic register equals or exceeds N. In the preferred embodiment, the cost is a function of the number, type and frequency of each operation introduced by the spill, and is divided by a benefit factor represented as the degree of the node.

Abstract: The present application discloses an instruction format for storing multiple microprocessor instructions as one combined instruction. The instruction format includes a combination opcode field for storing a combination opcode that identifies a combination of the multiple instructions. The application also discloses an instruction format that uses prefix fields to specify the destination functional block for each combined instruction stored in an execute packet. A compiler program or an assembler program obtains from a table a combination opcode that corresponds to a combination of the multiple instructions. The table stores combination opcodes and their corresponding combinations of instructions. The compiler program or assembler program then assigns the found combination opcode to an opcode field of the combined instruction. In a trivial scenario, a single instruction can also be stored as a combined instruction.

Abstract: A method, article of manufacture, and apparatus for displaying compiler optimized source code. Initially, an optimized source code is generated for an original source code. The optimized source code is displayed on an output device to visually indicate a change performed to the original source code in accordance to a compiler optimization.

Abstract: A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of the processor types compared with generating a non-customized version. If a performance advantage would be achieved, the method generates at least one customized object code version and a non-customized version for the source code segment, and it generates a control section that causes one of the object code versions to be called during execution of the object code in accordance with an executing processor's processor type. If no performance advantage would be achieved, the method generates a non-customized version of the object code that can be executed by any of the different processor types.

Abstract: High level program files are compiled into an efficient machine readable output file by using an optimizer that processes program files into intermediate files and reprocesses the intermediate files extracting necessary information to maintain. Information is provided in intermediate files that relate to dependency and interrelationships between target files that are to be compiled. If program files are modified and the compilation process must be re-done, interrelationship content is maintained to allow files to be compiled with undue calculations.

Abstract: A scalar register promotion using static single assignment representation (SRP-SSAR) system and method are used in a compiler for optimizing compilation of source code. This optimization uses a promotion algorithm that is profile-driven and is based on the scope of intervals and works on static single representation of a program. The SRP-SSAR system comprises logic which promotes variables that hold scalar values and inserts loads and stores in an enclosing program interval (often natural loops). The system relies on recursive promotion of the outer program interval to propagate these loads and stores to the appropriate program interval. This logic exists in computer memory and is invoked by a user to compile source code into executable code. Use of the present invention significantly reduces memory operations, thereby increasing efficiency.

Abstract: A method and apparatus for distinguishing reference values from non-reference values in a runtime environment is described. A set of volatile registers and a set of non-volatile registers are statically determined. The set of volatile registers is partitioned into reference and non-reference register partitions statically. The set of non-volatile registers is partitioned into reference and non-reference partitions dynamically.

Abstract: A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of the processor types compared with generating a non-customized version. If a performance advantage would be achieved, the method generates at least one customized object code version and a non-customized version for the source code segment, and it generates a control section that causes one of the object code versions to be called during execution of the object code in accordance with an executing processor's processor type. If no performance advantage would be achieved, the method generates a non-customized version of the object code that can be executed by any of the different processor types.

Abstract: Computer method and apparatus allows instrumentation of program modules while maintaining exception-handling unwinding context. In the case of instrumenting procedure prologues, the invention preserves the calling context. A sanitized copy of the prologue and rewind instructions to reverse the effects of duplicate prologue instructions are employed.

Abstract: A compiler having one or more separate components, each of which contains the source code of the compiler which is responsible for implementing a corresponding data representation. These components are responsible for all of the parts of compilation which depend on the corresponding data representation. In one aspect of the present invention, a compiler comprises: a converter for converting program code to object code; and a data representation implementor for isolating within the compiler information that relates to representation of data at runtime, wherein the converter accesses the data representation implementor to obtain information that is needed for converting any portion of the program code that is dependent on representation of data at runtime.

Abstract: One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

Abstract: A method and apparatus for optimizing performance of a method. A method is loaded and verified in a virtual machine. Prior to execution of the method, elements of the method are analyzed for optimization according to a policy. Responsive to identifying elements that can be optimized according to the policy, the elements are optimized following the policy and the method is then executed.

Abstract: A method for optimizing bytecode in the presence of try-catch blocks comprises generating an Intermediate Representation of the bytecode, scanning each basic block of the bytecode to identify try blocks, scanning each basic block of the bytecode to identify try-blocks, splitting each try-block into a first half and a second half at the first statement that can throw an exception, establishing an edge between the first half and the second half of each try-block, between the first half and the catch block, and between the catch block and the basic block subsequent to the second half of each try-block.

Abstract: The invention relates to a computer program interpreter and a method for the same, using statistics to group (SR89, SR17 . . . SR6; SR4, SR34 . . . SR16) frequently used service routines (SR) in the same program function and to control encoding of instructions. Frequently used service routines are assigned shorter codes thus enhancing the performance of a simulator or emulator.

Abstract: A compiling method, for compiling a source program into an object program for a CPU having multiple functional units that allow for concurrent operations and supporting predicated execution, for generating the object program that can be executed on the CPU at high speed by analyzing the source program and generating intermediate codes, making an analysis of the intermediate codes, generating, based on the analysis, an execution mode set instruction to set an execution mode managed within the CPU, allocating, based on the analysis, instructions such that whether they are to be executed or not to be executed depends on the execution mode set by the execution mode set instruction from the intermediate codes, wherein one or more instructions in which values in their respective specific fields are identical make an block together for every value in the specific field, finding, for each block, an ending part of the block in which its last instruction is allocated, and generating, when the ending part of a certain b