Static (source Or Intermediate Level) Patents (Class 717/152)
  • Patent number: 7181730
    Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: February 20, 2007
    Assignee: Altera Corporation
    Inventors: Nikos P. Pitsianis, Benjamin Strautin, Sanjay Banerjee, Gerald G. Pechanek
  • Patent number: 7171657
    Abstract: One embodiment of the present invention provides a system that facilitates importing static members of a class. During operation, the system examines code associated with a compilation unit to locate a static import declaration that identifies one or more static members of the class to import. Upon finding such a static import declaration, the system records the static import declaration in a symbol table used to compile the compilation unit. This allows the names for the one or more static members of the class to appear within the compilation unit without being prefixed with a name for the class.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: January 30, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Joshua J. Bloch, Guy L. Steele
  • Patent number: 7159212
    Abstract: Art asset rendering systems and methods in which pre-processing is performed in a compilation process. Geometric data are processed in the compilation process with knowledge of associated shading programs. The data are converted into data structures targeted directly to a target hardware platform, and a code stream is assembled that describes the manipulations required to render these data structures. The compiler includes a front end configured to read the geometric data and attributes (an art asset) output from a 3D modeling package and shaders in a platform independent form and perform platform-independent optimizations, and a back end configured to perform platform-specific optimizations and generate platform-targeted data structures and code streams.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: January 2, 2007
    Assignee: Electronic Arts Inc.
    Inventors: Eric Schenk, Paul Lalonde
  • Patent number: 7152223
    Abstract: Methods and systems are provided for expressing one or more associations between source language declarations and implementations in a language neutral fashion. A determination is made as to whether a source language association rule related to a declaration is different from a default association rule for a target runtime. If so, an override association is expressed between the declaration and the implementation, and if not, a default association is expressed. Methods and systems are also provided for interpreting an association between a declaration and an implementation in a runtime system, wherein a determination is made as to whether the association comprises an override association. If so, the association is interpreted according to an override association rule for the runtime system, and if not, the association is interpreted according to a default association rule.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: December 19, 2006
    Assignee: Microsoft Corporation
    Inventors: Christopher W. Brumme, James H. Hogg, Craig T. Sinclair
  • Patent number: 7140006
    Abstract: The invention provides a method and apparatus for optimizing code. Embodiments of the present invention comprise, for each expression in an intermediate program representation, transparently forwarding definitions of variables in said expression as said expression is being parsed by a term rewriter, the intermediate program representation being left unchanged; determining whether a term rewriting rule exists in the term rewriter for said expression; and rewriting said expression in the intermediate program representation according to said rule.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Williams L. Harrison, III, Cotton Seed
  • Patent number: 7127710
    Abstract: In one embodiment, disambiguation of memory references, such as structure field accesses, of a computer program is performed. Disambiguation may be effected by identifying pure pointer variables within the computer program and applying at least one disambiguation rule to memory references associated with the pure pointers to determine whether the references are disjoint.
    Type: Grant
    Filed: June 24, 2002
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Rakesh Ghiya, Daniel Lavery, David Sehr
  • Patent number: 7111289
    Abstract: A method is disclosed for free memory allocation in a linked list memory scheme. Free lists are link lists designating available memory for data storage. This method leverages the ability to read memory while concurrently updating a pointer to the next location. Multiple free lists are used to reduce the number of cycles necessary to allocate memory. The number of entries in each free list is tracked. When memory becomes available, it is spliced into the shortest free list to achieve balance between the free lists. The free list structure disclosed consists of head, head +1, and tail pointers where head +1 is the next logical address pointed to from the head pointer location. The free list consists only of the head and tail pointers. Each link list structure of memory to be freed contains the head, head +1, and tail pointers. This allows us to simultaneously allocate and free with only 1 memory cycle.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: September 19, 2006
    Assignee: Agere Systems, Inc.
    Inventors: Christopher Koob, David P. Sonnier
  • Patent number: 7103883
    Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: September 5, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Alan L. Davis, Jonathan F. Humphreys, Todd M. Snider
  • Patent number: 7086043
    Abstract: A superblock unroller creates a superblock in a first instruction stream, and unrolls the superblock using different methods depending on the suitability of the superblock to different types of unrolling. The superblock unroller uses complete unrolling if a number of iterations of the superblock is sufficiently small and if the number of iterations is known at compile-time. The superblock unroller uses static unrolling if the number of iterations of the superblock is too large for complete unrolling and if the number of iterations is known at compile-time. The superblock unroller uses dynamic unrolling if the number of iterations of the superblock is unknown at compile-time. Each of these unrolling methods may include the insertion of count rectification code into the first instruction stream to account for execution that exits the superblock. Code performance may be improved by providing the sophisticated unrolling of superblocks disclosed herein.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Robert Ralph Roediger, William Jon Schmidt, Peter Jerome Steinmetz
  • Patent number: 7086046
    Abstract: A method, article of manufacture, and apparatus for displaying compiler optimized source code. Initially, an optimized source code is generated for an original source code. The optimized source code is displayed on an output device to visually indicate a change performed to the original source code in accordance to a compiler optimization.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Eric Lawrence Barsness, John Matthew Santosuosso
  • Patent number: 7073167
    Abstract: A compiler has a detection unit, a conversion unit, and a expansion unit. The detection unit detects a predetermined target from an input source program. The conversion unit converts the target detected by the detection unit into a procedure call. The expansion unit generates an online code describing a definition of a procedure to be called by the procedure call obtained by the detection unit. The compiler outputs a program in which the target detected by the detection unit is replaced with a procedure call, and an online code corresponding to the procedure call.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: July 4, 2006
    Assignee: Fujitsu Limited
    Inventor: Hidetoshi Iwashita
  • Patent number: 7065747
    Abstract: An enhanced Java Bytecode verifier suitable for operation in a Java computing environment is disclosed. The enhanced Java Bytecode verifier operates to determine whether one or more Java conventional Bytecode commands within a stream of Bytecodes are likely to place a reference to a Java object on the execution stack. In one embodiment, the conventional Java Bytecode commands identified as such are translated by the enhanced Java Bytecode verifier into one or more corresponding Java commands. When a corresponding command is executed, the reference associated with the conventional Java command is placed on a reference stack as well as the execution stack.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: June 20, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Stepan Sokolov, David Wallman
  • Patent number: 7065757
    Abstract: Consider a set of functions, each of whose calculations are almost identical. A common example is the set of trigonometric functions sine, cosine, and tangent. Each of these functions is computed by first performing argument reduction and some preliminary calculations, which are identical for all members of the set. A few unique instructions are performed at the end for each of the functions in the set. Normally, when such functions are encountered, a separate sequence of instructions is called for each function even if the functions appear in close proximity. This results in duplicate instructions being performed which increases execution time and length of compiled program. Specialized functions exists to minimize execution, but programs with such specialized function calls suffer from non-portability. The present invention includes a method and a system to optimize function calls for faster execution while maintaining portability.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: June 20, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter Markstein, James Thomas, Kevin Crozier
  • Patent number: 7062761
    Abstract: Systems and methods are provided for writing code to access data arrays. One aspect provides a method of accessing a memory array. Data is provided within a one-dimensional array of allocated memory. A dimensional dynamic overlay is declared from within a block of statements, and the declaration initializes various attributes within an array attribute storage object. The data is accessed from within the block of statements as a dimensional indexed array using the array attribute storage object. Another aspect provides a method of creating and accessing a dimensional dynamic array. A dimensional dynamic array is declared from within a block of statements, and memory storage for the array is dynamically allocated. A dynamic overlay storage object is also provided and its attributes are initialized from the dynamic array declaration. The data is accessed as a dimensional indexed array from within the block of statements using the array attribute storage object.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: June 13, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Keith R Slavin, Shane C. Hu
  • Patent number: 7058932
    Abstract: An emulation system, computer program product, and method for emulating the execution of a target program comprising instructions of an instruction set of a target computer on a host computer having a different instruction set operate by performing a static translation of the instructions of the target program into a series of instructions of an intermediate instruction set, the intermediate instruction set being optimized for interpretation on the host computer, and then executing the series of instructions of the intermediate instruction set by interpretation on the host computer.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: June 6, 2006
    Assignee: Unisys Corporation
    Inventors: Andrew T. Jennings, G. Lawrence Krablin, Timothy Neilson Fender, William Stratton
  • Patent number: 7032216
    Abstract: Fragile native compilation of virtual machine code is described, in which a native code optimizer inspects external code entities such as Java base classes and emits target code based on an inter-procedural analysis of the code and data structure invariants and other properties of the external code entity. The fragile compiler also records which properties of the external code entities were used to produce the optimized code in a “fragile set”, so that the virtual machine at which the compiled code is deployed and executed can detect if the recorded properties of the external code entities are compatible with the properties of the corresponding entities on the deployment virtual machine. If the code entities are incompatible, the compiled native code is rejected and the virtual machine reverts to interpreting the virtual machine code.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: April 18, 2006
    Assignee: Oracle International Corporation
    Inventor: Dmitry Nizhegorodov
  • Patent number: 7028293
    Abstract: Indirect method invocation of methods that only return constant values is optimized using fetching operations and return constant tables. Such method calls can be optimized if all possible method calls via the call site instruction return a constant value and have no side effects. Each constant return value is loaded from a return constant table, and method invocation is eliminated. If all possible target methods in a program result in a constant return value and have no side effects, an associated virtual function dispatch table (vtable) may be used as the return constant table. Furthermore, control operation optimization may be applied to identify type constraints, based on one or more possible type-dependent constant return values from an indirect method invocation. An optimizer identifies and maps between a restricted set of values and an associated restricted set of types on which execution code may operate relative to a given control operation.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 11, 2006
    Assignee: Microsoft Corporation
    Inventor: Erik S. Ruf
  • Patent number: 7000213
    Abstract: Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: February 14, 2006
    Assignee: Northwestern University
    Inventors: Prithviraj Banerjee, Alok Choudhary, Malay Haldar, Anshuman Nayak
  • Patent number: 7000227
    Abstract: An optimizing compiler and method thereof performs a sequence of optimizing changes to an intermediate language representation of a routine, and measures an execution characteristic of each optimization, such as a timing of the machine language representation performed on an architecture similar to the target machine using a user selectable initialization state. The sequence of optimizations is selected according to a criterion that includes a lexicographic search and other methods. The pre-optimized code is also broken into segments wherein discrete optimizations are performed on each segment and measured using a user provided routine. The target routine is tested with the object code in main memory if not the cache if possible and optimizations are chosen only if they improve the target subroutine according to the user defined metric. After a stopping criterion is achieved, the most optimized code is selected.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventor: Gregory Henry
  • Patent number: 6986128
    Abstract: A method for dynamic recompilation of source software instructions for execution by a target processor, which considers not only the specific source instructions, but also the intent and purpose of the instructions, to translate and optimize a set of equivalent code for the target processor. The dynamic recompiler determines what the source operation code is trying to accomplish and the optimum way of doing it at the target processor, in an “interpolative” and context sensitive fashion. The source instructions are processed in blocks of varying sizes by the dynamic recompiler, which considers the instructions that come before and after a current instruction to determine the most efficient approach out of several available approaches for encoding the operation code for the target processor to perform the equivalent tasks specified by the source instructions. The dynamic compiler comprises a decoding stage, an optimization stage and an encoding stage.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: January 10, 2006
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Randal N. Linden
  • Patent number: 6973646
    Abstract: This invention describes a method and several variants for compiling programs or components of programs in a mixed static and dynamic environment, so as to reduce the amount of time and memory spent in run-time compilation, or to exercise greater control over testing of the executable code for the program, or both. The invention involves generating persistent code images prior to program execution based on static compilation or dynamic compilation from a previous run, and then, adapting those images during program execution. We describe a method for generating auxiliary information in addition to the executable code that is recorded in the persistent code image. Further, we describe a method for checking the validity of those code images, adapting those images to the new execution context, and generating new executable code to respond to dynamic events, during program execution.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Rajesh Bordawekar, Manish Gupta, Samuel Pratt Midkiff, Mauricio J. Serrano
  • Patent number: 6973648
    Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Tatsushi Inagaki, Hideaki Komatsu, Akira Koseki
  • Patent number: 6966056
    Abstract: A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: November 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenichi Kawaguchi
  • Patent number: 6964043
    Abstract: The present invention relates to a method, apparatus, and system to optimize frequently executed code and to use compiler transformation and hardware support to handle infrequently executed code. The method includes compiling a computer program. The method further includes improving performance of the computer program by optimizing frequently executed code and using compiler transformation to handle infrequently executed code with hardware support. The method also includes storing temporarily the results produced during execution of a region to improve performance of the computer program. The method additionally includes committing the results produced when the execution of the region is completed successfully.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: November 8, 2005
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Li-Ling Chen
  • Patent number: 6952821
    Abstract: A system and method of automatically configuring memory in a data processing system, including the steps of: receiving source code containing a loop nest, wherein the loop nest includes data arrays with affine indexes; optimizing source code by relocating elements from a first array in memory to a second array in memory; and executing the optimized source code.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 4, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Robert S. Schreiber
  • Patent number: 6952820
    Abstract: The invention concerns a data compaction method and system for an intermediate program. The method consists in searching the program (1000) for identical sequences (Si) and counting Ni number of occurrences of each sequence (Si), a comparison test (1001) to find the superiority of a function f(Ni) to a reference value enables to generate (1003) a specific instruction of a specific code (Ci) with which the sequence (Si) is associated, replacing (1004) each occurrence in the sequence (Si) by the specific code (Ci) in the intermediate program to create a compacted intermediate program (FCC) with which an executing file (FEX) is associated. The invention is applicable to multiple application portable objects such as microprocessor cards, onboard systems of the like.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: October 4, 2005
    Assignees: Bull CP8, INRIA-Institut National de la Recherche en Informatique et en Automatique
    Inventors: Ulrik Pagh Schultz, Gilles Muller, Charles Consel, Lars Clausen, Christian Goire
  • Patent number: 6934939
    Abstract: A method is disclosed for instructing a computing system to unwind a program call stack that lacks explicit Stack Frame Backchain Pointers, including finding the called function's entry point, determining the return point in the calling function, placing a NOP instruction at the return point that contains embedded information about what type of call was used, and backing up in storage by an amount determined by using the address of the called function's entry point to locate the static data item containing the called function's DSA size.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: Graham W. Ewart, Hans E. Boettiger, Patricia A. Healy, James T. Mulvey, Gregory T. Reid, David J. Sudlik
  • Patent number: 6934940
    Abstract: Embodiments of the invention generally provide a method, article of manufacture, and apparatus for code transformation. In one embodiment, the invention provides a method of transforming source code. The method determines if a source code statement includes a first operation that receives input from a result of a second operation, where the second operation acts on a plurality of arguments. If the source code includes the first operation, then the method transforms the source code into a plurality of statements that include the first operation acting on one of the arguments.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: Cary Lee Bates, John Matthew Santosuosso
  • Patent number: 6898787
    Abstract: A ? function provides a mechanism for static single assignment in the presence of predicated code. Guards placed on each source operand of the ? function indicate the condition under which the corresponding source operand is live and provide correct materialization of the ? functions after code reordering. For control functions ?c representing a confluence of live reaching definitions at a join point in the control flow graph, the guards indicate the basic block which is the source of the edge associated with the source operand. The ?c operands are paired with the source basic block of the incoming edge(s) along which they are live. The operands are also ordered according to a topological ordering of their associated block. This ordering is maintained through subsequent code transformations. In the topological ordering, the source of the edge from which the definition was passed is defined.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: May 24, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Carol Linda Thompson, Vatsa Santhanam, Dz-Ching Ju, Vasanth Bala
  • Patent number: 6865730
    Abstract: A method is provided for analyzing an object oriented program that supports dynamic class loading. A set A of classes in the program is identified, wherein each class within set A is capable of, during execution of the program, causing the loading of a class outside of set A. A first set of method calls belonging to the classes in set A are identified that, during execution of the program, are capable of calling only methods belonging to a class within set A. A second set of method calls belonging to the classes in set A are identified that, during execution of the program, are capable of calling methods belonging to a class outside set A. Data that identifies the first and the second set of method calls is stored for subsequent use.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Michael G. Burke, Jong-Deok Choi, Vugranam C. Sreedhar
  • Patent number: 6823507
    Abstract: A method, an apparatus, and a computer program product are disclosed for detecting memory-related errors in a computer program during compiling of the computer program. In the method, static analysis is performed upon a computer program. One or more conditions in the computer program are computed based on the static analysis. Each condition is a test for checking a memory access in the computer program and can be either a pre- or post-condition. The validity of each condition in the computer program is then evaluated. If the evaluation is determinate during compiling, the presence or absence of memory-related errors in the computer program is reported. A condition is determinate if the condition is valid or invalid during compiling. Otherwise, computer code based on the condition is generated for incorporation in the computer program for run-time detection of memory-related errors.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ravi Srinivasan, Usha Kiran, Navin Kumar Sinha
  • Patent number: 6820256
    Abstract: Defect detection in a software system made of multiple computer program programs is facilitated by using information about cross-program interactions and dependency relationships between programs to analyze the individual programs in such a way that the behavior of the system as a whole is accurately represented. A list of dependency relationships is read in; these dependency relationships are used to determine an order in which the programs should be analyzed. The programs are then analyzed in that order. Information from the analysis of the programs is used to inform the analysis of subsequently-analyzed programs.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: November 16, 2004
    Assignee: Microsoft Corporation
    Inventors: Timothy G. Fleehart, Jonathan D. Pincus, Jeffrey S. Wallace
  • Publication number: 20040221277
    Abstract: An improved architecture for a program code conversion apparatus and method for generating intermediate representations for program code conversion. The program code conversion apparatus determines which types of IR nodes to generate in an intermediate representation of subject code to be translated. Depending upon the particular subject and target computing environments involved in the conversion, the program code conversion apparatus utilizes either base nodes, complex nodes, polymorphic nodes, and architecture specific nodes, or some combination thereof, in generating the intermediate representation.
    Type: Application
    Filed: December 8, 2003
    Publication date: November 4, 2004
    Inventors: Daniel Owen, Jonathan Jay Andrews, Miles Philip Howson, David Haikney
  • Publication number: 20040205738
    Abstract: An object of the present invention is to enable parts of a source program having a large number of executions, or parts having a high possibility of a large number of executions, to be extracted with good precision and compiled preferentially. In S11, a loop having a multi-nested structure or a single-nested structure is searched for in a main program. In S14, another program that is being called from within this loop is detected. In S15, a loop having a multi-nested structure or a single-nested structure is searched for in the callee program. In S17, the total number of nests in the loops detected so far is calculated as the loop depth. In other words, in S17 the degree of multiplicity in all of the loops forming a multi-nested structure over a plurality of programs having a calling relationship is calculated as the loop depth. In S20, the loop having the greatest loop depth is included in the parts to be compiled preferentially. In S21, only the parts determined as parts to be compiled are compiled.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 14, 2004
    Inventors: Takehiro Yoshida, Takuji Kawamoto
  • Publication number: 20040194075
    Abstract: A distributed make command is used when compiling a computer program in order to allow non-dependent processes in the compiling be performed in parallel, such as with different resources, in order to speed compile time. The distributed make command is typically executed by a user who also specifies a maximum number of resources to allocate to the compiling. The present invention dynamically adjusts this maximum number of resources to allocate if the resources become overloaded during the compiling, which has the effect of optimizing the efficiency of the compiling, either by reducing the number of resources utilized or by reducing the amount of time the compiling takes (or both).
    Type: Application
    Filed: March 26, 2003
    Publication date: September 30, 2004
    Applicant: Sun Microsystems, Inc., a Delaware Corporation
    Inventors: Nikolay Molchanov, Raj Prakash
  • Publication number: 20040148592
    Abstract: Source code is compiled using a multi-stage compiler that includes a tokenizer, a type checker, and a composer. The tokenizer segments source code into a sequence of tagged segments. The source code includes at least one instruction that composes a first abstraction and a second abstraction with a selected composition operator. The parser builds a tree using the sequence of tagged segments. The type checker performs a first pass of the tree to determine whether abstractions on the tree are well typed. The composer reduces the at least one instruction composing the first and the second abstractions on the tree to a third abstraction. The composer substitutes the first and the second abstractions on the tree with the third abstraction, wherein the type checker performs a second pass of the tree to determine whether the third abstraction is well typed.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 29, 2004
    Applicant: XEROX CORPORATION
    Inventor: Jean-Yves Vion-Dury
  • Publication number: 20040133885
    Abstract: A method is described for providing required values as needed in a class of computer-program compilers, which transform a first computer-program (source program) into a second computer-program (target program), such that the target program has modified or augmented functionality. The source and target programs may be written in the same or different programming languages. As an example, the compiler may perform automatic differentiation (AD), where the source program evaluates a function and the target program evaluates both the function and its derivative, and both programs are written in a high level programming language such as Fortran. In this example, required values are needed in the target program to evaluate its control flow, index expressions, or local derivative information. Providing required values in an efficient way is essential in AD but constitutes a major complexity for various modes of AD. For typical applications, our method is significantly more efficient than standard approaches.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 8, 2004
    Applicant: FastOpt Drs. Ralf Giering und Thomas Kaminski GbR
    Inventors: Ralf Christian Giering, Thomas Herbert Kaminski
  • Patent number: 6760906
    Abstract: A parallel data processing system is provided for increasing the program execution rate of a target machine. A parallelizer converts intermediate code, which has been generated by a compiler front end, into a parallelly executable form. An execution order determiner determines the order of the basic blocks to be executed. An expanded basic block parallelizer subdivides the intermediate code of the basic blocks into execution units, each of which is made up of parallelly executable instructions, following the order determined and on the basic block basis. When a particular one of the basic blocks is subdivided into execution units, an instruction belonging to the first execution unit of the next basic block, which has already been subdivided into execution units, is also used.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: July 6, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kensuke Odani, Taketo Heishi
  • Publication number: 20040117778
    Abstract: A system and method for optimizing software code are provided. Based on user input, a desired segmentation model is determined. Resultant code is generated to replace smaller N-bit pointers, when feasible, for larger pointers in the source code, while maintaining the desired segmentation model.
    Type: Application
    Filed: December 16, 2002
    Publication date: June 17, 2004
    Inventors: David C. Sehr, Rakesh Ghiya, Kevin J. Smith, Richard B.. Wirt
  • Patent number: 6745384
    Abstract: A method and system for anticipatory optimization of computer programs. The system generates code for a program that is specified using programming-language-defined computational constructs and user-defined, domain-specific computational constructs, the computational constructs including high-level operands that are domain-specific composites of low-level computational constructs. The system generates an abstract syntax tree (AST) representation of the program in a loop merging process. The AST has nodes representing the computational constructs of the program and abstract optimization tags for folding of the composites. A composite folding process is applied to the AST according to the optimization tags to generate optimized code for the program.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: June 1, 2004
    Assignee: Microsoft Corporation
    Inventor: Ted J. Biggerstaff
  • Patent number: 6732356
    Abstract: Systems and methods are provided through which compare instructions in computer code are eliminated partially resolving the predicate of the compare instructions. Partially resolved predicates are used to reduce the number of compares generated during the prediction phase of the compiler. In a partially resolved predicate, the predicate name is defined along the same paths as the fully resolved predicate counterpart, but it can be used to guard a subset of the instructions of the fully resolved predicate name. A partially resolved predicate is generated for predicate names which are only valid in a restricted control flow region. One or more of the control flow edges are ignored when computing control dependence. The predicate name relies partially on the actual ignored control flow edge to prevent incorrect usage of the predicate name.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventor: William Y. Chen
  • Publication number: 20040078789
    Abstract: Methods and apparatus are disclosed for determining if a user-defined software function is a memory allocation function during compile-time. The methods and apparatus determine if a user-defined function returns a new memory object every time the user-defined function is invoked. In addition, the methods and apparatus determine if the memory objects created by the user-defined function are available outside the scope of the user defined function. If the user-defined function returns a new memory object every time the user-defined function is invoked, and the memory objects created by the user-defined function are not available outside the scope of the user defined function, then the user-defined function is determined to be a memory allocation function. Otherwise, the user-defined function is determined to be a non-memory allocation function.
    Type: Application
    Filed: June 11, 2002
    Publication date: April 22, 2004
    Inventors: Rakesh Ghiya, Daniel M. Lavery, David C. Sehr
  • Patent number: 6718540
    Abstract: A data processing system and method for managing the storage of compiled instructions used in interpretive programming language applications is implemented. As the applications are implemented in an interpreted programming language, the instructions are compiled into byte-codes to be used by a virtual machine and are subsequently stored in a memory. The data processing system and method recognize that a same application may be used repeatedly and periodically. Thus, the data processing system and method diminish the time required to compile the instructions of an interpretive programming language application, while preserving the compilation of interpretive programming code across sessions accessing the code. Additionally, the data processing system and method diminish the time required to download a Java application and, therefore, allow a user to more efficiently access Internet operations.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Maria C. Azua, Viktors Berstis
  • Patent number: 6718541
    Abstract: A method for scheduling operations utilized by an optimizing compiler to reduce register pressure on a target hardware platform assigns register economy priority (REP) values to each operation in a basic block. For each time slot, operations are scheduled in order of their lowest REP values.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: April 6, 2004
    Assignee: Elbrus International Limited
    Inventors: Alexander Y. Ostanevich, Vladimir Y. Volkonsky
  • Patent number: 6704927
    Abstract: Techniques for performing static binding of dispatched-calls in the presence of dynamic linking and loading are provided. A method for increasing the execution performance of a function at run-time includes compiling the function, which may either be interpreted or previously compiled, and identifying a call within the function to a process. The method also includes adding dependency information to the function. The dependency information is arranged to indicate a status of the function, and contains information pertaining to the class, the name, and the signature associated with the process. In one embodiment, the process is a virtual process, and the method includes analyzing a class structure associated with the function in order to determine when the virtual process is a substantially unique target of the call. In such an embodiment, the virtual process may be inlined into the function when it is determined that the virtual process is the substantially unique target of the call.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: March 9, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Lars Bak, Srdjan Mitrovic, Urs Hölzle
  • Patent number: 6701520
    Abstract: A method to improve object-oriented computer processing by reducing the incidences of object creation and garbage collection. A compiler, preferably of object-oriented language such as Java, identifies a list of objects that are fixed in value or are constant and places those fixed/constant objects in a separate class, a root class, which is loaded at run-time along with all the other classes. Upon creation of an object table, a separate object table may be created for those objects in the root class thereby immunizing the fixed entries from garbage collection and the values will not be erased from memory. Alternatively, the fixed/constant objects can be placed in an object table along with other variable objects but can be marked as active by changing the bit values in a field of the object table.
    Type: Grant
    Filed: May 11, 1999
    Date of Patent: March 2, 2004
    Assignee: International Business Machines Corporation
    Inventors: John Matthew Santosuosso, Eric Lawrence Barsness
  • Patent number: 6694512
    Abstract: A data processing device, data processing method and a supply medium thereof for generating machine instructions to allow faster processing. A DAG (Directed Acyclic Graph) is generated from a substitute statement input by the syntax analyzer, and instructions then generated according to the DAG in the instruction generator, and the instruction generated in the instruction execution simulator then performed and a search made by the search section for the instructions with the smallest number of clock pulses based on the number of clock pulses required to execute the instruction.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: February 17, 2004
    Assignee: Sony Corporation
    Inventor: Nobuhisa Fujinami
  • Publication number: 20040019881
    Abstract: An improved method and process for array shape inferencing for high-level array-based languages such as MATLAB and APL. The process is based on a framework that algebraically describes the shape of an expression at compile time. The method leverages on algebraic properties that underlie MATLAB's shape semantics and exactly captures the shape that the expression assumes at run time. Other highlights of this method are its generality and the uniformity of its approach. Compared with the traditional shadow variable scheme, the algebraic view permits powerful shape-related assertions and optimizations not possible in the conventional approach.
    Type: Application
    Filed: January 30, 2001
    Publication date: January 29, 2004
    Applicant: NORTHWESTERN UNIVERSITY
    Inventors: Pramod G. Joisha, Prithviraj Banerjee, Nagaraj Shenoy
  • Publication number: 20040019883
    Abstract: Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.
    Type: Application
    Filed: January 26, 2001
    Publication date: January 29, 2004
    Applicant: NORTHWESTERN UNIVERSITY
    Inventors: Prithviraj Banerjee, Alok Choudhary, Malay Haldar, Anshuman Nayak
  • Publication number: 20040015923
    Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.
    Type: Application
    Filed: October 24, 2001
    Publication date: January 22, 2004
    Inventors: Craig Hemsing, Dave Hylands, Andrew Jones, Henry W. H. Li, Susan Pullman