Using Flow Graph Patents (Class 717/156)
  • Patent number: 10936342
    Abstract: Embodiments of apparatus, systems, and methods are described for creating, arranging, and displaying data mappings between two different data schemas in a graphical user interface (GUI). The GUI allows scaling of a data schema, automatic data sorting and grouping of objects in a schema, dynamic spacing of data mappings in the GUI, and customizable data map transformations to entities of a canonical data model. The GUI can limit the display of objects and fields to those that have been mapped into entity groups. The GUI can display mapped or unmapped fields to facilitate the mapping of additional fields or objects. The GUI displays visual logic connectors between objects and entities to summarize the relationship and number of mappings between the objects and entities. Objects and entities can be expanded and collapsed to show more granular relationship information. Instance-enabled canonical entities can be created to conceptually group fields.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 2, 2021
    Assignee: salesforce.com, inc.
    Inventors: Christopher Bill, Steven Kostrzewski, Sarah Flamion
  • Patent number: 10789401
    Abstract: Approaches for folding multiply-and-accumulate (MAC) logic in a circuit design involve a design tool recognizing a first instance of the MAC logic and a second instance of the MAC logic. The design tool replaces the first instance of the MAC logic and the second instance of the MAC logic with one instance of pipelined MAC logic. The design tool configures the pipelined MAC logic to input data signals of the first instance of the MAC logic and the second instance of the MAC logic to the pipelined MAC logic at a first clock rate, and switch between selection of the data signals of the first instance of the MAC logic and the second instance of the MAC logic at a second clock rate that is double the first clock rate. The design tool further configures the pipelined MAC logic to pipeline input data signals at the second clock rate, and to capture intermediate results at the second clock rate. The design tool further configures a register to capture output of the pipelined MAC logic at the first clock rate.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 29, 2020
    Assignee: Xilinx, Inc.
    Inventors: Srijan Tiwary, Aman Gayasen, Kumar S. S. Vemuri
  • Patent number: 10754761
    Abstract: Methods and systems for testing source code are disclosed. The method includes mounting a shared memory and launching a controller container. The controller container is configured to retrieve a repository identifier of a repository on which the source code is stored, and a build descriptor including build steps and an indicator of a build VM image for generating the build. The method further includes storing the build steps in the shared memory, retrieving the source code from the repository based on the repository identifier, and storing the retrieved source code in the shared memory. The method also includes launching a build container based on the indicator of the build VM image, the build container configured to retrieve the build steps and the source code from the shared memory and perform the build on the source code based on the steps defined in the build steps.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: August 25, 2020
    Assignee: Atlassian Pty Ltd
    Inventors: Samuel Joseph Tannous, Paul Anthony Kelcey, Jeroen Paul Magdalena De Raedt, Nathan Wayne Burrell, Per Daniel Kjellin
  • Patent number: 10698674
    Abstract: The present application is directed towards systems and methods for identifying and grouping code objects into functional areas with boundaries crossed by entry points. An analysis agent may select a first functional area of a source installation of an application to be transformed to a target installation of the application from a plurality of functional areas of the source installation, each functional area comprising a plurality of associated code objects; and identify a first subset of the plurality of associated code objects of the first functional area having associations only to other code objects of the first functional area, and a second subset of the plurality of associated code objects of the first functional area having associations to code objects in additional functional areas, the second subset comprising entry points of the first functional area.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: June 30, 2020
    Assignee: smartShift Technologies, Inc.
    Inventors: Albrecht Gass, Stefan Hetges, Nikolaos Faradouris, Oliver Flach
  • Patent number: 10691489
    Abstract: Queries are monitored in a database which receives input from a stream computing application to identify data of interest. Parameters defining the data of interest, which are preferably expressed as a logical query, are sent to the stream computing application, which then processes the in-flight streamed data satisfying the parameters in some special manner. In some embodiments, the stream computing application increases the processing priority of in-flight data satisfying the parameters. In some embodiments, the stream computing application applies additional processing steps to the in-flight data satisfying the parameters to provide enhanced data or metadata.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eric L. Barsness, Daniel E. Beuch, Alexander Cook, John M. Santosuosso
  • Patent number: 10686449
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
  • Patent number: 10628286
    Abstract: System, methods, and other embodiments described herein relate to improving the functioning of a program. In one embodiment, a method includes, in response to detecting a code segment being added to source code of the program, identifying control flow characteristics of the source code including the code segment. The method includes updating a control flow graph of the source code according to the control flow characteristics. The control flow graph represents execution paths through the program that are comprised of nodes representing blocks of the source code and directed edges between the nodes representing transitions between the blocks. The method includes providing the control flow graph to improve functioning of the program by facilitating adjustments in the source code.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Denso International America, Inc.
    Inventors: Gopalakrishnan Iyer, Ameer Kashani
  • Patent number: 10579368
    Abstract: Distributed version control systems, methods, and computer-readable media are described. A computer system may implement a version control blockchain system by obtaining source code and/or an artifact associated with source code. The computer system may serialize the source code and/or the artifact to obtain serialized data, and may encipher the serialized data to obtain a current block identifier (cb_id). The computer system may generate a block to include the cb_id, and may add the generated block to the version control blockchain upon validation of the block. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: March 3, 2020
    Assignee: SALESFORCE.COM, INC.
    Inventor: Peter Wisnovsky
  • Patent number: 10540255
    Abstract: A method for analyzing code may include generating, via a flow-insensitive points-to analysis, initial interest points each corresponding to a statement in the code, generating, via a flow-sensitive points-to analysis, flow tuples and refined interest points by removing a subset of the initial interest points, and constructing a flow graph using the refined interest points. The flow graph may include nodes each corresponding to a statement in the code, and edges corresponding to the flow tuples. The method may further include identifying a trace through the flow graph. The trace may include a node corresponding to an interest point of the refined interest points.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 21, 2020
    Assignee: Oracle International Corporation
    Inventors: Raghavendra Kagalavadi Ramesh, Padmanabhan Krishnan, Francois Gauthier
  • Patent number: 10423416
    Abstract: This disclosure provides a computer-implemented method for automatically creating a macro-service. The method includes: converting source code of an analytic program that includes a set of operation units into a graph representation. Each of the set of operation units performs at least an operation to a data object, and the method further includes performing a query associated with the macro-service on the graph representation to determine a subset of the graph representation. The method further includes generating code for the macro-service based on the determined subset of the graph representation.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bi Bo Hao, Wen Sun, Yi Qin Yu, Guo Tong Xie
  • Patent number: 10417098
    Abstract: For accessing files from block-level backups of a virtual disk, an apparatus is disclosed. The apparatus includes a changed block module that obtains a list of changed blocks between a previous and a current backup of a virtual disk. The apparatus includes a mapping module that maps logical clusters of the virtual disk to the changed blocks and identifies files corresponding to the logical clusters. The apparatus further includes a changed file module that designates the files corresponding to the logical clusters as changed files, unless current attributes of the files for the current backup match attributes of the files in a backup file index corresponding to the previous backup of the virtual disk. The changed file module further stores the current attributes and extents for the changed files within blocks of a backup storage device for updating in the backup file index.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Fruchtman, Avishai H. Hochberg, Vadzim I. Piletski, James P. Smith
  • Patent number: 10372786
    Abstract: The invention relates to inferring the state of a system of interest having a plurality of indicator values and possibly being heterogeneous in nature. A number of indicator values from a control state and from a comparison state are gathered. From these indicator values, classification power between the control and comparison states (measure of goodness) is computed. Difference values are computed for the indicator values from the system of interest based on the difference to the indicator values from control and comparison states. From a number of these indicators, composite indicators are formed, and composite measures of goodness and composite difference values are computed. A plurality of composite indicators may be formed at different levels. These indicators may be represented as a tree and grouped according to content, and at the same time they may be arranged according to the measure of goodness or some other value.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Combinostics Oy
    Inventors: Jyrki Loetjoenen, Juha Koikkalainen, Jussi Mattila
  • Patent number: 10324694
    Abstract: Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tong Chen, Brian Flachs, Brad W. Michael, Mark R. Nutter, John K. P. O'Brien, Kathryn M. O'Brien, Tao Zhang
  • Patent number: 10297053
    Abstract: Provided herein are methods, systems, and computer products for evaluating nodes concurrently using a modified data flow graph. The modified data flow graph can identify independent nodes that can run as separate tasks. However, rather than relying on declared dependencies, embodiments herein can determine dependencies between segments of data elements in a data flow graph, and modify the data flow graph to take advantage of the determined dependencies. In such embodiments, the data elements can be divided into segments. By separating data elements into segments, nodes that previously depended on each other can be evaluated concurrently when independent segments are identified.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: May 21, 2019
    Assignee: Pixar
    Inventors: Florian Zitzelsberger, George ElKoura
  • Patent number: 10180826
    Abstract: A compiler generates transfer functions for blocks of a program during compilation of the program. The transfer functions estimate bit widths of variables in the blocks based on numbers of bits needed to carry out at least one instruction in the blocks and whether the variables are live in the blocks. For example, a transfer function may return a number indicating how many bits of a variable are needed to execute a current instruction as a function of the number of bits of the variable used by the program in subsequent instructions. Numbers of bits to represent the variables in the compiled program based on the transfer functions.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 15, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Prakash Sathyanath Raghavendra, Dibyendu Das, Arun Rangasamy
  • Patent number: 10120686
    Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Vineeth Mekkat, Oleg Margulis, Ching-Tsun Chou, Youfeng Wu
  • Patent number: 10013520
    Abstract: A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a layout design. Each candidate cell of the set of candidate cells is one of the set of base layout cells, or one of the set of composite layout cells, and constituent layout cells of the one of the set of composite layout cells having been determined as N-colorable. Whether a first candidate cell of the set of candidate cell is N-colorable is determined. An abutment-sensitive conflict graph of the first candidate cell is generated when the first candidate cell is N-colorable and the first candidate cell is not the top layout cell.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung Lung Lin, Chin-Chang Hsu, Chien Lin Ho, Wen-Ju Yang
  • Patent number: 10013255
    Abstract: A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 3, 2018
    Assignee: CENTIPEDE SEMI LTD.
    Inventors: Jonathan Friedmann, Ido Goren, Shay Koren, Noam Mizrahi, Alberto Mandler
  • Patent number: 9858053
    Abstract: Methods, apparatus and computer software product for optimization of data transfer between two memories includes determining access to master data stored in one memory and/or to local data stored in another memory such that either or both of the size of total data transferred and the number of data transfers required to transfer the total data can be minimized. The master and/or local accesses are based on, at least in part, respective structures of the master and local data.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 2, 2018
    Assignee: Reservoir Labs, Inc.
    Inventors: Richard A. Lethin, Allen K. Leung, Benoit J. Meister, David E. Wohlford
  • Patent number: 9858056
    Abstract: A system and method to hardware-accelerate finite state transducer libraries and their compilation toolchains. In an embodiment, a computer-implemented method for partitioning an UIMA-PEAR file into software-based and hardware-accelerated components may comprise creating a data-flow graph representation of the UIMA-PEAR-file, flattening hierarchies of the data-flow graph representation, and selecting the components to be hardware accelerated from the flattened hierarchies of the data-flow graph representation based on data dependencies of data types produced and consumed by each component of the flattened data-flow graph.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kubilay Atasu, Akihiro Nakayama, Raphael Polig, Tong Xu
  • Patent number: 9787693
    Abstract: In a method and apparatus for analyzing nodes of a Deterministic Finite Automata (DFA), an accessibility ranking, based on a DFA graph geometrical configuration, may be determined in order to determine cacheable portions of the DFA graph in order to reduce the number of external memory accesses. A walker process may be configured to walk the graph in a graph cache as well as main memory. The graph may be generated in a manner allowing each arc to include information if the node it is pointing to is stored in the graph cache or in main memory. The walker may use this information to determine whether or not to access the next arc in the graph cache or in main memory.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: October 10, 2017
    Assignee: Cavium, Inc.
    Inventors: Rajan Goyal, Muhammad Raghib Hussain, Trent Parker
  • Patent number: 9696975
    Abstract: Register halves are allocated independently when performing register allocation during program compilation, thereby effectively doubling the number of registers which are available for allocation, which in turn may reduce spill code and improve run-time performance. When hardware registers are 64 bits wide, for example, an architecture supporting the present invention provides some number of separate hardware instructions that operate on the 32-bit high-word and/or the 32-bit low word of the hardware registers as if those 32-bit words are separate registers. Such hardware instructions are able to manipulate the register halves independently, leaving the other register half untouched. A register coloring algorithm using in the compilation process is invoked using the number of register halves, instead of the number of hardware registers.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David P. Belanger, Christopher A. Lapkowski, Chwan-Hang Lee
  • Patent number: 9600253
    Abstract: Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tong Chen, Brian Flachs, Brad W. Michael, Mark R. Nutter, John K. P. O'Brien, Kathryn M. O'Brien, Tao Zhang
  • Patent number: 9569187
    Abstract: An approach to generating irreducible modules. The approach includes a method that includes receiving, by at least one computing device, data associated with a specification. The method includes defining, by the at least one computing device, a pattern on the received data. The pattern reduces a set of rules into a single condition. The method includes generating, by the at least one computing device, an irreducible module based on the pattern. The irreducible module has one output dependent variable and is associated with a data flow application.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: William J. Lewis
  • Patent number: 9477928
    Abstract: In one embodiment, a method may include symbolically executing application code on a first framework. The method may also include creating a first model based on the symbolic execution of the first framework. The method may additionally include symbolically executing the application code on a second framework. The method may further include creating a second model based on the symbolic execution of the first framework. The method may also include determining one or more parameters associated with the first framework based on the first model. The method may additionally include determining one or more parameters associated with the second framework based on the second model. The method may also include selecting one of the first framework and the second framework as a desired framework for execution of the application code based on a comparison of the one or more parameters associated with the first framework and the one or more parameters associated with the second framework.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: October 25, 2016
    Assignee: Fujitsu Limited
    Inventors: Sreeranga P. Rajan, Indradeep Ghosh
  • Patent number: 9389848
    Abstract: In a computer-implemented method for scheduling a plan of operations in a datacenter selection of a target from a plurality of targets in the datacenter is enabled for scheduling operations on the selected target. Selection of one or more bundles is enabled, wherein the plan of operations on the selected target are based on the one or more bundles. Dependency relationships between the selected target and other targets in the plurality of targets are determined based on the selection of one or more bundles. The plan of operations on the selected target is scheduled.
    Type: Grant
    Filed: June 28, 2014
    Date of Patent: July 12, 2016
    Assignee: VMware, Inc.
    Inventors: John Powell, Patrick Devine, Mustafa Jamil, Daniel Hiltgen, Timothy Stack, Saleem Abdulrasool, Moshe Zadka, Kshitij Padalkar
  • Patent number: 9292265
    Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 22, 2016
    Assignee: NVIDIA Corporation
    Inventors: Vinod Grover, Yunsup Lee, Xiangyun Kong, Gautam Chakrabarti, Ronny M. Krashinsky
  • Patent number: 9256409
    Abstract: A method includes inspecting function summaries generated during a static analysis of a program and identifying a set of function summaries for a same method that have structural similarities. The method includes replacing the set of structurally similar summaries with a coarse summary. The method further includes using the coarse summary in subsequent static analysis operations. Apparatus and program products are also disclosed.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Marco Pistoia, Omer Tripp
  • Patent number: 9250876
    Abstract: A method includes inspecting function summaries generated during a static analysis of a program and identifying a set of function summaries for a same method that have structural similarities. The method includes replacing the set of structurally similar summaries with a coarse summary. The method further includes using the coarse summary in subsequent static analysis operations. Apparatus and program products are also disclosed.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Marco Pistoia, Omer Tripp
  • Patent number: 9208060
    Abstract: Systems, methods and computer program products are described that enable a diagnostic tool, such as a debugger, to evaluate an expression based on the state of a target program process where the expression to be evaluated includes a call to a first function that exists in the target program process but where evaluation of such first function requires evaluation of a second function that does not exist in the target program process. For an expression such as this, the diagnostic tool emulates execution of the first function within a process other than the target program process, such as within the diagnostic tool process. In other embodiments, the emulation capability of the diagnostic tool is leveraged to enable a user thereof to simulate a modification of the target program process without making actual changes to the target program process.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: December 8, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Patrick L. Nelson, Gregory B. Miskelly, Jackson M. Davis, Eric H. Feiveson, Azeemullah Khan
  • Patent number: 9207923
    Abstract: Exemplary embodiments of the present invention disclose a method and system for replacing an unevaluated input that is constant at runtime to a group of instructions that calculates an output and can not modify the unevaluated input with invocation code that calls evaluation code. In a step, an exemplary embodiment identifies a group of instructions with an unevaluated input that is constant at runtime that calculates an output and can not modify the unevaluated input. In another step, an exemplary embodiment identifies an unevaluated input to the group of instructions that is constant at runtime. In another step, an exemplary embodiment generates an evaluation code that evaluates the unevaluated input. In another step, an exemplary embodiment replaces the unevaluated input with an invocation code that invokes the evaluation code.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jean-Louis Ardoint, Benoit H. Poupon
  • Patent number: 9183021
    Abstract: A method and system for optimizing application code via transformation of calls made by the application code during runtime. A computer system loads the application code that has been intermediately compiled into bytecode. The computer system then compiles and executes the application code. During runtime, the application code makes a call from a call site to an implementation of an operation that returns a value to the application code. The computer system runs an implementer of the implementation and an agent that operates independently of a compiler. The agent receives a notification of the call, performs an analysis on the application code during runtime to determine whether the value is used by the application code, and optimizes the application code by transforming the call site based on a result of the analysis.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: November 10, 2015
    Assignee: Red Hat, Inc.
    Inventor: Andrew E. Dinn
  • Patent number: 9164743
    Abstract: An optimizing compiler includes a strength reduction mechanism that optimizes a computer program that includes operations that have an unknown stride by analyzing the instructions in the computer program in a single pass, determining whether instruction substitution is profitable for original instructions in the code, and performing instruction substitution for one or more original instructions for which instruction substitution is deemed profitable, including operations with unknown strides. The substituted instructions result in strength reduction in the computer program.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 20, 2015
    Assignee: International Business Machines Corporation
    Inventor: William J. Schmidt
  • Patent number: 9158517
    Abstract: An optimizing compiler includes a strength reduction mechanism that optimizes a computer program that includes operations that have an unknown stride by analyzing the instructions in the computer program in a single pass, determining whether instruction substitution is profitable for original instructions in the code, and performing instruction substitution for one or more original instructions for which instruction substitution is deemed profitable, including operations with unknown strides. The substituted instructions result in strength reduction in the computer program.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventor: William J. Schmidt
  • Patent number: 9135146
    Abstract: Technologies are described herein for use in identifying and resolving software issues. One or more corrective actions may be identified and taken that are based upon the similarity between an unresolved issue and one or more resolved issues and/or upon the similarity between code changes made to resolve similar previously resolved issues. A version control graph might also be utilized to determine if a change made to resolve an issue in one branch of a software component is applicable to another branch of the software component. The version control graph might also be utilized to compute the relevance of an entry in an issue tracking system for an issue at a point in time after the entry is created in the issue tracking system.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 15, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Nicholas Alexander Allen, Andrew Thomas Troutman, Joshua William McFarlane, Matthew Roy Noble
  • Patent number: 9135057
    Abstract: A stream computing application may permit one job to connect to a data stream of a different job. As more and more jobs dynamically connect to the data stream, the connections may have a negative impact on the performance of the job that generates the data stream. Accordingly, a variety of metrics and statistics (e.g., CPU utilization or tuple rate) may be monitored to determine if the dynamic connections are harming performance. If so, the stream computing system may be optimized to mitigate the effects of the dynamic connections. For example, particular operators may be unfused from a processing element and moved to a compute node that has available computing resources. Additionally, the stream computing application may clone the data stream in order to distribute the workload of transmitting the data stream to the connected jobs.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, Ryan K. Cradick, John M. Santosuosso, Brandon W. Schulz
  • Patent number: 9122494
    Abstract: A method for code size reduction, which comprises determining basic blocks in an IR module; grouping the basic blocks having duplicate code into groups; providing weighting values corresponding to different instructions of the module, wherein the weighting values are determined based on a plurality of intermediate representation program codes; determining a weighted size of the module, wherein the weighted size of the module is determined by summing weighted sizes of the basic blocks of the module, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks and the corresponding weighting values; removing duplicates in one group to obtain a module having one processed group; determining a weighted size of the module having one processed group; and comparing the weighted size of the module to the weighted size of the module having one processed group.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 1, 2015
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Kun Hua Yang, Shao Chung Wang, Jenq Kuen Lee
  • Patent number: 9116714
    Abstract: The present disclosure relates to a method and system for file processing. The file processing method may include the steps of scanning a source files, identifying a target code block, and generating a first abstract syntax tree (AST) reflecting the structure of the target code block. The file processing method may further include the steps of identifying a position to place a plugin code, placing the plugin code into the first AST, generating a second AST reflecting the structure of the target code block with the plugin code, and using the write-back interface to write the second AST into the source file. The present disclosure may improve the efficiency and enhance the flexibility of the file processing system.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: August 25, 2015
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Yunjia Wu
  • Patent number: 9117043
    Abstract: Processing a circuit design can include determining a first set of net sensitivity ranges for a net of the circuit design, wherein at least two net sensitivity ranges of the first set are partially overlapping, and translating the first set of net sensitivity ranges into a second set of net sensitivity ranges comprising a plurality of member net sensitivity ranges with no partially overlapping member net sensitivity ranges. A net sensitivity tree can be constructed that includes hierarchically ordered nodes. Each node can specify a net sensitivity range of one member of the second set of net sensitivity ranges.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 25, 2015
    Assignee: XILINX, INC.
    Inventors: Lixin Huang, Hem C. Neema, Sonal Santan
  • Patent number: 9052956
    Abstract: Disclosed herein are techniques for selecting execution environments. Each operation in a sequence of operations is implemented using a selected execution environment. Each operation is converted into code executable in the selected execution environment. If some operations in the sequence were implemented in different execution environments, execution of the operations is coordinated.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 9, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alkiviadis Simitsis, William K Wilkinson
  • Publication number: 20150149988
    Abstract: The present invention is a technique for obtaining execution frequency information on execution paths in a CFG, including preparing a CFG from a source code read into a memory, preparation of the CGF including modifying the CFG by assigning path value zero to an edge v?w between a precedent basic block v and a successor basic block w following the predecessor basic block v in a case where the successor basic block w has a predecessor basic block x other than the predecessor basic block v, and where the successor basic block w exists on a fall-through path from the predecessor basic block x. The technique also includes obtaining execution frequency information by using the modified CFG.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 28, 2015
    Inventor: Takuya Nakaike
  • Patent number: 9043774
    Abstract: Computer-implemented methods for analyzing computer programs written in semi-structured languages are disclosed. The method is based on unification of the two classic forms of program flow analysis, control flow and data flow analysis. As such, it is capable of substantially increased precision, which increases the effectiveness of applications such as automated parallelization and software testing. Certain implementations of the method are based on a process of converting source code to a decision graph and transforming that into one or more alpha graphs which support various applications in software development. The method is designed for a wide variety of digital processing platforms, including highly parallel machines. The method may also be adapted to the analysis of (semi-structured) flows in other contexts including water systems and electrical grids.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: May 26, 2015
    Inventors: William G. Bently, David D. Duchesneau
  • Publication number: 20150143349
    Abstract: A method comprises generating an intermediate representation of a pointer-based program; providing a control flow graph of the intermediate representation; selecting an analysis candidate from the intermediate representation as a traced variable and a root node; determining a definition site of the trace variable according to a use-define chain and the control flow graph; defining a node for each definition site variable; defining an edge by using each definition site variable and the traced variable; using each definition site variable of the definition site as a traced variable; repeating the steps of determining a definition site, defining a node, defining an edge and using each definition site to obtain a divergence relation graph; transforming the divergence relation graph into a directed acyclic graph; and determining whether the analysis candidate is divergent or not according to a divergent node and the directed acyclic graph.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: SHAO CHUNG WANG, JENQ KUEN LEE
  • Patent number: 9038036
    Abstract: A method of generating an executable that operates as a compiler includes: receiving a unified input description containing syntax rules for both regular and context-free expressions and interspersed code; generating a common internal representation from the unified input description; checking regular expressions in the common internal representation; checking context-free expressions in the common representation; checking the interspersed code; and outputting the executable.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wolfgang Gellerich, Andreas Krebbel
  • Patent number: 9032380
    Abstract: A device receives program code, generated via a technical computing environment (TCE) and including code that requires further processing to execute, and identifies one or more function calls or one or more object method calls in the program code. The device creates a control flow graph, for the program code, based on the one or more function calls or the one or more object method calls. The device transforms the control flow graph into a data flow graph. The data flow graph includes a representation for each of the one or more function calls or the one or more object method calls. The device generates hardware code based on the data flow graph, the hardware code including code that does not require further processing to execute.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: May 12, 2015
    Assignee: The MathWorks, Inc.
    Inventors: Navaneetha K. Ruthramoorthy, Kiran K. Kintali
  • Patent number: 9026987
    Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: May 5, 2015
    Assignee: National Instruments Corporation
    Inventor: Christopher G. Cifra
  • Patent number: 9021451
    Abstract: In one embodiment, a method for call graph analysis is provided. The method includes determining a plurality of nodes in a call graph. The plurality of nodes represent resource consumption of functions of a software program executed in a software system. A simplification factor is determined. A first set of nodes in the plurality of nodes is then eliminated based on exclusive values for the plurality of nodes, inclusive values for the plurality of nodes, and the simplification factor. An inclusive value for a node is a first amount of resources consumed by the node and any descendent nodes of that node. An exclusive value for the node is a second amount of resources consumed by the node. A simplified call graph is output including a second set of nodes in the plurality of nodes. The second set of nodes does not include the eliminated first set of nodes.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 28, 2015
    Assignee: SAP SE
    Inventors: Cheolman Park, Chan Young
  • Patent number: 9015687
    Abstract: Systems and methods of allocating physical registers to variables may involve identifying a partial definition of a variable in an inter-procedural control flow graph. A determination can be made as to whether to terminate a live range of the variable based at least in part on the partial definition. Additionally, a physical register may be allocated to the variable based at least in part on the live range.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Biju George, Guei-Yuan Lueh
  • Patent number: 9013574
    Abstract: A machine vision system program editing environment including synchronized selection and/or identification of related features in a plurality of different user interface windows is provided. In particular, one of the windows is an editing window where a part program representation is displayed for editing by a user. In one embodiment, a user may select data or another feature of interest in a window that is not the editing window (e.g., a results window, or graphical workpiece inspection feature display window) and the associated part program instruction representation is automatically highlighted and/or selected in the editing window. Conversely, a part program instruction representation may be selected by a user in the editing window and the associated results or feature in another window is automatically highlighted and/or selected. User interface navigation, rapid program quality assessment, and overall part program creation and editing efficiency are significantly enhanced in such an editing environment.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: April 21, 2015
    Assignee: Mitutoyo Corporation
    Inventors: Barry Saylor, Ryan Northrup, Akira Takada, Kozo Ariga
  • Patent number: 9003383
    Abstract: The subject system provides the ability to parallelize pre-existing serial code by importing and encapsulating all of the serial code into an object orientated flowchart language utilizing an analytic engine so that the imported code can be efficiently executed taking advantage of the partially ordered transitive flowchart system. The importation examines the serial code to ascertain what elements may be processed under an atomic time to instantiate them as either Action or Test objects, whereas statements which require more than atomic time are instantiated as Task object, with the Action, Test and Task objects being processable by separate processors to establish parallel processing, or by the multitasking afforded by the partially ordered transitive flowchart system.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: April 7, 2015
    Assignee: You Know Solutions, LLC
    Inventors: Ronald J. Lavallee, Thomas C. Peacock