Abstract: Techniques for compiling a data stream processing application are provided. The techniques include receiving, by a compiler executing on a computer system, source code for a data stream processing application, wherein the source code comprises source code for a plurality of operators, each of which performs a data processing function, determining, by the compiler, one or more characteristics of operators within the data stream processing application, grouping, by the compiler, the operators into one or more execution containers based on the one or more characteristics, and compiling, by the compiler, the source code for the data stream processing application into executable code, wherein the executable code comprises a plurality of execution units, wherein each execution unit contains one or more of the operators, wherein each operator is assigned to an execution unit based on the grouping, and wherein each execution unit is to be executed in a partition.

Abstract: A system and method for facilitating simulation of a computer program. A program representation is generated from a computer program. A simulation of the program is performed. Simulation may include applying heuristics to determine program flow for selected instructions, such as a branch instruction or a loop instruction. Simulation may also include creating imaginary objects as surrogates for real objects, when program code to create real objects is restricted, or fields of the objects are unavailable or uncertain, or for other reasons. Data descriptive of the simulation is inserted into the program representation. A visualizer may retrieve the program representation and generate a visualization that shows sequence flows resulting from the simulation.

Abstract: The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.

Abstract: Methods and apparatus for checking the compliance of a file with global and custom standards are disclosed. According to one aspect of the present invention, a method for checking a file that is associated with a first set of standards and a second set of standards into a repository includes providing the file to a checking arrangement that includes a checking tool and an adapter that is interfaced with the checking tool. The method also includes executing the checking tool to determine compliance of the file with the first set of standards, and executing the adapter to determine compliance of the file with the second set of standards.

Abstract: A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The decomposed instructions allow a compiler with knowledge of the instruction semantics to perform optimizations which would be unavailable on traditional software transactional memory systems. Additionally, high-level software transactional memory optimizations are performed such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects. During execution, multi-use header words for objects are extended to provide for per-object housekeeping, as well as fast snapshots which illustrate changes to objects. Additionally, entries to software transactional memory logs are filtered using an associative table during execution, preventing needless writes to the logs.

Abstract: A method for finding sequential patterns of attributes in a directed graph includes constructing a directed graph comprising multiple nodes and edges between the nodes. Each of the nodes may be assigned one or more attributes. Similarly, each of the edges may be assigned a weight value which may indicate the probably the edge will be traversed during traversal of the directed graph. The method may further include finding sequences of attributes in the directed graph that have some minimum amount of frequency and/or time support. In performing this step, the frequency support of each individual instance of a sequence of attributes may be calculated by multiplying the weight values along the edge or edges of the instance. A corresponding apparatus and computer program product are also disclosed and claimed herein.

Abstract: A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.

Abstract: The present invention is a method of eliminating loops from a computer program by receiving the program, graphing its function and control, identifying its entry point, and identifying groups of loops connected to its entry point. Stop if there are no such groups. Otherwise, selecting a group of loops. Then, identifying the selected group's entry point. If the selected group includes no group of loops having a different entry point then replacing it with a recursive or non-recursive function, reconfiguring each connection entering and exiting the selected group to preserve their functionality, and returning to the fifth step. Otherwise, identifying groups of loops in the selected group connected to, but having different entry points and returning to the loop selection step.

Abstract: A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model.

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: In one embodiment, the present invention includes a method for partitioning a program segment into at least a first stage and a second stage, determining a live set of variables and control flow information alive at a boundary between the first and second stages, and controlling the first stage to transmit a trace-specific portion of the live set for a first trace to the second stage via a communication channel. In such manner, reduced transmission of data between the stages is effected. Other embodiments are described and claimed.

Abstract: In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Abstract: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.

Abstract: A method and apparatus for dynamic binary translator to support precise exceptions with minimal optimization constraints. In one embodiment, the method includes the translation of a source binary application generated for a source instruction set architecture (ISA) into a sequential, intermediate representation (IR) of the source binary application. In one embodiment, the sequential IR is modified to incorporate exception recovery information for each of the exception instructions identified from the source binary application to enable a dynamic binary translator (DBT) to represent exception recovery values as regular values used by IR instructions. In one embodiment, the sequential IR may be optimized with a constraint on movement of an exception instruction downward past an irreversible instruction to form a non-sequential IR. In one embodiment, the non-sequential IR is optimized to form a translated binary application for a target ISA. Other embodiments are described and claimed.

Abstract: An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link generating unit generates, based on the association information, a link that couples nodes generated by the node generating unit. A sub-chart generating unit configured to generate a plurality of sub-charts by dividing a chart indicating a content of the specification description, based on the node and the link. A function-module generating unit generates, for each of the sub-charts, a function module that executes a function based on the processing information corresponding to the node in the sub-chart and the association information corresponding to the link in the sub-chart.

Abstract: A method and apparatus for disambiguating in a dynamic binary translator is described. The method comprises selecting a code segment for load-store memory disambiguation based at least in part on a measure of likelihood of frequency of execution of the code segment; heuristically identifying one or more ambiguous memory dependencies in the code segment for disambiguation by runtime checks; based at least in part on inspecting instructions in the code segment, and using a pointer analysis of the code segment to identify all other ambiguous memory dependencies that can be removed by the runtime checks.

Abstract: Methods and apparatus to create software basic block layouts are disclosed. In one example, a method identifies branch data associated with a plurality of machine accessible instructions and identifies a plurality of basic blocks associated with the branch data. The method generates a partial layout from the plurality of basic blocks and generates a substantial layout from the partial layout based on a cost metric.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. A first availability chain is created from a producer instruction (p1) to a first consumer instruction (c1), when the execution of the instruction requires a value produced by the producer instruction. The first availability chain includes at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the producer execution unit to a second point (22: DRF) accessible by a first consumer execution unit. When a second consumer instruction (c2), also requiring the same value, is scheduled for execution by an execution unit (23: EXU) other than the first consumer execution unit, at least part of the first availability chain is reused to move the required value to a point (23: DRF) accessible by that other execution unit.

Abstract: An intermediate representation of sequences of instructions for a stacked based computer is a code graph using a numbering method on the nodes of the graph, along with a set of relations among the nodes, to determine, in a single pass, the independence of each node or sub-graph represented by the node. The numbering is a post-order that directly, by numerical comparison defines the relevant hierarchical relationships among sub-graphs. The sub-graph of a particular node may have one or more alias nodes that refers to target nodes, a target node being a node representing an argument which is the result of a previous program instruction. For a subgraph to be considered independent, any aliases generated by nodes within the subgraph must themselves be contained in it, and conversely, any aliases in the subgraph must have been generated by nodes also within it.

Abstract: A system and method to perform post pass optimizations in a dynamic compiling environment. A dynamic compiler emits machine code. Responsive to the emission of the machine code a post pass processor creates an abstract representation of the code from the dynamic compiler. Data flow analysis is then conducted on the abstract representation. Redundant instructions in the machine code are identified and eliminated as a result of the data flow analysis.

Abstract: An information-processing method usable by an information-processing apparatus is provided. The information-processing-apparatus is used for editing state-transition information usable to construct a state-transition diagram including information on the operation in each of states, information on events each possibly occurring in each specific one of the states to result in a transition, and information on transition directions each indicating the direction of a transition caused by each of the events possibly occurring in the states. The method includes searching for a hardware event not assigned yet as any one of the events, assigning a hardware are event found in a search process carried out at the searching step as a shortcut event if the events include the software event, generating the state-transition diagram on the basis of the state-transition information, and displaying the state-transition diagram.

Abstract: A system and method for efficient architectural register liveness analysis and register usage reduction. A compiler within a computing system maintains a master liveness vector for each instruction in a program code and a path liveness vector for each path within a predetermined control flow graph (CFG). Predetermined required paths from an earlier compiler stage are used to find force paths, which are used to reduce the number of times a control block (CB) is processed. Upon completion of the liveness analysis, the compiler finds an instruction within the program code where a chosen register previously dead is now live. The compiler identifies allocation code paths from this instruction, wherein each path terminates at an instruction wherein the chosen register is dead for the first time in the allocation code path. The compiler subsequently replaces the chosen register with a determined dead register.

Abstract: Commercial data processors are available that include a capability of extending their instruction set for a specified application, i.e. of introducing customized functional units in the interest of enhanced processing performance. For such processors there is a need for automatically forming the extensions from high-level application code. A technique is described for selecting maximal-speedup convex subgraphs of the application dataflow graph under micro-architectural constraints.

Abstract: Implementations provide a technology for generating a minimum delta between at least two program binaries. An implementation is given a source program (S) in a binary format and a target program (T) in a binary form. It constructs control flow graphs (CFGs) of each. It matches common blocks of the S's CFGs and T's CFGs. The blocks are matched based upon their content and their local neighborhoods. In addition, the register renaming problems is solved so that blocks can be fairly compared. This implementation produces an intermediate output, which is the content of unmatched blocks. It generates a set of edge edit operations for merging the unmatched blocks into S. The combination of the unmatched blocks and the edit operations is the delta. To patch S to produce a reconstructed copy of T, the delta is merged with S.

Abstract: Implementations provide a technology for generating a minimum delta between at least two program binaries. An implementation is given a source program (S) in a binary format and a target program (T) in a binary form. It constructs control flow graphs (CFGs) of each. It matches common blocks of the S's CFGs and T's CFGs. The blocks are matched based upon their content and their local neighborhoods. In addition, the register renaming problems is solved so that blocks can be fairly compared. This implementation produces an intermediate output, which is the content of unmatched blocks. It generates a set of edge edit operations for merging the unmatched blocks into S. The combination of the unmatched blocks and the edit operations is the delta. To patch S to produce a reconstructed copy of T, the delta is merged with S.

Abstract: Compile-time non-concurrency analysis of parallel programs improves execution efficiency by detecting possible data race conditions within program barriers. Subroutines are modeled with control flow graphs and region trees having plural nodes related by edges that represent the hierarchical loop structure and construct relationship of statements. Phase partitioning of the control flow graph allows analysis of statement relationships with programming semantics, such as those of the OpenMP language, that define permitted operations and execution orders.

Abstract: A method for analyzing a program is provided. The method includes, determining an object type that may exist at an execution point of the program, wherein this enables determination of possible virtual functions that may be called; creating a call graph at a main entry point of the program; and recording an outgoing function call within a main function. The method also includes analyzing possible object types that may occur at any given instruction from any call path for virtual calls, wherein possible object types are determined by tracking object types as they pass through plural constructs; and calling into functions generically for handling specialized native runtime type information.

Abstract: A method for optimizing a transaction consisting of an initial sequence of computer operations, the method including identifying one or more idempotent operations in the initial sequence. The method further includes reordering the initial sequence to form a reordered sequence consisting of a first sub-sequence of the computer operations followed by a second sub-sequence of the computer operations. The second sub-sequence has only the one or more idempotent operations.

Abstract: A system and method for determining where bottlenecks in a program's data accesses occur and providing information to a software developer as to why the bottlenecks occur and what may be done to correct them. A stream of data access references is analyzed to determine data access patterns (also called data access sequences). The stream is analyzed to find frequently repeated data access sequences (called hot data streams). Properties of the hot data streams are calculated and upon selection of a hot data stream are displayed in a development tool that associates lines of code with the hot data streams.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: A method to provide effective control and data flow information in an Intermediate Representation (IR) form. A Path Sensitive single Assignment (PSA) IR form with effective and explicit control and data path information supports control flow sensitive optimizations such as path sensitive symbolic substitution, array privatization and speculative multi threading. In the definition of PSA form, besides defining new versioned variables, the gamma functions keep control path information. The gamma function in PSA form keeps the basic attribute of SSA IR form and only one definition exists for each use. Therefore, all existing Single Static Assignment (SSA) IR form based analysis can be applied in PSA form. The gamma function in PSA form keeps all essential control flow information and eliminates unnecessary predicates at the same time.

Abstract: A system and method for visually indicating one or more problems in a graphical program. The graphical program may be programmatically analyzed to discover a problem (or potential problem) in the graphical program. The problem found during the programmatic analysis of the graphical program may then be visually indicated on a display device. Visually indicating the problem may comprise visually indicating one or more objects in the graphical program to which the problem corresponds. Visually indicating the graphical program object(s) may comprise displaying information or altering the appearance of the object(s) in order to call the user's attention to the object(s).

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract: Provides methods for transforming a flowchart to an equivalent tree diagram, methods for transforming an equivalent tree diagram to a flowchart, methods for verifying reorganization of a flowchart, methods for editing a flowchart, methods for creating a flowchart and a flowchart editor. A flowchart includes one or more logic structures and one or more processing activities in said one or more logic structures. The method for transforming a flowchart to an equivalent tree diagram comprises: traversing said flowchart; transforming said one or more logic structures in said flowchart to one or more branching nodes in said tree diagram; and transforming one or more processing activities in said logic structures of said flowchart to one or more leaf nodes below corresponding branching nodes in said tree diagram. Further, edition of a flowchart and verification of reorganization of a flowchart are performed by utilizing an equivalent tree diagram.

Abstract: A mobile care engine system is provided for delivering customer care to mobile devices, comprising. The mobile care engine system compares profile data from a mobile device with reference data and highlights any inconsistencies between the data, so that the device can be optimized. The inconsistencies are preferably determined using rule-based processing, and are automatically highlighted on the device display itself, or on a display of a customer service representative interface. Optionally, the system allows for corrective patches or settings to be sent to the device.

Abstract: A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

Abstract: A method to optimize speculative parallel thread execution comprises selecting a plurality of partition candidate pairs for speculative parallel thread execution, transforming each partition candidate pair of the plurality of partition candidate pairs to improve the expected performance gain of each pair, and selecting a set of one or more transformed partition candidate pairs that do not interfere with each other and produce a maximum expected performance gain.

Abstract: The present invention is a machine implemented, design automation method that assists a designer in the understanding of a software and/or hardware source code specification by transforming the source code into a simplified specification called a program slice. The present invention extends graph-based program slicing to the hardware-software interface that is commonly found in embedded systems. In addition to the known benefits of program slicing applied to a pure software or pure hardware, the present invention aids a designer in understanding the complex interaction between software procedures and hardware processing elements in the context of a codesign methodology.

Abstract: Methods for representing and evaluating dependency systems are provided. In one implementation a method is provided. The method includes receiving a file. The file includes a node array having data entries corresponding to one or more nodes. The file also includes an edge array having data entries corresponding to one or more edges, the edge entries identifying an invertability state of an edge, a suppressed state of an edge, and one or more partner edge linking a first and a second edge in the edge array. The method also include processing the received file. In another implementations a method for evaluating dependencies in a cyclic system is provided as well as a method for evaluating an enhanced directed dependency graph.

Abstract: Pre-compiling postdominating functions. Some embodiments may be practiced in a computing environment including a runtime compilation. For example one method includes acts for compiling functions. The method includes determining that a function of an application has been called. A control flow graph is used to determine one or more postdominance relationships between the function and one or more other functions. The one or more other functions are assigned to be pre-compiled based on the postdominance relationship.

Abstract: Computer-implemented methods for analyzing computer programs written in semi-structured languages are disclosed. The method is based on unification of the two classic forms of program flow analysis, control flow and data flow analysis. As such, it is capable of substantially increased precision, which increases the effectiveness of applications such as automated parallelization and software testing. Certain implementations of the method are based on a process of converting source code to a decision graph and transforming that into one or more alpha graphs which support various applications in software development. The method is designed for a wide variety of digital processing platforms, including highly parallel machines. The method may also be adapted to the analysis of (semi-structured) flows in other contexts including water systems and electrical grids.

Abstract: A method including analyzing a program to obtain information about variables within the program, generating a call graph based on the information, determining all possible aliases for each variable, identifying parallel accesses by two variables, a variable and an alias, and/or two aliases during an instruction in the program, generating an interference graph based on the parallel accesses, and assigning the variables to logical stacks based on the interference graph.

Abstract: Repetitive synchronization in program code is optimized through lock coarsening that is performed subject to a number of constraints. Using a forward pass over the program code followed by a backward pass, region extent bits may be determined that identify the points in the program where object locking can be coarsened. The program code may then be modified to realize coarsened locking regions determined based on the region extent bits. Alternatively, previously determined value numbers may provide much of the information collected by the two passes. In such a case, a single pass over the program code may locate features that limit lock coarsening opportunities. A set of synchronization operations that can be removed may then be determined and used when modifying the program code to coarsen locking regions.

Abstract: A method of intra-block memory usage analysis for a program can include identifying a memory block that has been allocated to the program and determining at least one intra-memory block usage characteristic for the allocated memory block.

Abstract: A method, system, and computer readable medium for converting a series of computer executable instructions in control flow graph form into an intermediate representation, of a type similar to Static Single Assignment (SSA), used in the compiler arts. The indeterminate representation may facilitate compilation optimizations such as constant propagation, sparse conditional constant propagation, dead code elimination, global value numbering, partial redundancy elimination, strength reduction, and register allocation. The method, system, and computer readable medium are capable of operating on the control flow graph to construct an SSA representation in parallel, thus exploiting recent advances in multi-core processing and massively parallel computing systems. Other embodiments may be employed, and other embodiments are described and claimed.

Abstract: When, during debugging, a program failure occurs, the location of the failure is determined. First the address in the stack related to the program failure is found. Then static analysis is performed in order to determine a possible culprit for the failure. For example, when a security cookie has been overwritten, indicating a probable overflow, the location of the security cookie on the stack is determined, and proximate storage structures (such as arrays) which may have overflowed onto the location of the security cookie are determined. Then static analysis is used to determine probable sources (e.g. functions or instructions in a function) for this error. In this way, the root cause of a buffer overflow or similar problem can be identified easily, rather than requiring extensive time and knowledge regarding the working of the compiler, the security cookie, the stack, static analysis, and the source code.

Abstract: Method and systems are provided for representing interfaces between electronic components of a computational hardware device in a graphical model and automatically generating code from the graphical model to implement one or more component interfaces in the computational hardware device. A graphical modeling environment provides for the definition of interface boundaries to represent component interfaces between electronic components associated with partitions of a graphical model design. A code building tool automatically generates code from the graphical model to build executable instructions to run the component interfaces on the electronic components of the computational hardware device.

Abstract: A computer implemented method, apparatus, and computer program product for generating an optimization insensitive behavior profile. In one embodiment, a source identifier is assigned to each instruction in an original control flow graph representing a program code prior to optimization. The identifiers identify a basic block associated with the instruction or a group of basic blocks. A source identifier in the set of source identifiers is assigned to instructions in an optimized control flow graph representing the program code after optimizing the program code. The instructions in the optimized control flow graph are mapped to the original control flow graph using the set of source identifiers to form a mapping transformation. Behavior profile data associated with the optimized program code is moved to basic blocks in the original control flow graph using the mapping transformation to form the optimization insensitive behavior profile.

Abstract: A program development supporting apparatus that groups a plurality of events each executed in an information processor to divide the events into a plurality of parallel execution units to be executed in parallel with each other has a directional graph acquisition section that acquires directional graph data expressing each of the plurality of events as a vertex and a restriction on the execution order between two of the plurality of events as a directional branch, an inverse chain partial set extraction section that traces the directional branch from each event in the forward direction to extract from the directional graph data an inverse partial set that is a combination of the events having such a relationship that any one of the events cannot be reached from the other events, and a parallel execution unit assignment section that assigns the plurality of events belonging to the inverse partial set to units different from each other in the parallel execution units.