Shaping Or Removal Of Materials (e.g., Etching, Etc.) Patents (Class 977/888)

Cross-Reference Art Collections

By laser ablation (Class 977/889)
  • Patent number: 9040121
    Abstract: Vacuum deposited thin films of material are described to create an interface that non-preferentially interacts with different domains of an underlying block copolymer film. The non-preferential interface prevents formation of a wetting layer and influences the orientation of domains in the block copolymer. The purpose of the deposited polymer is to produce nanostructured features in a block copolymer film that can serve as lithographic patterns.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 26, 2015
    Assignee: Board of Regents The University of Texas System
    Inventors: C. Grant Willson, William Durand, Christopher John Ellison, Christopher Bates, Takehiro Seshimo, Julia Cushen, Logan Santos, Leon Dean, Erica Rausch
  • Patent number: 9037214
    Abstract: In certain embodiments novel nanoparticles (nanowontons) are provided that are suitable for multimodal imaging and/or therapy. In one embodiment, the nanoparticles include a first biocompatible (e.g., gold) layer, an inner core layer (e.g., a non-biocompatible material), and a biocompatible (e.g., gold) layer. The first gold layer includes a concave surface that forms a first outer surface of the layered nanoparticle. The second gold layer includes a convex surface that forms a second outer surface of the layered nanoparticle. The first and second gold layers encapsulate the inner core material layer. Methods of fabricating such nanoparticles are also provided.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: May 19, 2015
    Assignee: The Regents of the University of California
    Inventors: Fanqing Chen, Louis-Serge Bouchard
  • Patent number: 9034197
    Abstract: The disclosure relates generally to a method for fabricating a patterned medium. The method includes providing a substrate with an exterior layer under a lithographically patterned surface layer, the lithographically patterned surface layer comprising a first pattern in a first region and a second pattern in a second region, applying a first masking material over the first region, transferring the second pattern into the exterior layer in the second region, forming self-assembled block copolymer structures over the lithographically patterned surface layer, the self-assembled block copolymer structures aligning with the first pattern in the first region, applying a second masking material over the second region, transferring the polymer block pattern into the exterior layer in the first region, and etching the substrate according to the second pattern transferred to the exterior layer in the second region and the polymer block pattern transferred to the exterior layer in the first region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: May 19, 2015
    Assignee: HGST NETHERLANDS B.V.
    Inventors: Jeffrey S. Lille, Kurt A. Rubin, Ricardo Ruiz, Lei Wan
  • Patent number: 9023388
    Abstract: A high-efficacy, long-acting formulation of silibinin, comprising silibinin solid dispersion, silibinin-loaded silica nanoparticles, slow-release matrix material and release enhancer, wherein the mass ratio of these components is silibinin solid dispersion:silibinin-loaded silica nanoparticles:slow-release matrix material:release enhancer=1:0.5˜1.25:0.1˜0.3:0.1˜0.3; the drug loading rate of the said silibinin-loaded silica nanoparticles is 51.29˜51.77%; the said silibinin solid dispersion contains povidone K30, soybean lecithin, acrylic resin IV, wherein the mass ratio between silibinin and other medical accessories is silibinin:povidone K30:soybean lecithin:acrylic resin IV=1:1˜3:0.3˜0.8:0.2˜0.5. Compared with the existing formulations, the half life of the high-efficacy, long-acting formulation of silibinin disclosed in this invention is 14.8 times longer while the mean residence time (MRT) of which is 4.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: May 5, 2015
    Assignee: Jiangsu University
    Inventors: Ximing Xu, Jiangnan Yu, Xia Cao, Yuan Zhu
  • Patent number: 9018649
    Abstract: A nanopatterned surface is prepared by forming a block copolymer film on a miscut crystalline substrate, annealing the block copolymer film, then reconstructing the surface of the annealed block copolymer film The method creates a well-ordered array of voids in the block copolymer film that is maintained over a large area. The nanopatterned block copolymer films can be used in a variety of different applications, including the fabrication of high density data storage media.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 28, 2015
    Inventors: Thomas P. Russell, Soojin Park, Ting Xu
  • Patent number: 9011705
    Abstract: The present invention relates to a method of forming polymer substrate with variable refractive index sensitivity, the method comprising the steps of: (a) contacting a metal-coated patterned mold with a polymer substrate at a temperature sufficient to deform said polymer substrate to thereby deposit a patterned mask of a metal film on the polymer substrate; and (b) etching away portions of said polymer substrate not covered by said patterned mask under conditions to form a region of variable refractive index sensitivity on said polymer substrate.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: April 21, 2015
    Assignee: Agency for Science, Technology and Research
    Inventors: Kwok Wei Shah, Xiaodi Su, Soo Jin Chua, Hong Yee Low
  • Patent number: 8993088
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald L. Westmoreland
  • Patent number: 8987138
    Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over the said porous dielectric film, and anisotropically and selectively etching the deposited material.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Kathryn Wilder Guarini
  • Publication number: 20150076137
    Abstract: According to a method for manufacturing a sheet-like heating element and a sheet-like heating element manufactured by the method of the present invention, cubics are pulverized into nanoparticles, the nanoparticle powder is mixed with carbon to become an original yarn, and the original yarn is cut to a length of between 0.2 mm and 0.8 mm and mixed into a pulp liquid to be formed into nanoparticle pulp. The sheet-like heating element forms a space where the particles can be rotated so as to allow 90% or higher far infrared radiation, and thus contributes to the health of users, entails a low defective rate since no bending occurs during the manufacturing, can be manufactured in quantity at low cost, and can be used for multiple purposes.
    Type: Application
    Filed: April 9, 2013
    Publication date: March 19, 2015
    Inventor: Sun Il Kim
  • Publication number: 20150061487
    Abstract: A cold cathode field emission electron source capable of emission at levels comparable to thermal sources is described. Emission in excess of 6 A/cm2 at 7.5 V/?m is demonstrated in a macroscopic emitter array. The emitter is comprised of a monolithic and rigid porous semiconductor nanostructure with uniformly distributed emission sites, and is fabricated through a room temperature process which allows for control of emission properties. These electron sources can be used in a wide range of applications, including microwave electronics and x-ray imaging for medicine and security.
    Type: Application
    Filed: October 20, 2014
    Publication date: March 5, 2015
    Inventors: Fred Sharifi, MYUNG-GYU KANG, HENRI LEZEC
  • Patent number: 8969148
    Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Maud Vinet, Sylvain Barraud, Laurent Grenouillet
  • Patent number: 8962017
    Abstract: A high-efficacy, long-acting formulation of silymarin, comprising silymarin solid dispersion, silymarin-loaded silica nanoparticles, slow-release matrix material and release enhancer, wherein the mass ratio of these components is silymarin solid dispersion:silymarin-loaded silica nanoparticles:slow-release matrix material:release enhancer=1:0.5˜1.25:0.1˜0.3:0.1˜0.3; the drug loading rate of the said silymarin-loaded silica nanoparticles is 51.95%-52.87%; the said silymarin solid dispersion contains povidone K30, soybean lecithin and acrylic resin IV, and the mass ratio between silymarin and other medical accessories in silymarin solid dispersion is silymarin:povidone K30:soybean lecithin:acrylic resin IV=1:1˜3:0.3˜0.8:0.2˜0.5. Compared with the existing formulations, the half life of the high-efficacy, long-acting formulation of silymarin disclosed in this invention is 2.3 times longer while the mean residence time (MRT) of which is 9.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: February 24, 2015
    Assignee: Jiangsu University
    Inventors: Ximing Xu, Jiangnan Yu, Shanshan Tong, Yuan Zhu, Xia Cao
  • Patent number: 8945406
    Abstract: A method for manufacturing a symbol on an exterior of an electronic device is provided. The method includes preparing a support layer, preparing a nanograting layer on the support layer, the nanograting layer including a first nanograting area corresponding to a preset symbol and a second nanograting area corresponding to an area other than the preset symbol, wherein each of the first nanograting area and the second nanograting area includes three-dimensional (3D) nanostructures and a pitch between the 3D nanostructures arranged in the first nanograting area is different from a pitch between the 3D nanostructures arranged in the second nanograting area.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-eun Chung, Il-yong Jung
  • Patent number: 8945700
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Donald L. Westmoreland
  • Patent number: 8927405
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8927968
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8927397
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20140370326
    Abstract: A method for forming porous metal structures and the resulting structure may include forming a metal structure above a substrate. A masking layer may be formed above the metal structure, and then etched using a reactive ion etching process with a mask etchant and a metal etchant. Etching the masking layer may result in the formation of a plurality of pores in the metal structure. In some embodiments, the metal structure may include a first end region, a second end region, and an intermediate region. Before etching the masking layer, a protective layer may be formed above the first end region and the second end region, so that the plurality of pores is contained within the intermediate region. In some embodiments, the intermediate metal region may be a nanostructure such as a nanowire.
    Type: Application
    Filed: June 18, 2013
    Publication date: December 18, 2014
    Inventors: Yann Astier, Jingwei Bai, Robert L. Bruce, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8907456
    Abstract: A method of fabricating integrated circuits is described. A multi-material hard mask is formed on an underlying layer to be patterned. In a first patterning process, portions of the first material of the hard mask are etched, the first patterning process being selective to etch the first material over the second material. In a second patterning process, portions of the second material of the hard mask are etched, the second patterning process being selective to etch the second material over the first material. The first and second patterning processes forming a desired pattern in the hard mask which is then transferred to the underlying layer.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: December 9, 2014
    Assignee: Olambda, Inc.
    Inventor: Haiqing Wei
  • Publication number: 20140352779
    Abstract: One embodiment is a nanostructured arrangement having a base and pyramidal features formed on the base. Each pyramidal feature includes sloping sides converging at a vertex. The nanostructured arrangement further includes a nanostructured surface formed on at least one of the sloping sides of at least one of the pyramidal features. The nanostructured surface has a quasi-periodic, anisotropic array of elongated ridge elements having a wave-ordered structure pattern. Each ridge element has a wavelike cross-section and oriented substantially in a first direction.
    Type: Application
    Filed: January 18, 2012
    Publication date: December 4, 2014
    Applicant: Wostec. Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov
  • Patent number: 8895337
    Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li
  • Patent number: 8887381
    Abstract: In one preferred aspects, methods are provided to produce a three-dimensional feature, comprising: (a) providing a nano-manipulator device; (b) positioning an article with the nano-manipulator device; and (c) manipulating the article to produce the three-dimensional feature. The invention relates to production of nanoscale systems that can be tailored with specific physical and/or electrical characteristics or need to have these characteristics modified. Methods and apparatus are presented that can construct three-dimensional nanostructures and can also modify existing nanostructures in three dimensions.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: November 18, 2014
    Inventor: Nicholas Antoniou
  • Patent number: 8877078
    Abstract: Disclosed are a method for recycling silica waste and a method for preparing nanoporous material and other valuable silica materials. More specifically, a method for preparing a nanoporous material by recycling silica-containing waste produced from a silica etching process in the synthesis of nanoporous carbon is provided. The present disclosure allows recycling of silica waste in an effective and environment-friendly manner, reduction of consumption of chemical materials, and reduction of chemical waste. Accordingly, the present disclosure enables effective preparation of various valuable nanoporous silica and other silica materials from silica waste released for production of various nanoporous materials.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: November 4, 2014
    Assignee: Korea University Research And Business Foundation
    Inventor: Jong-Sung Yu
  • Publication number: 20140322373
    Abstract: In certain embodiments, a material comprising one or more semiconductive substances is vaporized to generate a vapor phase condensate. The vapor phase condensate is allowed to form nanoparticles. The nanoparticles are annealed to yield substantially spherical nanoparticles.
    Type: Application
    Filed: July 14, 2014
    Publication date: October 30, 2014
    Inventor: Kalin Spariosu
  • Patent number: 8858815
    Abstract: Nanofibers are formed using electrospray deposition from microfluidic source. The source is brought close to a surface, and scanned in one embodiment to form oriented or patterned fibers. In one embodiment, the surface has features, such as trenches on a silicon wafer. In further embodiments, the surface is rotated to form patterned nanofibers, such as polymer nanofibers. The nanofibers may be used as a mask to create features, and as a sacrificial layer to create nanochannels.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Harold G. Craighead, Jun Kameoka
  • Patent number: 8861080
    Abstract: Wire grid polarizers, methods of fabricating a wire grid polarizer and display panels including a wire grid polarizer are provided, the methods include preparing a mold having a lower surface in which a plurality of parallel fine grooves are formed, and arranging the mold on a transparent substrate. The plurality of parallel fine grooves are filled with a conductive liquid ink. A plurality of parallel conductive nano wires are formed on the transparent substrate by curing the conductive liquid ink. The mold is removed.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-seung Lee, Jun-seong Kim, Ki-deok Bae
  • Patent number: 8841239
    Abstract: Nanoscale patterns prepared by lithography are used to direct the self-assembly of amphiphilic molecules to form patterned nanosubstrates having a desired distribution of chemical functional moieties. These patterns can be fabricated over a large area and require no special limitations on the chemistry the assembled amphiphiles. Hydrophilic/hydrophobic patterns can be created and used to direct the deposition of a single functional component to specific regions of the surface or to selectively assemble polymer blends to desired sites in a one step fashion with high specificity and selectivity. The selective deposition of functional moieties on a patterned surface can be based on electrostatic forces, hydrogen bonding, or hydrophobic interactions.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: September 23, 2014
    Assignees: Northeastern University, University of Massachusetts
    Inventors: Ahmed A. Busnaina, Joey L. Mead, Carol M. F. Barry, Ming Wei
  • Publication number: 20140273361
    Abstract: Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Wisconsin Alumni Research Foundation
    Inventors: Michael S. Arnold, Padma Gopalan, Nathaniel S. Safron, Myungwoong Kim, Jonathan Woosun Choi
  • Publication number: 20140273423
    Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jody A. Fronheiser, Jeremy A. Wahl, Kerem Akarvardar, Ajey P. Jacob, Daniel T. Pham
  • Patent number: 8834967
    Abstract: A method of reducing the diameter of pores formed in a graphene sheet includes forming at least one pore having a first diameter in the graphene sheet such that the at least one pore is surrounded by passivated edges of the graphene sheet. The method further includes chemically reacting the passivated edges with a chemical compound. The method further includes forming a molecular brush at the passivated edges in response to the chemical reaction to define a second diameter that is less than the initial diameter of the at least one pore.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Ahmed A. Maarouf, Glenn J. Martyna
  • Patent number: 8835215
    Abstract: A simple method is developed in the present invention for fabricating periodic ripple microstructures on the surface of an ITO film by using single-beam femtosecond laser pulses. The periodic ripple microstructures composed of self-organized nanodots can be directly fabricated through the irradiation of the femtosecond laser, without scanning. The ripple spacing of ˜800 nm, ˜400 nm and ˜200 nm observed in the periodic ripple microstructures can be attributed to the interference between the incident light and the scattering light of the femtosecond laser from the surface of the ITO film. In the present invention, the self-organized dots are formed by the constructive interference formed in the surface of the ITO film, where includes higher energy to break the In—O and Sn—O bonds and then form the In—In bonds. Therefore, the dots have higher surface current greater than other disconstructive regions of the ITO film.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 16, 2014
    Assignee: National Tsing Hua University
    Inventors: Jih-perng Leu, Chih-Wei Luo, Chih Wang, Jwo-Huei Jou
  • Patent number: 8835141
    Abstract: The present invention relates to systems, compositions and methods for the conversion of lignocellulosic material to recalcitrant cellulose and hydrolyzed sugars and products produced therefrom (e.g., biofuel, nano-fibrillated cellulose). In particular, the invention provides novel fractionation processes configured to integrate production of hydrolyzed sugars (e.g., for biofuel production) and recalcitrant cellulose (e.g., for nano-fibrillated cellulose production) from lignocellulosic material and methods of using the same (e.g., in the production of biofuel and nano-fibrillated cellulose). The invention is also directed to nanocellulose with morphologies of having a less entangled and slightly branched fibril network, and having the same thermal stability as of that of the initial lignocellulose feedstock.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: September 16, 2014
    Assignee: The United States of America as Represented by the Secretary of Agriculture
    Inventors: JunYong Zhu, Ronald Sabo, Craig Clemons
  • Publication number: 20140246811
    Abstract: The disclosure related to a method for making a nanowire structure. First, a free-standing carbon nanotube structure is suspended. Second, a metal layer is coated on a surface of the carbon nanotube structure. The metal layer is oxidized to grow metal oxide nanowires.
    Type: Application
    Filed: May 14, 2014
    Publication date: September 4, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: JIA-PING WANG, KAI-LI JIANG, QUN-QING LI, SHOU-SHAN FAN
  • Patent number: 8822124
    Abstract: A method of forming a pattern comprises diffusing an acid formed by irradiating a portion of a photosensitive layer, into an underlayer comprising an acid sensitive copolymer having acid decomposable groups and attachment groups covalently bonded to the surface of the substrate and/or forming an interpolymer crosslink. Diffusing comprises heating the underlayer and photosensitive layer. The acid sensitive group reacts with the diffused acid to form a polar region on the underlayer, with the shape of the pattern. The photosensitive layer is removed, forming a self-assembling layer comprising a block copolymer having a first block with an affinity for the polar region, and a second block having less affinity for the polar region. The first block forms a domain aligned to the polar region, and the second block forms another domain aligned to the first. Removing either domain exposes a portion of the underlayer.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: September 2, 2014
    Assignee: Dow Global Technologies LLC
    Inventors: Peter Trefonas, Phillip Dene Hustad, Cynthia Pierre
  • Publication number: 20140231379
    Abstract: A nanotip, is fabricated by modifying a precursor nanotip having an apex and a shank by applying an electric field in the presence of a reactive gas to perform field-assisted etching wherein atoms are preferentially removed from the shank by chemical interaction with the reactive gas, and controlling the reactive gas pressure and/or tip voltage to vary the electric field so as to promote field evaporation of apex atoms during fabrication of the nanotip and thereby control the overall profile of the resulting nano-tip. The method permits shaping of the overall tip profile.
    Type: Application
    Filed: September 26, 2012
    Publication date: August 21, 2014
    Applicants: NATIONAL RESEARCH COUNCIL OF CANADA, THE GOVERNORS OF THE UNIVERSITY OF ALBERTA
    Inventors: Jason L. Pitters, Radovan Urban, Robert A. Wolkow
  • Patent number: 8800138
    Abstract: A method for forming an electronic device on a flexible substrate conditions a surface of the flexible substrate to increase its malleability and to provide a conditioned substrate surface. A master surface is impressed against the conditioned substrate surface. The master surface is then released from the conditioned substrate surface, thereby forming a circuit-side surface on the substrate. The electronic device is then formed on the circuit-side surface. The substrate may be supported on a carrier during the method.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 12, 2014
    Assignee: Carestream Health, Inc.
    Inventors: Timothy J. Tredwell, Roger S. Kerr
  • Publication number: 20140217507
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8790534
    Abstract: A system and method are disclosed for the precision fabrication of Micro-Electro-Mechanical Systems (MEMS), Nano-Electro-Mechanical Systems (NEMS), Microsytems, Nanosystems, Photonics, 3-D integration, heterogeneous integration, and Nanotechology devices and structures. The disclosed system and method can also be used in any fabrication technology to increase the precision and accuracy of the devices and structures being made compared to conventional means of implementation. A platform holds and moves a substrate to be machined during machining and a plurality of lasers and/or ion beams are provided that are capable of achieving predetermined levels of machining resolution and precision and machining rates for a predetermined application. The plurality of lasers and/or ion beams comprises a plurality of the same type of laser and/or ion beam.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 29, 2014
    Assignee: Corporation for National Research Initiatives
    Inventor: Michael A. Huff
  • Patent number: 8790863
    Abstract: In a method for imaging a solid state substrate, a vapor is condensed to an amorphous solid water condensate layer on a surface of a solid state substrate. Then an image of at least a portion of the substrate surface is produced by scanning an electron beam along the substrate surface through the water condensate layer. The water condensate layer integrity is maintained during electron beam scanning to prevent electron-beam contamination from reaching the substrate during electron beam scanning. Then one or more regions of the layer can be locally removed by directing an electron beam at the regions. A material layer can be deposited on top of the water condensate layer and any substrate surface exposed at the one or more regions, and the water condensate layer and regions of the material layer on top of the layer can be removed, leaving a patterned material layer on the substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 29, 2014
    Assignee: President and Fellows of Harvard College
    Inventors: Daniel Branton, Anpan Han, Jene A. Golovchenko
  • Publication number: 20140202984
    Abstract: Methods for fabricating a nanopillared substrate surface include applying a polymer solution containing an amphiphilic block copolymer and a hydrophilic homopolymer to a substrate surface. The amphiphilic block copolymer and the hydrophilic homopolymer in the polymer solution self-assemble on the substrate surface to form a self-assembled polymer layer having hydrophobic domains adjacent to the substrate surface and hydrophilic domains extending into the self-assembled polymer layer. At least a portion of the hydrophilic domains may be removed to form a plurality of pores in the exposed surface of the self-assembled polymer layer. A protective layer may be deposited on the exposed surface as a mask for etching through the plurality of pores to form through-holes. A nanopillar-forming material may be deposited onto the substrate surface via the through-holes. Then, the remaining portion of the self-assembled polymer layer may be removed to expose a nanopillared substrate surface.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Inventors: Mark Alejandro Quesada, Jianguo Wang, Ying Zhang
  • Patent number: 8779561
    Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi Ho Jeong, Si Young Yang, Jae Wook Kwon, Jeong Hoon Park, Hyun Ju Yi, Choon Keun Lee
  • Patent number: 8778195
    Abstract: A method to fabricate an imprint mould in three dimensions including at least: a) forming at least one trench, of width W and depth h, in a substrate, thereby forming three surfaces including, a bottom of the at least one trench, sidewalls of the at least one trench, and a remaining surface of the substrate, called top of the substrate; b) forming alternate layers in the at least one trench, each having at least one portion perpendicular to the substrate, in a first material and in a second material which can be selectively etched relative to the first material; and c) selectively etching said portions of the layers perpendicular to the substrate.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 15, 2014
    Assignee: Commissariat a l' Energie Atomique
    Inventor: Stéfan Landis
  • Publication number: 20140193612
    Abstract: Material comprising sub-micrometer particles dispersed in a polymeric matrix. The materials are useful in article, for example, for numerous applications including display applications (e.g., liquid crystal displays (LCD), light emitting diode (LED) displays, or plasma displays); light extraction; electromagnetic interference (EMI) shielding, ophthalmic lenses; face shielding lenses or films; window films; antireflection for construction applications; and construction applications or traffic signs.
    Type: Application
    Filed: August 13, 2012
    Publication date: July 10, 2014
    Inventors: Ta-Hua Yu, Moses M. David, Douglas S. Dunn, Seth M. Kirk, Brant U. Kolb, William Blake Kolb, Mark A. Strobel, Jun-Ying Zhang
  • Patent number: 8772755
    Abstract: A nanowire field effect transistor (FET) device, includes a source region comprising a first semiconductor layer disposed on a second semiconductor layer, the source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, a drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the source region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes, and a nanowire channel member suspended by the source region and the drain region, wherein nanowire channel includes the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8758633
    Abstract: Disclosed is a method for fabricating nanofluidic channels having a height of from about 1 nm to about 10 nm. Generally, the method includes formation of doped silicon parallel strips in a silicon substrate, formation of a native oxide layer on the substrate, and etching of the native oxide layer at one of the strips to form a channel of a depth of between about 1 nm and about 10 nm. The method also includes bonding a second wafer to the surface, the second wafer including through etched windows to provide probe contacts to two of the parallel strips during use. These parallel strips provide high-frequency transmission lines in the device that can provide broadband dielectric spectroscopy measurement within the nanochannels.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 24, 2014
    Assignee: Clemson University
    Inventors: Pingshan Wang, Chunrong Song
  • Publication number: 20140166982
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8753912
    Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: William Graham, Supratik Guha, Oki Gunawan, George S. Tulevski, Kejia Wang, Ying Zhang
  • Patent number: 8753526
    Abstract: The present application relates to a porous thin film having holes, wherein the holes are formed in the top part and/or the bottom part of the thin film and the holes are linked to the pores of the thin film; and the present invention also relates to a production method for a porous thin film having holes, comprising the use of a particle alignment layer as a mold.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: June 17, 2014
    Assignee: Industry-University Cooperation Foundation Sogang University
    Inventors: Kyung Byung Yoon, Hyun Sung Kim, Myunpyo Hong, Na Pi Ha
  • Publication number: 20140151639
    Abstract: An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The germanium-free silicon material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the silicon-germanium alloy, and the silicon-germanium alloy is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the germanium-free silicon material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20140155253
    Abstract: Two methods of producing nano-pads of catalytic metal for growth of single walled carbon nanotubes (SWCNT) are disclosed. Both methods utilize a shadow mask technique, wherein the nano-pads are deposited from the catalytic metal source positioned under the angle toward the vertical walls of the opening, so that these walls serve as a shadow mask. In the first case, the vertical walls of the photo-resist around the opening are used as a shadow mask, while in the second case the opening is made in a thin layer of the dielectric layer serving as a shadow mask. Both methods produce the nano-pad areas sufficiently small for the growth of the SWCNT from the catalytic metal balls created after high temperature melting of the nano-pads.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 5, 2014
    Inventor: Alexander Kastalsky