Abstract: An article having a nanostructured surface and a method of making the same are described. The article can include a substrate and a nanostructured layer bonded to the substrate. The nanostructured layer can include a plurality of spaced apart nanostructured features comprising a contiguous, protrusive material and the nanostructured features can be sufficiently small that the nanostructured layer is optically transparent. A surface of the nanostructured features can be coated with a continuous hydrophobic coating. The method can include providing a substrate; depositing a film on the substrate; decomposing the film to form a decomposed film; and etching the decomposed film to form the nanostructured layer.

Abstract: Provided is a nanowire manufacturing method, comprising forming a plurality of grid patterns on a substrate, forming a nanowire on the grid patterns, and separating the grid pattern and the nanowire. According to the present invention, the width and height of the nanowire can be adjusted by controlling the wet-etching process time period, and the nanowire can be manufactured at a room temperature at low cost, the nanowire can be mass-manufactured and the nanowire with regularity can be manufactured even in case of mass production.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: A method of nanopatterning includes the steps of providing the resist film (12) and forming the pattern in the resist film (12). The resist film (12) includes an organosilicone compound having at least two vinyl groups, an organosilicone crosslinker different from the organosilicone compound, a catalyst, and a catalyst inhibitor. The cured resist film (12) includes the reaction product of the organosilicone compound having at least two vinyl groups and the organosilicone crosslinker different from the organosilicone compound, in the presence of the catalyst and the catalyst inhibitor. The article (10) includes a substrate (14), and the cured resist film (12) is disposed on the substrate (14). Due to the presence of the catalyst inhibitor in the resist film (12), the resist film (12) may be manipulated for hours at room temperature without curing. At the same time, the resist film (12) cures in a sufficiently short period of time to be commercially valuable.

Abstract: A method of controlling wetting characteristics is described. Such method includes forming and configuring nanostructures on a surface where controlling of the wetting characteristics is desired. Surfaces and methods of fabricating such surfaces are also described.

Abstract: A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.

Abstract: A process using the nanoimprint technique to form the diffraction grating for the DFB-LD is disclosed. The process includes (a) coating a resist for the EB exposure on a dummy substrate, (b) irradiating the resist as varying the acceleration voltage, (c) forming a resist pattern by developing the irradiated resist, (d) coating the SOG film on the patterned resist, (e) attaching the silica substrate on the cured SOG film, and (f) removing the dummy substrate with the resist from the SOG film and the silica substrate. Using the mold thus formed, the diffraction grating for the DFB-LD is formed by the nanoimprint technique.

Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.

Abstract: The invention provides apparatus for producing an extrudate product including a plurality of capillary channel. The apparatus comprises an extruder having an inlet, a die including an orifice having a predetermined outer shape and a plurality of needles each having a body including an internal conduit for fluid flow. Each needle further comprises an outlet from the internal conduit at an outlet end. The outlet end of each needle is arranged in a predetermined pattern substantially within the orifice of the die and the conduit of each needle is fluidly connected to a fluid source. In use extrudable material is fed into the extruder through the inlet. The extruder forces the extrudable material around the bodies of the needles towards the die and through the orifice in the die to produce an extrudate having substantially the predetermined outer shape.

Abstract: A method of making a nanostructure is provided that includes applying a thin, random discontinuous masking layer (105) to a major surface (103) of a substrate (101) by plasma chemical vapor deposition. The substrate (101) can be a polymer, an inorganic material, an alloy, or a solid solution. The masking layer (105) can include the reaction product of plasma chemical vapor deposition using a reactant gas comprising a compound selected from the group consisting of organosilicon compounds, metal alkyls, metal isopropoxides, metal acetylacetonates, and metal halides. Portions (107) of the substrate (101) not protected by the masking layer (105) are then etched away by reactive ion etching to make the nanostructures.

Abstract: Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the nanorod array. The contacts may allow I/V (current/voltage) characteristics of the nanorods to be measured.

Abstract: A process for manufacturing silicon-based nanoparticles by electrochemical etching of a substrate, wherein the substrate is a metallurgical-grade or upgraded metallurgical-grade silicon, the substrate including an impurity content greater than 0.01%.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.

Abstract: A method for forming a recess defect on a carbon nanotube is introduced. The method includes the following steps. A substrate with a surface is provided. A first carbon nanotube is deposed on the surface of the substrate. A second carbon nanotube is crossed with the first carbon nanotube. The second carbon nanotube crosses the first carbon nanotube and is in contact with the first carbon nanotube. A mask is deposited on substrate, the first carbon nanotube, and the second carbon nanotube. The substrate is etched to remove the second carbon nanotube and form a recess defect on the first carbon nanotube at a crossing position.

Abstract: High Hc (>4,000 Oe) and high Hk (>1 Tesla) has been achieved in FePt films as thin as 70 Angstroms. This was accomplished by starting with a relatively thick film having the required high coercivity, coating it with a suitable material such as Ta, and then using ion beam etching to remove surface material until the desired thickness was reached.

Abstract: A sheet structure has: a bundle structure including a plurality of linear structures made of carbon which are oriented in a predetermined direction; a covering layer covering the plurality of linear structures made of carbon; and a filling layer provided between the plurality of linear structures made of carbon covered with the covering layer. The thickness of the covering layer is not uniform in a direction crossing the predetermined direction.

Abstract: A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.

Abstract: A technique is provided for a structure. A substrate has a nanopillar vertically positioned on the substrate. A bottom layer is formed beneath the substrate. A top layer is formed on top of the substrate and on top of the nanopillar, and a cover layer covers the top layer and the nanopillar. A window is formed through the bottom layer and formed through the substrate, and the window ends at the top layer. A nanopore is formed through the top layer by removing the cover layer and the nanopillar.

Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).

Abstract: The present disclosure provides an article having (a) a substrate having a first nanostructured surface that is antireflective when exposed to air and an opposing second surface; and (b) a conductor micropattern disposed on the first surface of the substrate, the conductor micropattern formed by a plurality of traces defining a plurality of open area cells. The micropattern has an open area fraction greater than 80% and a uniform distribution of trace orientation. The traces of the conductor micropattern have a specular reflectance in a direction orthogonal to and toward the first surface of the substrate of less than 50%. Each of the traces has a width from 0.5 to 10 micrometer. The articles are useful in devices such as displays, in particular, touch screen displays useful for mobile hand held devices, tablets and computers.

Abstract: A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.

Abstract: Techniques for making nanowires with a desired diameter are provided. The nanowires can be grown from catalytic nanoparticles, wherein the nanowires can have substantially same diameter as the catalytic nanoparticles. Since the size or the diameter of the catalytic nanoparticles can be controlled in production of the nanoparticles, the diameter of the nanowires can be subsequently controlled as well. The catalytic nanoparticles are melted and provided with a gaseous precursor of the nanowires. When supersaturation of the catalytic nanoparticles with the gaseous precursor is reached, the gaseous precursor starts to solidify and form nanowires. The nanowires are separate from each other and not bind with each other to form a plurality of nanowires having the substantially uniform diameter.

Abstract: The present invention introduces a new technique allowing the fabrication of high-aspect ratio nanoscale semiconductor structures and local device modifications using FIB technology. The unwanted semiconductor sputtering in the beam tail region prevented by a thin slow-sputter-rate layer which responds much slower and mostly to the high-intensity ion beam center, thus acting as a saturated absorber funnel-like mask for the semiconductor. The protective layer can be deposited locally using FIB, thus enabling this technique for local device modifications, which is impossible using existing technology. Furthermore, such protective layers allow much higher resolution and nanoscale milling can be achieved with very high aspect ratios, e.g. Ti layer results in aspect ratio higher than 10 versus bare semiconductor milling ratio of about 3.

Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: Apparatus to deliver predetermined forces, containers to hold particulate material and media, media, and the associated parameters for operating such equipment along with methods and compositions provided by the apparatus and methods.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: Methods and devices for sequencing nucleic acids are disclosed herein. Devices are also provided herein for measuring DNA with nano-pores sized to allow DNA to pass through the nano-pore. The capacitance can be measured for the DNA molecule passing through the nano-pore. The capacitance measurements can be correlated to determine the sequence of base pairs passing through the nano-pore to sequence the DNA.

Abstract: A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.

Abstract: Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process.

Abstract: Articles of silicon nanowires were synthesized on metal substrates. The preparation minimized the formation of metal silicides and avoided the formation of islands of silicon on the metal substrates. These articles may be used as electrodes of silicon nanowires on current collectors.

Abstract: Methods for fabricating sub-lithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract: Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes subunits A and B, and will be self-assembled to form core structures spaced center-to-center by a distance of L0. The core structures are contained within a repeating pattern of polygonal unit cells. Distances from the core structures to various locations of the unit cells are calculated to determine desired distributions of subunit lengths.

Abstract: Nanopatterned surfaces are prepared by a method that includes forming a block copolymer film on a substrate, annealing and surface reconstructing the block copolymer film to create an array of cylindrical voids, depositing a metal on the surface-reconstructed block copolymer film, and heating the metal-coated block copolymer film to redistribute at least some of the metal into the cylindrical voids. When very thin metal layers and low heating temperatures are used, metal nanodots can be formed. When thicker metal layers and higher heating temperatures are used, the resulting metal structure includes nanoring-shaped voids. The nanopatterned surfaces can be transferred to the underlying substrates via etching, or used to prepare nanodot- or nanoring-decorated substrate surfaces.

Abstract: Two methods of producing nano-pads of catalytic metal for growth of single walled carbon nanotubes (SWCNT) are disclosed. Both methods utilize a shadow mask technique, wherein the nano-pads are deposited from the catalytic metal source positioned under the angle toward the vertical walls of the opening, so that these walls serve as a shadow mask. In the first case, the vertical walls of the photo-resist around the opening are used as a shadow mask, while in the second case the opening is made in a thin layer of the dielectric layer serving as a shadow mask. Both methods produce the nano-pad areas sufficiently small for the growth of the SWCNT from the catalytic metal balls created after high temperature melting of the nano-pads.

Abstract: A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed.

Abstract: A nanoflow detector cell comprises a nanoflow detection cell template defming a sample channel transverse template and a reference channel transverse template, generally parallel to the sample channel, and spaced apart from the sample channel. Clear capillary tubing extends through the sample channel, defming a sample chamber, a portion of the capillary tubing extends out of each end of the sample channel, and is shaped to the template.

Abstract: A field-emission device is disclosed. The device comprises a solid state structure formed of a crystalline material and an amorphous material, wherein an outer surface of the solid state structure is substantially devoid of the amorphous material, and wherein a p-type conductivity of the crystalline material is higher at or near the outer surface than far from the outer surface.

Abstract: A pattern forming method including: (a) forming a porous layer above an etching target layer; (b) forming an organic material with a transferred pattern on the porous layer; (c) forming, by use of the transferred pattern, a processed pattern in a transfer oxide film that is more resistant to etching than the porous layer; and (d) transferring the processed pattern to the etching target layer by use of the transfer oxide film as a mask.

Abstract: A device is made by forming sacrificial fibers on a substrate mold. The fibers and mold are covered with a first material. The substrate mold is removed, and the covered fibers are then removed to form channels in the first material.

Abstract: A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.

Abstract: A method for producing a matrix containing nanostructures. The method includes obtaining a layer having a thickness of 10 nm-100 ?m, wherein the layer contains organic macromolecules arranged in a nanopattern, staining the layer with a solution containing a salt so that a portion of the salt is retained in the layer, and removing the organic mcaromolecules from the layer to form a matrix containing nanostructures. Also within the scope of this invention are nanostructures prepared by this method.

Abstract: A nanopore device including a nanopore formed by penetrating a thin layer, a nanochannel formed at an entrance of the nanopore, and a filler in the nanochannel, as well as a method of fabricating the nanopore device and an apparatus including the nanopore device.

Abstract: A method of processing a graphene sheet material includes irradiating UV ray to a graphene sheet material in an atmosphere containing a first substance to inactivate an edge of the graphene sheet material by substituting an end group connected to the edge of the graphene sheet material with more stable functional group generated from the first substance, and irradiating UV ray to a surface of the graphene sheet material in an atmosphere containing a second substance containing oxygen to activate the second substance, and oxidize and remove a graphene sheet contained in the graphene sheet material sequentially from a surface side.

Abstract: A method for making light emitting diode includes the following steps. A substrate is provided. A first semiconductor layer is grown on a surface of the substrate. A patterned mask layer is located on a surface of the first semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures, a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed first semiconductor layer is etched to form a protruding pair. A number of three-dimensional nano-structures are formed. An active layer and a second semiconductor layers are grown on the number of three-dimensional nano-structures in that order. The substrate is removed and a surface of the first semiconductor layer is exposed. A first electrode is applied to cover the exposed surface. A second electrode is electrically connected with the second semiconductor layer.

Abstract: Devices, methods, and techniques for frequency-dependent optical switching are provided. In one embodiment, a device includes a substrate, a first optical-field confining structure located on the substrate, a second optical-field confining structure located on the substrate, and a composite structure located between the first and second optical-field confining structures. The second optical-field confining structure may be spaced apart from the first optical-field confining structure. The composite structure may include an embedding structure with a surface to receive photons and multiple quantum structures located in the embedding structure.

Abstract: A method for making light emitting diode includes following steps. A substrate is provided. A first semiconductor layer is grown on a surface of the substrate. A patterned mask layer is located on a surface of the first semiconductor layer, and the patterned mask layer includes a number of bar-shaped protruding structures, a slot is defined between each two adjacent protruding structures to expose a portion of the first semiconductor layer. The exposed first semiconductor layer is etched to form a protruding pair. A number of three-dimensional nano-structures are formed by removing the patterned mask layer. An active layer and a second semiconductor layers are grown on the number of three-dimensional nano-structures in that order. A first electrode is electrically connected with the first semiconductor layer. A second electrode is located to cover the entire surface of the second semiconductor layer which is away from the active layer.

Abstract: A method for fabricating a micro-structure is provided, which can simply and easily fabricate the micro-structure by a batch process of directly forming a highly aligned nano-material array on a micro-structure to be used as an adhesive material during plastic deformation of the micro-structure without the use of existing complicated fabrication process.

Abstract: The present invention relates to a method for producing a thin single crystal silicon having large surface area, and particularly relates to a method for producing a silicon micro and nanostructure on a silicon substrate (or wafer) and lifting off the silicon micro and nanostructure from the silicon substrate (or wafer) by metal-assisted etching. In this method, a thin single crystal silicon is produced in the simple processes of lifting off and transferring the silicon micro and nanostructure from the substrate by steps of depositing metal catalyst on the silicon wafer, vertically etching the substrate, laterally etching the substrate. And then, the surface of the substrate is processed, for example planarizing the surface of the substrate, to recycle the substrate for repeatedly producing thin single crystal silicons. Therefore, the substrate can be fully utilized, the purpose of decreasing the cost can be achieved and the application can be increased.

Abstract: A composite negative active material including metal nanostructures disposed on one or more of a surface and inner pores of a porous carbon-based material, a method of preparing the material, and a lithium secondary battery including the material.