Abstract: Provided are a light emitting diode (LED) using a Si nanowire as an emission device and a method of fabricating the same. The LED includes: a semiconductor substrate; first and second semiconductor protrusions disposed on the semiconductor substrate to face each other; a semiconductor nanowire suspended between the first and second semiconductor protrusions; and first and second electrodes disposed on the first and second protrusions, respectively.

Abstract: The invention provides a method for forming a patterned material layer on a structure, by condensing a vapor to a solid condensate layer on a surface of the structure and then localized removal of selected regions of the condensate layer by directing a beam of energy at the selected regions. The structure can then be processed, with at least a portion of the patterned solid condensate layer on the structure surface, and then the solid condensate layer removed. Further there can be stimulated localized reaction between the solid condensate layer and the structure by directing a beam of energy at at least one selected region of the condensate layer.

Abstract: A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide layer to narrow the first set of voids to become a second set of voids on the substrate. A polysilicon layer is deposited over the second oxide layer, the first oxide layer and the substrate. A third set of voids is etched into the polysilicon layer. Further etching widens the third set of voids to define a fourth set of voids to expose the first oxide layer and the substrate. The first oxide layer and the substrate is deeply etched to define beams and trenches in the substrate.

Abstract: The present invention provides nanoprisms etched to generate triangular framework structures. These triangular nanoframes possess no strong surface plasmon bands in the ultraviolet or visible regions of the optical spectrum. By adding a mild reducing agent, metal ions remaining in solution can be reduced, resulting in metal plating and reformation of nanoprisms. The extent of the backfilling process can be controlled, allowing the formation of novel nanoprisms with nanopores. This back-filling process is accompanied by a regeneration of the surface plasmon bands in the UV-visible spectrum.

Abstract: A method of producing ultrafine particles by vaporization comprising: vaporizing a target by sputtering; causing particles that fly from the target by vaporization to be deposited on an oil surface; and recovering the oil on which the flown particles have deposited to obtain individually dispersed ultrafine particles.

Abstract: An imprint apparatus configured such that it can press a laminate structure in which a magnetic film and a resist film are sequentially laminated on a substrate. The imprint apparatus includes a first press plate configured to mount the laminate structure, a second press plate adapted for sandwiching the laminate structure, a stamper placed on a surface of the second press plate, and has projections and recesses configured to be transferred onto the resist film, and a light source configured to dispose on the same plane as the laminate structure, and is oriented so that the light source can shine the resist film.

Abstract: A method of shrinking a film comprises the steps of providing a shrink film and exposing the film to an amount of radiation energy effective to activate the shrink characteristic of the film. The film comprises one or more thermoplastic polymers and at least about 0.001 weight % of single-walled carbon nanotube material based on the weight of the film.

Abstract: A method for forming quantum dots includes forming a superlattice structure that includes at least one nanostrip protruding from the superlattice structure, providing a quantum dot substrate, transferring the at least one nanostrip to the quantum dot substrate, and removing at least a portion of the at least one nanostrip from the substrate. The superlattice structure is formed by providing a superlattice substrate, forming alternating layers of first and second materials on the substrate to form a stack, cleaving the stack to expose the alternating layers, and etching the exposed alternating layers with an etchant that etches the second material at a greater rate than the first to form the at least one nanostrip.

Abstract: In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then permitting the device to solidify. Advantageous guiding conditions include adjacent spaced apart or contacting surfaces to control surface structure and preserve vertically. Unconstrained boundaries to permit smoothing of edge roughness. In an advantageous embodiment, a flat planar surface is disposed overlying a patterned nanostructure surface and the surface is liquified by a high intensity light source to repair or enhance the nanoscale features.

Abstract: Nanotube films and articles and methods of making the same are disclosed. A conductive article includes an aggregate of nanotube segments in which the nanotube segments contact other nanotube segments to define a plurality of conductive pathways along the article. The nanotube segments may be single walled carbon nanotubes, or multi-walled carbon nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. The articles so formed may be disposed on substrates, and may form an electrical network of nanotubes within the article itself. Conductive articles may be made on a substrate by forming a nanotube fabric on the substrate, and defining a pattern within the fabric in which the pattern corresponds to the conductive article.

Abstract: A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.

Abstract: A plurality of semiconductor nanoparticles having an elementally passivated surface are provided. These nanoparticles are capable of being suspended in water without substantial agglomeration and substantial precipitation on container surfaces for at least 30 days. The method of making the semiconductor nanoparticles includes reacting at least a first reactant and a second reactant in a solution to form the semiconductor nanoparticles in the solution. A first reactant provides a passivating element which binds to dangling bonds on a surface of the nanoparticles to passivate the surface of the nanoparticles. The nanoparticle size can be tuned by etching the nanoparticles located in the solution to a desired size.

Abstract: The invention provides high surface area talc compositions by a novel hybrid milling method or soaking method. The hybrid milling method comprises dry milling talc powder followed by mixing with water and wet milling to provide a nano-talc slurry with high surface area, also of the invention. The soaking method comprises dry milling talc powder followed by mixing with water and soaking to provide high surface area nano-talc slurry. The slurry may be dewatered and dried to provide dry nano-talc powder. The nano-talc powder provided by the invention is a novel hydrophilic talc composition. Further embodiments of the invention include organic solvent dispersed nano-talc slurries and methods for providing the same. These slurries can be used to provide polymer nano-talc composites in the form of coatings, sealing and gasketing materials, foams, extruded thermoplastic and thermoset sheets and films, thermoplastic pellets, thermoplastic and thermoset molded polymer composite articles.

Abstract: Disclosed is a magnetic memory apparatus which comprises a patterned magnetic recording medium in which multilayered films each having a first magnetic layer, a nonmagnetic metal layer or a nonmagnetic insulating layer and a second magnetic layer deposited discretely on a conductive electrode layer formed on a substrate, and a cantilever array having a plurality of cantilevers each having a conductive chip at its distal end. This provides a magnetic solid memory apparatus that has a large memory capacity and a super fast transfer rate, the merits of a hard disk apparatus, and a nanostructure and low power consumption, which are the merits of a semiconductor memory.

Abstract: Particles, which may include nanoparticles, are mixed with carbon nanotubes and deposited on a substrate to form a cold cathode. The particles enhance the field emission characteristics of the carbon nanotubes. An additional activation step may be performed on the deposited carbon nanotube mixture to further enhance the emission of electrons.

Abstract: A method of producing a thin film bulk acoustic resonator having a piezoelectric layer, a first electrode joined to a first surface of the piezoelectric layer, and a second electrode joined to a second surface of the piezoelectric layer, which is located at the opposite side to the first surface, including the steps of forming a pit on a surface of a substrate; filling the pit with a sacrificial layer; polishing a surface of the sacrificial layer so that the RMS variation of a height of the surface of the sacrificial layer is equal to 25 nm or less; forming the first electrode over a partial area of the surface of the sacrificial layer and a partial area of the surface of the substrate; forming the piezoelectric layer on the first electrode so that RMS variation of a height of the second surface of the piezoelectric layer is equal to 5% or less of a thickness of the piezoelectric layer; forming the second electrode on the piezoelectric layer; and removing the sacrificial layer from the inside of the pit by et

Abstract: Present invention provides enabling techniques of integrating novel nanotube elements into semiconductor devices, particularly in transistors, as gate channels or/and as interconnects. This is done in a series of process steps, which consist of fabricating magnetic-core-containing nanotubes of selected size (diameter and length), filtration of nanotube powders, preparing nanotube precursor in aqueous chemicals to form colloidal solutions of proper concentration, dispersing nanotube-containing solutions onto wafer surface, and finally positioning nanotubes at desired locations by magnetic means to complete nanotube device structure. The key to this invention is to provide miniature nanotubes with tangible physical properties, in this case, magnetic properties, so that they can be aligned, filtered, and precisely directed to desired locations for device application. Such processes enable nanotubes to be compatible with typical semiconductor wafer processing technologies.