Abstract: A Si-based light emitting diode structure and a method for fabricating the Si-based light emitting diode structure are each predicated upon a multilayer material layer that comprises alternating, interposed and laminated sub-layers of: (1) a group IV nanocrystal material; and (2) an erbium or neodymium doped dielectric material. The light emitting diode structure is preferably laterally actuated to provide both efficient photoluminescence and electroluminescence. The group IV nanocrystal material may comprise a silicon nanocrystal material and the doped dielectric material may comprise an erbium doped silicon oxide material.

Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Abstract: In a method for making a liquid crystal display module, a first polarizing layer and a liquid crystal module are provided. The liquid crystal module includes an upper substrate, an upper electrode layer, a first alignment layer, a liquid crystal layer, a second alignment layer, a thin film transistor panel, and a second polarizing layer stacked in sequences. At least two driving-sensing electrodes are disposed on a surface of the upper substrate. The at least two driving-sensing electrodes are spaced from each other and spaced from the upper electrode layer. A free-standing transparent conductive layer is laid on a surface of the first polarizing layer to form a touch polarizer. The touch polarizer is fixed to the upper substrate to form the liquid crystal display module. The at least two driving-sensing electrodes are electrically connected with the transparent conductive layer.

Abstract: An electrochemical sensor for sensing a gaseous analyte includes a substrate having at least two electrodes disposed thereon, and a carbon nanotube-polyaniline (CNT/PANI) film disposed on the substrate and in contact with at least two electrodes. The CNT/PANI film includes carbon nanotubes coated with a thin layer of polyaniline. The thickness of the polyaniline coating is such that electron transport can occur along and/or between the carbon nanotubes.

Abstract: Semiconductor nanostrings, mats containing semiconductor nanostrings, and devices and modules, such as, solar energy generating modules, including semiconductor nanostrings or mats containing semiconductor nanostrings are described herein. Methods for making multi-layer nanostrings and mats and other devices including multi-layer nanostrings are also described.

Abstract: A method for manufacturing a photodiode including the steps of providing a substrate, solution depositing a quantum nanomaterial layer onto the substrate, the quantum nanomaterial layer including a number of quantum nanomaterials having a ligand coating, and applying a thin-film oxide layer over the quantum nanomaterial layer.

Abstract: A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gate electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.

Abstract: The nanoparticle production device includes a target provided with a nanoparticle source surface, and a magnetron generating a first magnetic field, the target being mounted on the magnetron and the first magnetic field forming field lines at the level of the nanoparticle source surface. The device further includes balancing means of the first magnetic field at the level of the target, arranged to close fleeing field lines of the first magnetic field and to keep said lines closed at the level of said nanoparticle source surface, said balancing means being distinct from the magnetron.

Abstract: A method of making a neutron detector such as a microstructured semiconductor neutron detector is provided. The method includes the step of providing a particle-detecting substrate having a surface and a plurality of cavities extending into the substrate from the surface. The method also includes filling the plurality of cavities with a neutron-responsive material. The step of filling including the step of centrifuging nanoparticles of the neutron-responsive material with the substrate for a time and a rotational velocity sufficient to backfill the cavities with the nanoparticles.

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: The method of forming carbon nanotubes from carbon-rich fly ash is a chemical vapor deposition-based method for forming carbon nanotubes from recycled carbon-rich fly ash. The method includes first ultrasonically treating the carbon-rich fly ash to produce an ultrafine powdered ash, and then reacting the ultrafine powdered ash in a low pressure chemical vapor deposition reactor to form the carbon nanotubes. The ultrasonic treatment of the carbon-rich fly ash includes the steps of dissolving the carbon-rich fly ash in water to form a solution, then sonicating the solution, separating the ultrafine powdered ash from the solution, and finally drying the ultrafine powdered ash. The method provides for total conversion of the carbon-rich fly ash to carbon nanotubes having a variety of differing diameters and lengths, including multi-walled carbon nanotubes with a high degree of wall graphitization and C?C double bonds stretching at 1635 cm?1.

Abstract: In one aspect, a method comprises: providing a substrate having at least one layer in which the patterned dot array is to be fabricated; depositing a nanoparticle layer, wherein the nanoparticle layer comprises one or more surfactants and nanoparticles coated with the one or more surfactants; treating the one or more surfactants that coat the nanoparticles and the portions of the one or more surfactants that fill the spaces among the nanoparticles; removing the portions of the one or more surfactants that fill the spaces among the nanoparticles to expose portions of the at least one layer in which the patterned dot array is to be fabricated; etching the exposed portions of the at least one layer in which the patterned dot array is to be fabricated; and removing at least a portion of the nanoparticles.

Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.

Abstract: The present invention relates to a method for producing small structures includes: depositing a mask on a surface of a substrate; and evaporating a source material under such evaporation condition performed at such pressure to form a layer onto both a shadowed surface area and a non-shadowed surface area of the mask and the substrate.

Abstract: Disclosed is a method for carbon coating on lithium titanium oxide-based anode active material nanoparticles. The method includes (a) introducing a lithium precursor solution, a titanium precursor solution and a surface modifier solution into a reactor, and reacting the solutions under supercritical fluid conditions to prepare a solution including nanoparticles of an anode active material represented by Li4Ti5O12, (b) separating the anode active material nanoparticles from the reaction solution, and (c) calcining the anode active material nanoparticles to uniformly coat the surface of the nanoparticles with carbon. Further disclosed are carbon-coated lithium titanium oxide-based anode active material nanoparticles produced by the method. In the anode active material nanoparticles, lithium ions are transferred rapidly. In addition, the uniform carbon coating ensures high electrical conductivity, allowing the anode active material nanoparticles to have excellent electrochemical properties.

Abstract: A method of forming a strained semiconductor channel, comprising: forming a relaxed SiGe layer on a semiconductor substrate; forming a dielectric layer on the relaxed SiGe layer and forming a sacrificial gate on the dielectric layer, wherein the dielectric layer and the sacrificial gate form a sacrificial gate structure; depositing an interlayer dielectric layer, which is planarized to expose the sacrificial gate; etching to remove the sacrificial gate and the dielectric layer to form an opening; forming a semiconductor epitaxial layer by selective semiconductor epitaxial growth in the opening; depositing a high-K dielectric layer and a metal layer; and removing the high-K dielectric layer and metal layer covering the interlayer dielectric layer by planarizing the deposited metal layer and high-K dielectric layer to form a metal gate. A semiconductor device manufactured by this process is also provided.

Abstract: Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.

Abstract: A method of formation of nanowires at a surface of a substrate attached to a solid immersion lens. The method includes formation of a catalyst element at the surface of the substrate and growth of nanowires from the catalyst element formed at the surface of the substrate. The catalyst element is a metal nanoparticle and the formation of the catalyst element at the surface of the substrate deposits the metal nanoparticle using a light beam focused by the solid immersion lens at the surface of the substrate.

Abstract: The present invention relates to carbon nanocomposite sorbents. The present invention provides carbon nanocomposite sorbents, methods for making the same, and methods for separation of a pollutant from a gas that includes that pollutant. Various embodiments provide a method for reducing the mercury content of a mercury-containing gas.

Abstract: The present teachings disclose a surface coating composition. The surface coating composition includes fluorine containing particles, aerogel particles and positive tribocharging particles. The surface coating is useful as the release layer for fuser members.

Abstract: A technique for a nanodevice is provided. The nanodevice includes a fluidic cell, and a membrane dividing the fluidic cell. A nanopore is formed through the membrane, and the nanopore is coated with an organic compound. A first part of the organic compound binds to a surface of the nanopore and a second part of the organic compound is exposed freely inside of the nanopore. The second part of the organic compound is configured to be switched among a first neutral hydrophilic end group, a second negatively charged hydrophilic end group, and a third neutral hydrophobic end group based on a switching mechanism.

Abstract: Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active species on the halogen-sensitive metal-including layer, the metal-including active species being derived from a non-halogenated metal oxide precursor. The example method also includes reacting an oxygen-containing reactant with the metal-including active species to form the metal oxide protective layer.

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract: Disclosed is a method of manufacturing a porous graphene film representing superior electrical properties. The method includes preparing a graphene/polymer composite dispersed solution by adding polymer particles to a first graphene dispersed solution obtained by dispersing graphene powders into a solvent, manufacturing a graphene/polymer composite film by using the graphene/polymer composite dispersed solution, and manufacturing the porous graphene film by removing the polymer particles from the graphene/polymer composite film.

Abstract: Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.

Abstract: An electronic device housing includes a substrate and a nano titanium dioxide coating formed on the substrate. The nano titanium dioxide coating has a thickness of about 10-100 nm. The nano titanium dioxide coating is formed of rutile crystals or composite crystals formed of rutile and anatase. A method for making the electronic device is also described.

Abstract: A process for forming thermoelectric nanoparticles includes the steps of providing a core material and a bismuth containing compound in a reverse micelle; providing a tellurium containing compound either in or not in a reverse micelle; reacting the bismuth containing compound with the tellurium containing compound in the presence of a base, forming a composite thermoelectric nanoparticle having a core and shell structure.

Abstract: Toner particles include a shell and a core, wherein the shell includes charge control agent-treated spacer particles that cause protrusions from the toner particle surface.

Abstract: A quality control system for the manufacture of carbon nanostructure-laden substrates includes a resistance measurement module for continuously measuring resistance of the carbon nanostructure (CNS)-laden substrate.

Abstract: A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.

Abstract: There are provided a carbon wire using CNT or a similar carbon filament having a sufficiently low electrical resistance value, and a wire assembly employing that carbon wire. A carbon wire (1) includes an assembly portion (3) and a graphite layer (4). The assembly portion (3) is configured of a plurality of carbon filaments implemented as carbon nanotubes (2) in contact with one another. The graphite layer (4) is provided at an outer circumference of the assembly portion (3).

Abstract: The invention relates to light-emitting devices, and related components, systems and methods. In one aspect, the present invention is related to light emitting diode (LED) light extraction efficiency. A non-limiting example, the application teaches a method for improving light emitting diode (LED) extraction efficiency, by providing a nano-rod light emitting diode; providing quantum wells; and reducing the size of said nano-rod LED laterally in the quantum-well plane (x and y), thereby improving LED extraction efficiency.

Abstract: A process for forming a porous nanoscale membrane is described. The process involves applying a nanoscale film to one side of a substrate, where the nanoscale film includes a semiconductor material; masking an opposite side of the substrate; etching the substrate, beginning from the masked opposite side of the substrate and continuing until a passage is formed through the substrate, thereby exposing the film on both sides thereof to form a membrane; and then simultaneously forming a plurality of randomly spaced pores in the membrane. The resulting porous nanoscale membranes, characterized by substantially smooth surfaces, high pore densities, and high aspect ratio dimensions, can be used in filtration devices, microfluidic devices, fuel cell membranes, and as electron microscopy substrates.

Abstract: A process for fabricating a nanochannel system using a combination of microelectromechanical system (MEMS) microfabrication techniques and atomic force microscopy (AFM) nanolithography. The nanochannel system, fabricated on either a glass or silicon substrate, has channel heights and widths on the order of single to tens of nanometers. The channel length is in the micrometer range. The nanochannel system is equipped with embedded micro or nanoscale electrodes, positioned along the length of the nanochannel for electron tunneling based characterization of nanoscale particles in the channel. Anodic bonding is used to cap off the nanochannel with a cover chip.

Abstract: Two methods of producing nano-pads of catalytic metal for growth of single walled carbon nanotubes (SWCNT) are disclosed. Both methods utilize a shadow mask technique, wherein the nano-pads are deposited from the catalytic metal source positioned under the angle toward the vertical walls of the opening, so that these walls serve as a shadow mask. In the first case, the vertical walls of the photo-resist around the opening are used as a shadow mask, while in the second case the opening is made in a thin layer of the dielectric layer serving as a shadow mask. Both methods produce the nano-pad areas sufficiently small for the growth of the SWCNT from the catalytic metal balls created after high temperature melting of the nano-pads.

Abstract: Methods for fabricating graphene nanoelectronic devices with semiconductor compatible processes, which allow wafer scale fabrication of graphene nanoelectronic devices, is provided. One method includes the steps of preparing a dispersion of functionalized graphene in a solvent; and applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate.

Abstract: Photovoltaic cells having copper contacts can be made by using copper nanoparticles during their fabrication. Such photovoltaic cells can include a copper-based current collector located on a semiconductor substrate having an n-doped region and a p-doped region. The semiconductor substrate is configured for receipt of electromagnetic radiation and generation of an electrical current therefrom. The copper-based current collector includes an electrically conductive diffusion barrier disposed on the semiconductor substrate and a copper contact disposed on the electrically conductive diffusion barrier. The copper contact is formed from copper nanoparticles that have been at least partially fused together. The electrically conductive diffusion barrier limits the passage of copper therethrough.

Abstract: A method of manufacturing an electrical conductor includes providing a substrate layer, depositing a surface layer on the substrate layer that has pores at least partially exposing the substrate layer, and forming graphene deposits in the pores. Optionally, the graphene deposits may be formed only in the pores. The graphene deposits may be formed along the exposed portions of the substrate layer. The graphene layers may be selectively deposited or may be deposited to cover an entire layer. Optionally, the forming of the graphene deposits may include processing the electrical conductor using a chemical vapor deposition process using an organic compound precursor and heat of sufficient temperature to facilitate graphene growth on the metal compound comprising the substrate layer.

Abstract: A method for fabricating semiconductor nanowire includes the following steps: providing a metal substrate in a reactor; filling the reactor with an inert gas; heating and maintaining the reactor in a reaction temperature, raising the pressure in the reactor to a first predetermined pressure, and then passing a reacting precursor into the reactor; keeping passing the reacting precursor to raising the pressure of the reactor to a second predetermined pressure; and, maintaining the second predetermined pressure for a predetermined duration, so as to form semiconductor nanowires on the metal bulk. Accordingly, the method of the invention is capable of forming semiconductor nanowires on metal substrate, so that the processes for fabricating semiconductor nanowires can be simplified.

Abstract: Technologies are generally described for a system and process effective to coat a substance with graphene. A system may include a first container including graphene oxide and water and a second container including a reducing agent and the substance. A third container may be operative relationship with the first container and the second container. A processor may be in communication with the first, second and third containers. The processor may be configured to control the third container to receive the graphene oxide and water from the first container and to control the third container to receive the reducing agent and the substance from the second container. The processor may be configured to control the third container to mix the graphene oxide, water, reducing agent, and substance under sufficient reaction conditions to produce sufficient graphene to coat the substance with graphene to produce a graphene coated substance.

Abstract: The disclosure provides an electromagnetic shielding composite material, and a method for manufacturing the same. The electromagnetic shielding composite material includes: a polymer sheet; and an acicular carbon nanotube layer including acicular portions of carbon nanotubes fixed on the polymer sheet. The method for manufacturing the electromagnetic shielding composite material includes: preparing a carbon nanotube dispersion solution; applying the carbon nanotube dispersion solution to the surface of a polymer sheet; and drying the polymer sheet to which the carbon nanotube dispersion solution is applied and then forming an acicular structure of carbon nanotubes on the polymer sheet. The composite material has superb electromagnetic wave shielding properties suitable for a variety of electronics applications.

Abstract: The present invention relates to a method of manufacturing a heterogeneous catalyst using space specificity, comprising: depositing a metal in a core of micelles provided on a substrate; depositing an oxide around a shell of the micelles after the deposition of the metal in the core of the micelle; and reducing the metal in the core of the micelles after the deposition of the oxide, then, removing the micelles, and a method for generation of hydrogen through decomposing water in the presence of the heterogeneous catalyst prepared according to the aforesaid method under a light source.

Abstract: The present disclosure relates to a nanocomposite material containing carbon nanotube coated glass fiber and graphite, in which fiber-shaped conductive particles obtained by coating a glass fiber with carbon nanotube as a conductive material with a good electromagnetic wave shielding property are hybridized with graphite sheets having a nanometer thickness and having an excellent heat conductivity, thereby creating a nanocomposite material with excellent electromagnetic wave shielding and heat dissipation properties. The nanocomposite material may be applied to a wide variety of electronics fields requiring both electromagnetic wave shielding and heat dissipation property, such as automotive electronic component housings, components of an electric car, mobile phones, and display devices.

Abstract: Technologies are generally described for a membrane that may incorporate a graphene layer perforated by a plurality of nanoscale pores. The membrane may also include a gas sorbent that may be configured to contact a surface of the graphene layer. The gas sorbent may be configured to direct at least one gas adsorbed at the gas sorbent into the nanoscale pores. The nanoscale pores may have a diameter that selectively facilitates passage of a first gas compared to a second gas to separate the first gas from a fluid mixture of the two gases. The gas sorbent may increase the surface concentration of the first gas at the graphene layer. Such membranes may exhibit improved properties compared to conventional graphene and polymeric membranes for gas separations, e.g., greater selectivity, greater gas permeation rates, or the like.

Abstract: In certain examples, a porous silica-based matrix may be formed. In an exemplary embodiment, using sol gel methods, a coating solution of or including metal alkoxides such as TEOS and porous nanoparticles such as mesoporous silica may be used to form a layer(s) of or including silica and porous nanoparticles in a solid matrix directly or indirectly on a glass substrate. The coated article may be heat treated (e.g., thermally tempered). The layer of the porous silica-based matrix may be used as a broadband anti-reflective coating.

Abstract: A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.

Abstract: Improved silicon/germanium nanoparticle inks are described that have silicon/germanium nanoparticles well distributed within a stable dispersion. In particular the inks are formulated with a centrifugation step to remove contaminants as well as less well dispersed portions of the dispersion. A sonication step can be used after the centrifugation, which is observed to result in a synergistic improvement to the quality of some of the inks. The silicon/germanium ink properties can be engineered for particular deposition applications, such as spin coating or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon/germanium nanoparticles. The silicon/germanium nanoparticles are well suited for forming semiconductor components, such as components for thin film transistors or solar cell contacts.

Abstract: A technique for embedding a nanotube in a nanopore is provided. A membrane separates a reservoir into a first reservoir part and a second reservoir part, and the nanopore is formed through the membrane for connecting the first and second reservoir parts. An ionic fluid fills the nanopore, the first reservoir part, and the second reservoir part. A first electrode is dipped in the first reservoir part, and a second electrode is dipped in the second reservoir part. Driving the nanotube into the nanopore causes an inner surface of the nanopore to form a covalent bond to an outer surface of the nanotube via an organic coating so that the inner surface of the nanotube will be the new nanopore with a super smooth surface for studying bio-molecules while they translocate through the nanotube.

Abstract: A method includes the steps of receiving a conductor element formed from a plurality of carbon nanotubes; and exposing the conductor element to a controlled amount of a dopant so as to increase the conductance of the conductor element to a desired value, wherein the dopant is one of bromine, iodine, chloroauric acid, hydrochloric acid, hydroiodic acid, nitric acid, and potassium tetrabromoaurate. A method includes the steps of receiving a conductor element formed from a plurality of carbon nanotubes; and exposing the conductor element to a controlled amount of a dopant solution comprising one of chloroauric acid, hydrochloric acid, nitric acid, and potassium tetrabromoaurate, so as to increase the conductance of the conductor element to a desired value.