Abstract: A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.

Abstract: An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and each cell is patterned to have a C-shape in the horizontal plane. The cell thereby operates by C-mode switching to provide stability against accidental writing by half-selection. During operation, switching of a cell's magnetization is accomplished with the assist of the pulsed magnetic fields of additional word lines that are formed either orthogonal to or parallel to the existing bit lines and that can carry currents in either direction as required to provide the assist.

Abstract: An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction.

Abstract: A memory includes: memory devices that each store data of one bit; and a read unit that, by using one predetermined memory device of the memory devices that are included in a memory block having a predetermined unit number of the memory devices as an inversion flag device, reads out data of (the predetermined unit number ?1) bits that is written in the other memory devices with the bits being inverted in a case where the data of one bit written in the inversion flag device is a first value representing any one of “0” and “1” and directly reads out the data of (the predetermined unit number ?1) bits that is written in the other memory devices in a case where the data of one bit written in the inversion flag device is a second value other than the first value.

Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.

Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

Abstract: The invention relates to a writable magnetic element comprising a stack of layers presenting a write magnetic layer, wherein the stack has a central layer of at least one magnetic material presenting a direction of magnetization that is parallel or perpendicular to the plane of the central layer, said central layer being sandwiched between first and second outer layers of non-magnetic materials, the first outer layer comprising a first non-magnetic material and the second outer layer comprising a second non-magnetic material that is different from the first non-magnetic material, at least the second non-magnetic material being electrically conductive, wherein it includes a device for causing current to flow through the second outer layer and the central layer in a current flow direction parallel to the plane of the central layer, and a device for applying a magnetic field having a component along a magnetic field direction that is either parallel or perpendicular to the plane of the central layer and the curr

Abstract: One embodiment of a magnetic random access memory includes a transistor formed on a substrate and having a gate width, a plurality of magnetoresistive elements disposed above the transistor and jointly electrically coupled to the transistor at their first terminals, a plurality of parallel conductive lines formed above magnetoresistive elements and independently electrically coupled to their second terminals. A magnetoresistive element includes, a pinned layer having a fixed magnetization direction, a free layer having a reversible magnetization direction, a tunnel barrier layer disposed between the free and pinned layers, and an element width that is substantially smaller than the gate width. The magnetization directions of the pinned and free layers are directed substantially perpendicular to the substrate. The magnetization direction of the free layer is reversed by a joint effect of a bias magnetic field and a spin-polarized current applied to the magnetoresistive element.

Abstract: In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer.

Abstract: Perpendicular magnetic tunnel junction (MTJ) devices, methods of fabricating a perpendicular MTJ device, electronic devices including a perpendicular MTJ device and methods of fabricating the electronic device are provided, the perpendicular MTJ devices include a pinned layer, a tunneling layer and a free layer. At least one of the pinned layer and the free layer includes a multi-layered structure including an amorphous perpendicular magnetic anisotropy (PMA) material.

Abstract: A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines.

Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have either in-plane or perpendicular anisotropy.

Abstract: A magnetic memory device may include a tunnel barrier, a reference layer on a first side of the tunnel barrier, and a free layer on a second side of the tunnel barrier so that the tunnel barrier is between the reference and free layers. The free layer may include a first magnetic layer adjacent the tunnel barrier, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer. More particularly, the nonmagnetic layer may be between the first and second magnetic layers, and the first magnetic layer may be between the tunnel barrier and the second magnetic layer. A product of a saturated magnetization of the first magnetic layer and a thickness of the first magnetic layer may be less than a product of a saturated magnetization of the second magnetic layer and a thickness of the second magnetic layer. Related methods are also discussed.

Abstract: A memory is provided that is capable of improving the thermal stability without increasing the write current. The memory is configured to include: a storage element which has a storage layer that holds information according to a magnetization state of a magnetic substance and in which a magnetization fixed layer is provided on the storage layer with an intermediate layer 16 interposed therebetween, the intermediate layer is formed of an insulator, the direction of magnetization of the storage layer is changed by injecting electrons spin-polarized in a lamination direction such that the information is recorded in the storage layer, and distortion is applied to the storage layer from an insulating layer which exists around the storage layer and has a smaller coefficient of thermal expansion than the storage layer. A wiring line for supplying a current flowing in the lamination direction of the storage element.

Abstract: By inserting a spin polarizing layer (typically pure iron) within the free layer of a MTJ or GMR memory cell, dR/R can be improved without significantly affecting other free layer properties such as Hc. Additional performance improvements can be achieved by also inserting a surfactant layer (typically oxygen) within the free layer.

Abstract: A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers, a selection transistor electrically connected to a word line, and a bit line intersecting the word line. The magnetic tunnel junction element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.

Abstract: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals.

Abstract: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer.

Abstract: The inventive ferromagnetic semiconductor comprises at least one magnetic element selected from the group consisting of Mn, Fe, Co, Ni and Cr, and has a Curie temperature which is equal to or higher than 350 K, and advantageously 400 K or higher. The semiconductor has a matrix which is depleted in magnetic element(s) and contains a discontinuous phase which is formed from columns, enriched with magnetic elements, and is ferromagnetic up to said Curie temperature, in such a way as to generate a lateral modulation of the composition of the semiconductor in the plane of the thin layer. Also disclosed is a method for the production of the semiconductor, a diode-type electronic component for the injection or collection of spins into or from another semiconductor respectively, or an electronic component which is sensitive to a magnetic field, and uses of the semiconductor relating to such a component.

Abstract: A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a second ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a nonmagnetic layer placed between the first ferromagnetic layer and the second ferromagnetic layer; a first interfacial magnetic layer placed between the first ferromagnetic layer and the nonmagnetic layer; and a second interfacial magnetic layer placed between the second ferromagnetic layer and the nonmagnetic layer. The first interfacial magnetic layer includes a first interfacial magnetic film, a second interfacial magnetic film placed between the first interfacial magnetic film and the nonmagnetic layer and having a different composition from that of the first interfacial magnetic film, and a first nonmagnetic film placed between the first interfacial magnetic film and the second interfacial magnetic film.

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract: In a method for measurement of very small local magnetic fields, in particular of local magnetic stray fields produced by magnetic beads, at least one magnetoresistive element is used. The element includes a hard-magnetic reference layer and a soft-magnetic sensor layer, whose magnetization can be rotated to a parallel position or an antiparallel position with respect to the reference layer magnetization, and whose output signal which can be tapped off is dependent on the position of the sensor layer magnetization with respect to the reference layer magnetization.

Abstract: An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a magnetic tunnel junction (MTJ) has a ferromagnetic free layer with multiple magnetic domains that are each independently programmable to predetermined magnetizations. Those magnetizations can then be read as different logical states of the MTJ.

Abstract: A spin high-frequency mixer includes a spin current generator generating a spin current upon input of a local oscillator signal, a TMR device which inputs a high-frequency signal and the spin current and generates a mixed signal, and an output device outputting the generated mixed signal from the TMR device.

Abstract: A spin injection device and spin transistor including a spin injection device. A spin injection device includes different semiconductor materials and a spin-polarizing ferromagnetic material there between. The semiconductor materials may have different crystalline structures, e.g., a first material can be polycrystalline or amorphous silicon, and a second material can be single crystalline silicon. Charge carriers are spin-polarized when the traverse the spin-polarizing ferromagnetic material and injected into the second semiconductor material. A Schottky barrier height between the first semiconductor and ferromagnetic materials is larger than a second Schottky barrier height between the ferromagnetic and second semiconductor materials. A spin injection device may be a source of a spin field effect transistor.

Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.

Abstract: Techniques and device designs associated with devices having magnetically shielded magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves that are configured to operate based on spin-transfer torque switching.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a variable magnetization and an easy-axis in a perpendicular direction to a film surface, a second magnetic layer with an invariable magnetization and an easy-axis in the perpendicular direction, and a first nonmagnetic layer between the first and second magnetic layers. The first magnetic layer comprises a ferromagnetic material including an alloy in which Co and Pd, or Co and Pt are alternately laminated on an atomically close-packed plane thereof. The first magnetic layer has C-axis directing the perpendicular direction. And a magnetization direction of the first magnetic layer is changed by a current flowing through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer.

Abstract: An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed.

Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

Abstract: A memory device includes: a memory layer that retains information based on a magnetization state of a magnetic material, a first intermediate layer and a second intermediate layer that are provided to sandwich the memory layer and are each formed of an insulator, a first fixed magnetic layer disposed on an opposite side of the first intermediate layer from the memory layer, a second fixed magnetic layer disposed on an opposite side of the second intermediate layer from the memory layer, and a nonmagnetic conductive layer provided between either the first intermediate layer or the second intermediate layer and the memory layer, the memory device being configured so that spin-polarized electrons are injected thereinto in a stacking direction to change the magnetization direction of the memory layer, thereby storing information in the memory layer.

Abstract: According to one embodiment, a semiconductor memory device includes bit line pairs extending in a column direction, each of the bit line pairs includes a first bit line and a second bit line, and memory cell groups connected to the bit line pairs, respectively, and each includes memory cells. Each of the memory cells comprises a first transistor, a second transistor and a resistive memory element. One end of the resistive memory element is connected to the first bit line. A drain region of the first transistor and a drain region of the second transistor are connected to each other and connected to the other end of the resistive memory element. A source region of the first transistor and a source region of the second transistor are connected to the second bit line.

Abstract: A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.

Abstract: An integrated circuit memory device may include an integrated circuit substrate, and a multi-bit memory cell on the integrated circuit substrate. The multi-bit memory cell may be configured to store a first bit of data by changing a first characteristic of the multi-bit memory cell and to store a second bit of data by changing a second characteristic of the multi-bit memory cell. Moreover, the first and second characteristics may be different. Related methods are also discussed.

Abstract: A recording method for a magnetic memory device that includes applying, when recording one piece of information, one or more main pulses and one or more sub-pulses in the same direction and applying the one or more sub-pulses after the one or more main pulses, the one or more main pulses each being a pulse that has a sufficient pulse height and pulse width to record information, the one or more sub-pulses each being a pulse that satisfies at least one of conditions that a pulse width is shorter than that of the one or more main pulses and that a pulse height is smaller than that of the one or more main pulses.

Abstract: An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization fixed layer, a first magnetization free layer, a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization free layer, a second magnetization fixed layer, a second magnetization free layer and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the second magnetization free layer. The first magnetization fixed layer and the first magnetization free layer have perpendicular magnetic anisotropy, and the second magnetization fixed layer and the second magnetization free layer have in-plane magnetic anisotropy. The first magnetization free layer and the second magnetization free layer are magnetically coupled to each other.

Abstract: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a variable magnetization and an easy-axis in a perpendicular direction to a film surface, a second magnetic layer with an invariable magnetization and an easy-axis in the perpendicular direction, and a first nonmagnetic layer between the first and second magnetic layers. The first magnetic layer comprises a ferromagnetic material including an alloy in which Co and Pd, or Co and Pt are alternately laminated on an atomically close-packed plane thereof. The first magnetic layer has C-axis directing the perpendicular direction. And a magnetization direction of the first magnetic layer is changed by a current flowing through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer.

Abstract: In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer.

Abstract: A spin injection device and spin transistor including a spin injection device. A spin injection device includes different semiconductor materials and a spin-polarizing ferromagnetic material there between. The semiconductor materials may have different crystalline structures, e.g., a first material can be polycrystalline or amorphous silicon, and a second material can be single crystalline silicon. Charge carriers are spin-polarized when the traverse the spin-polarizing ferromagnetic material and injected into the second semiconductor material. A Schottky barrier height between the first semiconductor and ferromagnetic materials is larger than a second Schottky barrier height between the ferromagnetic and second semiconductor materials. A spin injection device may be a source of a spin field effect transistor.

Abstract: A magnetoresistive element includes a first reference layer having magnetic anisotropy perpendicular to a film surface, and an invariable magnetization, a recording layer having a stacked structure formed by alternately stacking magnetic layers and nonmagnetic layers, magnetic anisotropy perpendicular to a film surface, and a variable magnetization, and an intermediate layer provided between the first reference layer and the recording layer, and containing a nonmagnetic material. The magnetic layers include a first magnetic layer being in contact with the intermediate layer and a second magnetic layer being not in contact with the intermediate layer. The first magnetic layer contains an alloy containing cobalt (Co) and iron (Fe), and has a film thickness larger than that of the second magnetic layer.

Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.

Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.

Abstract: In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer.

Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.

Abstract: A memory includes: a plurality of memory devices, each including a tunnel magnetic resistance effect device containing a magnetization free layer in which a direction of magnetization can be reversed, a tunnel barrier layer including an insulating material, and a magnetization fixed layer provided with respect to the magnetization free layer via the tunnel barrier layer with a fixed direction of magnetization; a random access memory area in which information is recorded using the direction of magnetization of the magnetization free layer of the memory device; and a read only memory area in which information is recorded depending on whether there is breakdown of the tunnel barrier layer of the memory device or not.

Abstract: In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path.

Abstract: A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.

Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.