Spintronics Or Quantum Computing Patents (Class 977/933)
  • Patent number: 9030866
    Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: May 12, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai
  • Patent number: 9025363
    Abstract: A memory device includes: a memory including a first magnetic layer having no retaining force and a second magnetic layer having a retaining force, the first magnetic layer and the second magnetic layer being stacked; a first magnet to magnetize the first magnetic layer in a first direction; and a second magnet to apply a magnetic field to a region through which the memory passes when the memory is removed and to magnetize the second magnetic layer in a second direction.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: May 5, 2015
    Assignee: Fujitsu Limited
    Inventor: Junichi Sato
  • Patent number: 9025371
    Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 5, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Roger K. Malmhall
  • Patent number: 9007820
    Abstract: A device comprising: an assembly consisting of two, respectively upper and lower thin layers each forming a ferromagnetic element and separated by a thin layer forming a non magnetic element, said assembly being made up so that the layers forming the ferromagnetic elements are magnetically coupled through the layer forming a non magnetic element; an electrode, a layer forming a ferroelectric element in which the polarization may be oriented in several directions by applying an electric voltage through said layer, said layer forming a ferroelectric element being positioned between the layer forming a lower ferromagnetic element and the electrode; said device being configured so as to allow control of the magnetic configuration of the layers forming ferromagnetic elements by the direction of the polarization in the layer forming a ferroelectric element.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: April 14, 2015
    Assignees: Thales, Centre National de la Recherche Scientifique (C.N.R.S)
    Inventor: Manuel Bibes
  • Patent number: 9007088
    Abstract: Preservation of quantum entanglement in a two-qubit system is achieved by use of the disclosed systems. Three different example two-qubit systems are shown: (1) a system employing a weak measurement, (2) a system in which a generalized amplitude dampening occurs without use of a weak measurement, and (3) an extended system in which the system is prepared in a more robust state less susceptible to decoherence prior to a generalized amplitude dampening.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: April 14, 2015
    Assignees: Texas A&M University System, King Abdulaziz City for Science and Technology
    Inventors: Zeyang Liao, M. Al-Amri, M. Suhail Zubiary
  • Patent number: 9001574
    Abstract: A spin logic device which includes an electron confinement layer confining an electron gas in a two-dimensional area (2DEG) subtended by a direction x and a direction y, the latter perpendicular to the former. The spin logic device is configured for the 2DEG to support a persistent spin helix (PSH) formed therein with a given spin component oscillating with periodicity ? along direction x but not oscillating along direction y. Majority logic circuit of the spin logic device includes: at least one input device energizable to create respective local spin-polarizations of the 2DEG in first regions of the confinement layer. The input device is configured to detect in a second region of the confinement layer an average spin-polarization of the 2DEG diffused through resulting PSHs, wherein a projection of a distance between the second region and first regions onto direction x is equal to n?/a, n integer, a equal to 2 or 4.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Andreas Fuhrer, Gian R Salis
  • Patent number: 8988934
    Abstract: A multi-bit cell of magnetic random access memory comprises a magnetoresistive element including first and second free layers, each free layer comprising a reversible magnetization direction directed substantially perpendicular to a layer plane in its equilibrium state and a switching current, first and second tunnel barrier layers, and a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers; a selection transistor electrically connected to a word line, and a bit line intersecting the word line; the magnetoresistive element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: March 24, 2015
    Inventor: Alexander Mikhailovich Shukh
  • Patent number: 8982616
    Abstract: A perpendicular spin transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 17, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall, Yiming Huai
  • Patent number: 8982600
    Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiho Nakamura, Tsuyoshi Kondo, Hirofumi Morise, Takuya Shimada
  • Patent number: 8982611
    Abstract: A magnetic memory element includes a first magnetic layer, a second magnetic layer, a first intermediate layer, a first magnetic wire, a first input unit, and a first detection unit. The first magnetic layer has magnetization fixed. The second magnetic layer has magnetization which is variable. The first intermediate layer is between the first magnetic layer and the second magnetic layer. The first magnetic wire extends in a first direction perpendicular to a direction connecting from the first magnetic layer to the second magnetic layer and is adjacent to the second magnetic layer. In addition, write-in is performed by propagating a first spin wave through the first magnetic wire and by passing a first current from the first magnetic layer toward the second magnetic layer. Read-out is performed by passing a second current from the first magnetic layer toward the second magnetic layer.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura, Junichi Akiyama
  • Patent number: 8983303
    Abstract: A method and system for transferring data comprising: an entangled photon source for producing first and second entangled photons associated with a receiver and a sender, respectively; a Bell state measurement device for performing a joint Bell state measurement on the second entangled photon and the at least one qubit; the Bell state measurement device outputting two bits of data to be used at the receiver; a transmission channel for transmitting two bits from the outcome of the Bell state measurement device to the receiver; a unitary transformation device for performing a unitary transformation operation on the first entangled photon based upon the value of the two bits of data; at least one detector for detecting encoded information from the first entangled photon; at least one processor operating to determine whether or not to transmit portions of data from a sequential successive qubit based upon the preceding qubit.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 17, 2015
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Ronald E Meyers, Keith S Deacon
  • Patent number: 8976577
    Abstract: One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: March 10, 2015
    Inventors: Tom A. Agan, Alexander Mikhailovich Shukh
  • Patent number: 8976578
    Abstract: A memory element has a layered configuration, including a memory layer in which a magnetization direction is changed corresponding to information; the magnetization direction being changed by applying a current in a lamination direction of the layered configuration to record the information in the memory layer, a magnetization-fixed layer in which a magnetization direction is fixed, an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, and a perpendicular magnetic anisotropy inducing layer, the memory layer including a first ferromagnetic layer, a first bonding layer, a second ferromagnetic layer, a second bonding layer and a third ferromagnetic layer laminated in the stated order.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Publication number: 20150060771
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed thereform.
    Type: Application
    Filed: July 31, 2014
    Publication date: March 5, 2015
    Applicants: The Governors of the University of Alberta, National Research Council of Canada
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 8971101
    Abstract: A semiconductor device includes a memory cell. The cell includes: a magnetic recording layer (MRL) formed of ferromagnetic material; first and second magnetization fixed layers (MFLs) coupled to the MRL; first and second reference layers (RLs) opposed to the MRL; and first and second tunnel barrier films (TBFs) inserted between the MRL and the first and second reference layers (RLs), respectively. The first MFL has a magnetization fixed in a first direction, and the second MFL has a magnetization fixed in a second direction opposite to the first direction. The first and second RLs and the first and second TBFs are positioned between the first and second MFLs. The first RL has a magnetization fixed in a third direction which is selected from the first and second directions, and the second RL has a magnetization fixed in a fourth direction opposite to the third direction.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Masaru Matsui
  • Patent number: 8971103
    Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Philip L. Trouilloud, Daniel Worledge
  • Patent number: 8971100
    Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai
  • Patent number: 8947919
    Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 3, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Patent number: 8947917
    Abstract: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Worledge, Guohan Hu
  • Patent number: 8947915
    Abstract: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Worledge, Guohan Hu
  • Patent number: 8947921
    Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 3, 2015
    Assignee: Crocus Technology SA
    Inventor: Bertrand Cambou
  • Patent number: 8947914
    Abstract: Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Heon Park, Woo Chang Lim, Sechung Oh, Woojin Kim, Sang Hwan Park, Jang Eun Lee
  • Publication number: 20150029569
    Abstract: An apparatus providing an integrated waveguide device that creates entanglement between a symmetrical sequence of periodically spaced (in time) photons in a single input and output mode. The invention comprises a polarization maintaining integrated waveguide chip containing a number of delay lines, integrated multimode interferometers with the potential for rapid switching, a polarization controller and off chip computer logic and timing.
    Type: Application
    Filed: September 10, 2013
    Publication date: January 29, 2015
    Inventors: AMOS M. SMITH, MICHAEL L. FANTO
  • Publication number: 20150029568
    Abstract: An apparatus providing an integrated waveguide device that creates entanglement between a sequence of periodically spaced (in time) photons in a single input and output mode. The invention comprises a polarization maintaining integrated waveguide chip containing a number of delay lines, integrated multimode interferometers with the potential for rapid switching, a polarization controller and off chip computer logic and timing.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 29, 2015
    Inventors: AMOS M. SMITH, MICHAEL L. FANTO
  • Patent number: 8934288
    Abstract: Magnetic memory devices are provided, the devices include at least memory cell and a reference cell on a substrate. The memory cells include a first base magnetic layer, a free layer, and a first tunnel barrier layer between the first base magnetic layer and free layer. The reference memory cell includes a second base magnetic layer, a reference magnetic layer, and a second tunnel barrier layer between the second base magnetic layer and reference magnetic layer. The reference magnetic layer has a magnetic direction substantially perpendicular to that of the free layer.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sechung Oh, Hyungrok Oh
  • Patent number: 8923037
    Abstract: A memory element including a memory layer to hold the information by the magnetization state of a magnetic substance, a magnetization pinned layer having magnetization serving as a reference of the information stored in the memory layer, an intermediate layer formed from a nonmagnetic substance disposed between the memory layer and the magnetization pinned layer, a magnetic coupling layer disposed adjoining the magnetization pinned layer and opposing to the intermediate layer, and a high coercive force layer disposed adjoining the magnetic coupling layer, wherein the information is stored by reversing magnetization of the memory layer, making use of spin torque magnetization reversal generated along with a current passing in the lamination direction of the layered structure including the memory layer, the intermediate layer, and the magnetization pinned layer, and the magnetic coupling layer has a two-layer laminate structure.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: December 30, 2014
    Assignee: Sony Corporation
    Inventors: Hiroyuki Ohmori, Masanori Hosomi, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida, Tetsuya Asayama
  • Patent number: 8917543
    Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: December 23, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20140368234
    Abstract: A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Jerry M. Chow, Jay M. Gambetta, Seth T. Merkel, Chad T. Rigetti, Matthias Steffen
  • Patent number: 8908423
    Abstract: A magnetoresistive effect element includes: a magnetization free layer having an invertible magnetization; an insulating layer being adjacent to the magnetization free layer; and a magnetization fixed layer being adjacent to the insulation layer and in an opposite side of the insulation layer to the magnetization free layer. The magnetization free layer includes: a first magnetization free layer being adjacent to the insulating layer and comprising Fe or Co; and a second magnetization free layer being adjacent to the first magnetization layer and comprising NiFeB.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: December 9, 2014
    Assignee: NEC Corporation
    Inventor: Hiroaki Honjou
  • Patent number: 8908425
    Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Philip L. Trouilloud, Daniel Worledge
  • Patent number: 8903094
    Abstract: The invention concerns a cryptographic key distribution system comprising a server node, a repeater network connected to the server node through a quantum channel, and a client node connected to the repeater network through a quantum channel; wherein in use: the repeater network and the client node cooperatively generate a transfer quantum key which is supplied to a system subscriber by the client node; the server node and the repeater network cooperatively generate a link quantum key; the repeater network encrypts the link quantum key based on the transfer quantum key and sends the encrypted link quantum key to the system subscriber through a public communication channel; the server node encrypts a traffic cryptographic key based on the link quantum key and a service authentication key and sends the encrypted traffic cryptographic key to the system subscriber through a public communication channel.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: December 2, 2014
    Assignee: Selex Sistemi Integrati S.p.A.
    Inventor: Fabio Antonio Bovino
  • Patent number: 8891291
    Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Zihui Wang, Yiming Huai
  • Patent number: 8885395
    Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: November 11, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Zihui Wang, Yiming Huai, Rajiv Yadav Ranjan, Roger K. Malmhall
  • Patent number: 8885396
    Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaya Yamanaka, Susumu Shuto
  • Patent number: 8879306
    Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 4, 2014
    Assignee: III Holdings 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 8860159
    Abstract: A spintronic electronic apparatus having a multilayer structure. The apparatus includes a substrate, having disposed in succession upon the substrate; a bottom interface layer; a pinned layer; a tunneling barrier; a free layer; and a top interface layer, wherein the apparatus operates as a non-resonant magnetic tunnel junction in a large amplitude, out-of-plane magnetization precession regime having weakly current dependent, large diode volt-watt sensitivity when external microwave signals that exceed a predetermined threshold current and have a frequency that is lower than a predetermined level excite the magnetization precession.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 14, 2014
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Thomas J. Meitzler, Elena N. Bankowski, Michael Nranian, Ilya N. Krivorotov, Andrei N. Slavin, Vasyl S. Tyberkevych
  • Publication number: 20140266406
    Abstract: A method and system to control crosstalk among qubits on a chip are described. The method includes placing two or more components symmetrically on the chip, the chip including the qubits, and driving two or more ports symmetrically to control the crosstalk based on controlling coupling of chip mode frequencies and qubit frequencies.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Patent number: 8830736
    Abstract: A method of initializing a magnetic random access memory (MRAM) element that is configured to store a state when electric current flows therethrough is disclosed. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ and each MTJ further includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ for storing reference bit.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai
  • Patent number: 8816479
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 26, 2014
    Assignees: National Research Council of Canada, The Governors of The University of Alberta
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 8811073
    Abstract: A magnetic device includes a reference layer, the magnetization direction of which is fixed, and a storage layer, the magnetization direction of which is variable. In a write mode, the magnetization direction of the storage layer is changed so as to store a “1” or a “0” in the storage layer. In a reading mode, the resistance of the magnetic device is measured so as to know what is stored in the storage layer. The magnetic device also includes a control layer, the magnetization direction of which is variable. The magnetization direction of the control layer is controlled so as to increase the effectiveness of the spin-transfer torque in the event writing to the storage layer is desired, and to decrease the effectiveness of the spin-transfer torque in the event reading the information contained in the storage layer, without modifying the information, is desired.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 19, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Bernard Dieny
  • Patent number: 8797621
    Abstract: Disclosed herein are atom phase-controlled double rephasing-based quantum memory and a double-rephased photon echo method therefor. The atom phase-controlled double rephasing-based quantum memory includes an optical medium and an optical pulse generation unit. The optical medium has three energy levels (|1>, |2> and |3>), receives one or more optical pulses from an optical pulse generation unit, and generates output light that satisfies phase matching conditions. The optical pulse generation unit generates at least five optical pulses that resonate among the energy levels of the optical medium.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: August 5, 2014
    Assignees: INHA Industry Partnership Institute, Gwangju Institute of Science and Technology
    Inventor: Byoung Seung Ham
  • Patent number: 8792271
    Abstract: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Morise, Hideaki Fukuzawa, Akira Kikitsu, Yoshiaki Fukuzumi
  • Patent number: 8750036
    Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 10, 2014
    Assignee: Seagate Technology, LLC
    Inventors: Xiaohua Lou, Haiwen Xi
  • Patent number: 8750035
    Abstract: There is disclosed a memory element including a memory layer that maintains information through the magnetization state of a magnetic material, a magnetization-fixed layer with a magnetization that is a reference of information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The storing of the information is performed by inverting the magnetization of the memory layer by using a spin torque magnetization inversion occurring according to a current flowing in the lamination direction of a layered structure having the memory layer, the intermediate layer, and the magnetization-fixed layer, the memory layer includes an alloy region containing at least one of Fe and Co, and a magnitude of an effective diamagnetic field which the memory layer receives during magnetization inversion thereof is smaller than the saturated magnetization amount of the memory layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: June 10, 2014
    Assignee: Sony Corporation
    Inventors: Kazuhiro Bessho, Masanori Hosomi, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8750030
    Abstract: According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to be in contact with the metal layer and has a magnetization easy axis in a direction perpendicular to a film plane and is variable in magnetization direction. The second magnetic layer is disposed on the first magnetic layer and has a magnetization easy axis in the direction perpendicular to the film plane and is invariable in magnetization direction. The nonmagnetic layer is provided between the first and second magnetic layers. The magnetization direction of the first magnetic layer is varied by a current that runs through the first magnetic layer, the nonmagnetic layer, and the second magnetic layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Ueda, Tadashi Kai, Toshihiko Nagase, Katsuya Nishiyama, Eiji Kitagawa, Tadaomi Daibou, Makoto Nagamine, Hiroaki Yoda
  • Publication number: 20140151770
    Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
  • Publication number: 20140151771
    Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.
    Type: Application
    Filed: August 13, 2013
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
  • Publication number: 20140153327
    Abstract: A spin transport channel includes a dielectric layer contacting a conductive layer. The dielectric layer includes at least one of a tantalum oxide, hafnium oxide, titanium oxide, and nickel oxide. An intermediate spin layer contacts the dielectric layer. The intermediate spin layer includes at least one of copper and silver. The conductive layer is more electrochemically inert than the intermediate spin layer. A polarizer layer contacts the intermediate spin layer. The polarizer layer includes one of a nickel-iron based material, iron, and cobalt based material. The conductive layer and intermediate layer are disposed on opposite sides of the dielectric layer. The dielectric layer and the polarizer layer are disposed on opposite sides of the intermediate spin layer. The intermediate spin layer is arranged to form a conducting path through the dielectric layer configured to transport a plurality of electrons. Each of the plurality of electrons maintains a polarized electron spin.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: The National Institute of Standards and Technology Government of the United States of America, as Re
    Inventor: The National Institute of Standards and Technology, Government of the United States of America, as R
  • Publication number: 20140151620
    Abstract: A method for fabricating a spintronic cell includes forming a cavity in a substrate, forming a wire in the cavity, depositing a spacer layer over exposed portions of the substrate and the conductive field line, depositing a layer of conductive material on a portion of the spacer layer, removing portions of the layer of conductive material to define a conductive strap portion, wherein the conductive strap portion has a first distal region a second distal region and a medial region arranged therebetween, wherein the medial region has a cross sectional area that is less than a cross sectional area of the first distal region and a cross sectional area of the second distal region, and forming an spintronic device stack on the conductive strap portion above the conductive field line.
    Type: Application
    Filed: August 6, 2013
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: David W. Abraham, Philip L. Trouilloud, Daniel C. Worledge
  • Publication number: 20140133001
    Abstract: A method and device for optimal processing of a plurality of sets of coherent states of lights. The method includes: receiving a light having a coherent state; splitting the coherent state into a plurality of identical states (slices), each a coherent state with lower intensity than that of the received coherent state; transferring the information of each of the identical coherent states into a qubit; compressing the quantum information of the qubit into a quantum memory; and quantum processing the quantum information from the quantum memory.
    Type: Application
    Filed: October 5, 2012
    Publication date: May 15, 2014
    Applicant: RAYTHEON BBN TECHNOLOGIES CORP.
    Inventor: RAYTHEON BBN TECHNOLOGIES CORP.