Abstract: A compatibility is ascertained between a configuration of a quantum processor (q-processor) of a quantum cloud compute node (QCCN) in a quantum cloud environment (QCE) and an operation requested in a first instruction in a portion (q-portion) of a job submitted to the QCE, the QCE including the QCCN and a conventional compute node (CCN), the CCN including a conventional processor configured for binary computations. In response to the ascertaining, a quantum instruction (q-instruction) is constructed corresponding to the first instruction. The q-instruction is executed using the q-processor of the QCCN to produce a quantum output signal (q-signal). The q-signal is transformed into a corresponding quantum computing result (q-result). A final result is returned to a submitting system that submitted the job, wherein the final result comprises the q-result.

Abstract: A modular quantum entanglement processing system can include a plurality of seed state systems, resource state systems, and fusion systems that can be ordered in different arrangements. The systems can be composed of modular assemblies or chips, such that the systems can be modularized and extended to perform entanglement based processing of tasks in a scalable manner. Some of the assemblies or chips of the different systems can be designed to operate at cryogenic temperatures, such as detector, while other assemblies or chips of the different systems can operate at room temperature, where the different chip types can be coupled to one another using fiber optic cables.

Abstract: A method and system are provided for comparing a first database table and a second database table with each other to produce a table of differences therebetween. The first database table and the second database table include one or more subsets of data that are intended to match each other, and the first database table and the second database table each include multiple rows. Indicia is generated for each of the multiple rows of the first database table, and each of the multiple rows of the second database table. The generated indicia for each of the multiple rows of the first database table are compared with the generated indicia for each of the multiple rows of the second database table, wherein the comparing occurs without regard to an order of the rows in either the first database table or the second database table.

Abstract: A measurement-device-independent quantum key distribution (MDI-QKD) network includes a plurality of user nodes connected to untrusted relay node that performs Bell-state measurements on qubits transmitted by the user nodes. The relay node contains a calibration laser that serves as a wavelength reference for the user nodes. The output of the calibration laser is split into two wavelength-calibration signals, which are transmitted to a pair of user nodes via optical fiber. At each user node, a laser diode used to generate weak coherent pulses is injection-locked with the wavelength calibration-signal, thereby ensuring that the user nodes generate photonic qubits with the same wavelength. The embodiments may be implemented with any encoding scheme compatible with MDI-QKD, such as polarization encoding and time-bin phase-encoding. No auxiliary connections between the user nodes are needed, allowing the MDI-QKD network to be scaled up to many users.

Abstract: In a general aspect, a method executed in a quantum computing system includes performing a calibration process in the quantum computing system to identify a value of a parameter of the quantum computing system. The method also includes analyzing a variation of the value in response to a change in a condition of the quantum computing system, thereby determining a stability of the parameter. The method additionally includes scheduling a recalibration of the parameter based on the stability of the parameter and executing a quantum algorithm in the quantum computing system based on the value of the parameter identified by the calibration process.

Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.

Abstract: Methods, apparatuses, and systems include acquiring initial environmental information corresponding to a superconducting qubit received from a superconducting circuit, the superconducting circuit being in an environment; determining first environmental information corresponding to the superconducting qubit in response to a quantum energy level of the superconducting qubit being a first preset energy level; determining second environmental information corresponding to the superconducting qubit in response to the quantum energy level of the superconducting qubit being a second preset energy level; determining effective environmental information based on the first environmental information and the second environmental information; and determining arbitrary-order correlation information for identifying an environmental noise based on the effective environmental information and the initial environmental information.

Abstract: Techniques for automating quantum circuit debugging are provided that simulate standard debugging behaviors. The technology includes rewriting a source quantum circuit into instrumented circuits based on instrumentation instruction information inserted into software code that corresponds to the source quantum circuit. The instrumented circuits can executed to obtain measurement data corresponding to different state data of qubits within the source quantum circuit. The measurement data can be processed to output generated information corresponding to one or more internal states or processes of a quantum computer associated with the source quantum circuit.

Abstract: A top-down distillation process for preparing low-error rate Toffoli gates utilizes Toffoli magic states as inputs to the distillation process. Multiple Toffoli magic states are used to distill a low-error rate Toffoli gate via one round of distillation. Lattice surgery operations are performed to distill the low-error rate Toffoli gate from the multiple Toffoli magic states. Each round of lattice surgery operations acts on a check qubit associated with the low error rate Toffoli gate being distilled. Errors introduced during the distillation (if non-trivial) will be manifest in the check qubit. Thus, the check qubit is measured subsequent to performing the lattice surgery operations to verify that the distilled Toffoli gate is very likely to be provide a correct result.

Abstract: A closed-loop feedback system and method of active noise cancellation to maintain a desired operating frequency of a qubit during a quantum computation, even when that frequency is relatively sensitive to flux noise. A series of Ramsey experiments is performed on the qubit to estimate an offset between its actual and desired operating frequencies, and the error is accumulated. After the probing is complete, the accumulated error is supplied to an arbitrary waveform generator that produces a magnetic flux that is coupled to the qubit, thereby tuning the qubit and actively controlling its operating frequency. Having corrected the operating frequency of the qubit and extended its coherence time, the quantum state of the qubit is allowed to evolve according to the computation.

Abstract: A controlled quantum logic gate implements a n?1 qubit controlled Z gate function based on n qubits and an ancilla qubit, wherein n is greater than 3. The quantum logic gate includes a plurality of leading gates that operate on the at least one ancilla qubit to generate an ancilla qubit state in response to an initial state of the ancilla bit and each of the n qubits. A measurement operates on the ancilla qubit state to generate a classical ancilla bit state. At least one following gate includes at least one controlled Z gate equivalent that operates under control of at least one of the n qubits and further under control of the classical ancilla bit state to selectively apply a phase adjustment to at least another one of the n qubits.

Abstract: Methods and apparatus for automatic qubit calibration. In one aspect, a method includes obtaining a plurality of qubit parameters and data describing dependencies of the plurality of qubit parameters on one or more other qubit parameters; identifying a qubit parameter; selecting a set of qubit parameters that includes the identified qubit parameter and one or more dependent qubit parameters; processing one or more parameters in the set of qubit parameters in sequence according to the data describing dependencies, comprising, for a parameter in the set of qubit parameters: performing a calibration test on the parameter; and performing a first calibration experiment or a diagnostic calibration algorithm on the parameter when the calibration test fails.

Abstract: Methods, systems and apparatus for producing quantum circuits with low T gate counts. In one aspect, a method for performing a temporary logical AND operation on two control qubits includes the actions of obtaining an ancilla qubit in an A-state; computing a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, comprising replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits; maintaining the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied; and erasing the ancilla qubit when the first condition is satisfied.

Abstract: Topologies for analog computing systems may include cells of qubits which may implement a tripartite graph and cross substantially orthogonally. Qubits may have an H-shape or an l-shape, qubits may change direction within a cell. Topologies may be comprised of two or more different sub-topologies. Qubits may be communicatively coupled to non-adjacent cells by long-range couplers. Long-range couplers may change direction within a cell. A cell may have two or more different type of long-range couplers. A cell may have shifted qubits, more than one type of inter-cell couplers, more than one type of intra-cell couplers and long-range couplers.

Abstract: One example includes a tunable current-mirror qubit. The qubit includes a plurality of flux tunable elements disposed in a circuit loop. A first portion of the flux tunable elements can be configured to receive a first input flux and a remaining portion of the flux tunable elements can be configured to receive a second input flux to control a mode of the tunable current-mirror qubit between a microwave excitation mode to facilitate excitation or quantum state manipulation of the tunable current-mirror qubit via a microwave input signal and a noise-protected mode to facilitate storage of the quantum state of the tunable current-mirror qubit. The qubit also includes at least one capacitor interconnecting nodes between respective pairs of the flux tunable elements to facilitate formation of Cooper-pair excitons in each of the microwave excitation mode and the noise-protected mode.

Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: A memory device includes: a memory including a first magnetic layer having no retaining force and a second magnetic layer having a retaining force, the first magnetic layer and the second magnetic layer being stacked; a first magnet to magnetize the first magnetic layer in a first direction; and a second magnet to apply a magnetic field to a region through which the memory passes when the memory is removed and to magnetize the second magnetic layer in a second direction.

Abstract: A device comprising: an assembly consisting of two, respectively upper and lower thin layers each forming a ferromagnetic element and separated by a thin layer forming a non magnetic element, said assembly being made up so that the layers forming the ferromagnetic elements are magnetically coupled through the layer forming a non magnetic element; an electrode, a layer forming a ferroelectric element in which the polarization may be oriented in several directions by applying an electric voltage through said layer, said layer forming a ferroelectric element being positioned between the layer forming a lower ferromagnetic element and the electrode; said device being configured so as to allow control of the magnetic configuration of the layers forming ferromagnetic elements by the direction of the polarization in the layer forming a ferroelectric element.

Abstract: Preservation of quantum entanglement in a two-qubit system is achieved by use of the disclosed systems. Three different example two-qubit systems are shown: (1) a system employing a weak measurement, (2) a system in which a generalized amplitude dampening occurs without use of a weak measurement, and (3) an extended system in which the system is prepared in a more robust state less susceptible to decoherence prior to a generalized amplitude dampening.

Abstract: A spin logic device which includes an electron confinement layer confining an electron gas in a two-dimensional area (2DEG) subtended by a direction x and a direction y, the latter perpendicular to the former. The spin logic device is configured for the 2DEG to support a persistent spin helix (PSH) formed therein with a given spin component oscillating with periodicity ? along direction x but not oscillating along direction y. Majority logic circuit of the spin logic device includes: at least one input device energizable to create respective local spin-polarizations of the 2DEG in first regions of the confinement layer. The input device is configured to detect in a second region of the confinement layer an average spin-polarization of the 2DEG diffused through resulting PSHs, wherein a projection of a distance between the second region and first regions onto direction x is equal to n?/a, n integer, a equal to 2 or 4.

Abstract: A multi-bit cell of magnetic random access memory comprises a magnetoresistive element including first and second free layers, each free layer comprising a reversible magnetization direction directed substantially perpendicular to a layer plane in its equilibrium state and a switching current, first and second tunnel barrier layers, and a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers; a selection transistor electrically connected to a word line, and a bit line intersecting the word line; the magnetoresistive element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.

Abstract: A method and system for transferring data comprising: an entangled photon source for producing first and second entangled photons associated with a receiver and a sender, respectively; a Bell state measurement device for performing a joint Bell state measurement on the second entangled photon and the at least one qubit; the Bell state measurement device outputting two bits of data to be used at the receiver; a transmission channel for transmitting two bits from the outcome of the Bell state measurement device to the receiver; a unitary transformation device for performing a unitary transformation operation on the first entangled photon based upon the value of the two bits of data; at least one detector for detecting encoded information from the first entangled photon; at least one processor operating to determine whether or not to transmit portions of data from a sequential successive qubit based upon the preceding qubit.

Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.

Abstract: A perpendicular spin transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: A magnetic memory element includes a first magnetic layer, a second magnetic layer, a first intermediate layer, a first magnetic wire, a first input unit, and a first detection unit. The first magnetic layer has magnetization fixed. The second magnetic layer has magnetization which is variable. The first intermediate layer is between the first magnetic layer and the second magnetic layer. The first magnetic wire extends in a first direction perpendicular to a direction connecting from the first magnetic layer to the second magnetic layer and is adjacent to the second magnetic layer. In addition, write-in is performed by propagating a first spin wave through the first magnetic wire and by passing a first current from the first magnetic layer toward the second magnetic layer. Read-out is performed by passing a second current from the first magnetic layer toward the second magnetic layer.

Abstract: A memory element has a layered configuration, including a memory layer in which a magnetization direction is changed corresponding to information; the magnetization direction being changed by applying a current in a lamination direction of the layered configuration to record the information in the memory layer, a magnetization-fixed layer in which a magnetization direction is fixed, an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, and a perpendicular magnetic anisotropy inducing layer, the memory layer including a first ferromagnetic layer, a first bonding layer, a second ferromagnetic layer, a second bonding layer and a third ferromagnetic layer laminated in the stated order.

Abstract: One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.

Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed thereform.

Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

Abstract: A semiconductor device includes a memory cell. The cell includes: a magnetic recording layer (MRL) formed of ferromagnetic material; first and second magnetization fixed layers (MFLs) coupled to the MRL; first and second reference layers (RLs) opposed to the MRL; and first and second tunnel barrier films (TBFs) inserted between the MRL and the first and second reference layers (RLs), respectively. The first MFL has a magnetization fixed in a first direction, and the second MFL has a magnetization fixed in a second direction opposite to the first direction. The first and second RLs and the first and second TBFs are positioned between the first and second MFLs. The first RL has a magnetization fixed in a third direction which is selected from the first and second directions, and the second RL has a magnetization fixed in a fourth direction opposite to the third direction.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.

Abstract: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction.

Abstract: Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer.

Abstract: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction.

Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.

Abstract: An apparatus providing an integrated waveguide device that creates entanglement between a sequence of periodically spaced (in time) photons in a single input and output mode. The invention comprises a polarization maintaining integrated waveguide chip containing a number of delay lines, integrated multimode interferometers with the potential for rapid switching, a polarization controller and off chip computer logic and timing.

Abstract: An apparatus providing an integrated waveguide device that creates entanglement between a symmetrical sequence of periodically spaced (in time) photons in a single input and output mode. The invention comprises a polarization maintaining integrated waveguide chip containing a number of delay lines, integrated multimode interferometers with the potential for rapid switching, a polarization controller and off chip computer logic and timing.

Abstract: Magnetic memory devices are provided, the devices include at least memory cell and a reference cell on a substrate. The memory cells include a first base magnetic layer, a free layer, and a first tunnel barrier layer between the first base magnetic layer and free layer. The reference memory cell includes a second base magnetic layer, a reference magnetic layer, and a second tunnel barrier layer between the second base magnetic layer and reference magnetic layer. The reference magnetic layer has a magnetic direction substantially perpendicular to that of the free layer.

Abstract: A memory element including a memory layer to hold the information by the magnetization state of a magnetic substance, a magnetization pinned layer having magnetization serving as a reference of the information stored in the memory layer, an intermediate layer formed from a nonmagnetic substance disposed between the memory layer and the magnetization pinned layer, a magnetic coupling layer disposed adjoining the magnetization pinned layer and opposing to the intermediate layer, and a high coercive force layer disposed adjoining the magnetic coupling layer, wherein the information is stored by reversing magnetization of the memory layer, making use of spin torque magnetization reversal generated along with a current passing in the lamination direction of the layered structure including the memory layer, the intermediate layer, and the magnetization pinned layer, and the magnetic coupling layer has a two-layer laminate structure.

Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.

Abstract: A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction.

Abstract: A magnetoresistive effect element includes: a magnetization free layer having an invertible magnetization; an insulating layer being adjacent to the magnetization free layer; and a magnetization fixed layer being adjacent to the insulation layer and in an opposite side of the insulation layer to the magnetization free layer. The magnetization free layer includes: a first magnetization free layer being adjacent to the insulating layer and comprising Fe or Co; and a second magnetization free layer being adjacent to the first magnetization layer and comprising NiFeB.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.

Abstract: The invention concerns a cryptographic key distribution system comprising a server node, a repeater network connected to the server node through a quantum channel, and a client node connected to the repeater network through a quantum channel; wherein in use: the repeater network and the client node cooperatively generate a transfer quantum key which is supplied to a system subscriber by the client node; the server node and the repeater network cooperatively generate a link quantum key; the repeater network encrypts the link quantum key based on the transfer quantum key and sends the encrypted link quantum key to the system subscriber through a public communication channel; the server node encrypts a traffic cryptographic key based on the link quantum key and a service authentication key and sends the encrypted traffic cryptographic key to the system subscriber through a public communication channel.

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.

Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor.

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.

Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.