Field Effect Transistors (fets) With Nanowire- Or Nanotube-channel Region Patents (Class 977/938)
  • Patent number: 9040957
    Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: May 26, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae-ho Lee, Seong-jun Park, Kyung-eun Byun, David Seo, Hyun-jae Song, Hyung-cheol Shin, Jae-hong Lee, Hyun-jong Chung, Jin-seong Heo
  • Patent number: 9029936
    Abstract: A memory device includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a first charge trap including a plurality of electrically conductive nanodots located over the tunnel dielectric layer, dielectric separation layer located over the nanodots, a second charge trap including a continuous metal layer located over the separation layer, a blocking dielectric located over the second charge trap, and a control gate located over the blocking dielectric.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Purayath, George Samachisa, George Matamis, James Kai, Yuan Zhang
  • Patent number: 9030187
    Abstract: A nanogap device includes a first insulation layer having a nanopore formed therein, a first nanogap electrode which may be formed on the first insulation layer and may be divided into two parts with a nanogap interposed between the two parts, the nanogap facing the nanopore, a second insulation layer formed on the first nanogap electrode, a first graphene layer formed on the second insulation layer, a first semiconductor layer formed on the first graphene layer, a first drain electrode formed on the first semiconductor layer, and a first source electrode formed on the first graphene layer such as to be apart from the first semiconductor layer.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-seung Lee, Yong-sung Kim, Jeo-young Shim, Joo-ho Lee
  • Patent number: 9029836
    Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Jung-Ung Park, SungWoo Nam, Charles M. Lieber
  • Patent number: 9012278
    Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: April 21, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
  • Patent number: 9007732
    Abstract: Device structures and methods for providing carbon nanotube field effect transistor (CNTFET) devices with enhanced current carrying capability at lower densities are disclosed. Apparatuses and methods using CNTFET devices for providing protection from electrostatic discharge (ESD) voltages are also disclosed. According to some aspects of the present disclosure the electrostatic discharge protection circuits are configured with CNTFET diodes and provide protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit. According to some aspects of the present disclosure the methods for providing protection from electrostatic discharge voltages create conducting paths for providing protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Nantero Inc.
    Inventor: Claude L. Bertin
  • Patent number: 9006087
    Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 9000499
    Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is formed on a substrate. A portion of the substrate is removed to form a recess below a section of the carbon nanotube. A doped material is applied in the recess to fabricate the semiconducting device. The recess may be between one or more contacts formed on the substrate separated by a gap.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Aaron D. Franklin, Siyuranga O. Koswatta, Joshua T. Smith
  • Patent number: 8987707
    Abstract: Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Michael S. Arnold, Feng Xu
  • Publication number: 20150069330
    Abstract: Provided are a nanowire field-effect transistor and a method for manufacturing the same. The nanowire field-effect transistor can enable a source region to be positioned, with respect to an asymmetrical nanowire channel, adjacent to a region in which the diameter of the nanowire channel is large, can enable a drain region to be positioned adjacent to a region in which the diameter of the nanowire channel is small, can enable an ON current to be increased in a state in which a threshold voltage level is kept the same, and can enable the current drivability of a gate electrode to be improved.
    Type: Application
    Filed: March 11, 2013
    Publication date: March 12, 2015
    Inventors: ChangKi Baek, TaiUk Rim, MyungDong Ko
  • Patent number: 8969145
    Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.
    Type: Grant
    Filed: January 19, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar
  • Patent number: 8969148
    Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Maud Vinet, Sylvain Barraud, Laurent Grenouillet
  • Publication number: 20150053913
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 26, 2015
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8962408
    Abstract: A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang
  • Patent number: 8946680
    Abstract: A tunnel field effect transistor (TFET) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Isaac Lauer, Amlan Majumdar, Jeffrey Sleight
  • Patent number: 8946683
    Abstract: The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: February 3, 2015
    Assignees: The Board of Trustees of the University of Illinois, Purdue Research Foundation
    Inventors: John A. Rogers, Qing Cao, Muhammad Alam, Ninad Pimparkar
  • Patent number: 8940562
    Abstract: The present disclosure provides the ability to produce backplanes for AMLCD and AMOLED. Specifically, each and every component of the backplanes can be printed. Depending on the resolution and screen size of the displays, backplanes can include over a million different components that must be printed that include components of the thin film transistor (TFT) and electrodes to address each of those TFTs. Even a slight misregistry of components during printing can lead to failure of one or more pixels, potentially rendering the entire display unsuitable for use. The present disclosure provides the ability to reproducibly and accurately print each and every component of the backplane for both AMLCD and AMOLED. The ability to completely print backplanes provides numerous advantages, such as reduced costs, improved throughput, more environmental friendliness, and the like.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: January 27, 2015
    Assignee: Atom Nanoelectronics, Inc
    Inventor: Huaping Li
  • Patent number: 8927968
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8927405
    Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Alfred Grill, Leathen Shi
  • Patent number: 8927397
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8921825
    Abstract: A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Patent number: 8912545
    Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventors: Deyuan Xiao, James Hong
  • Patent number: 8901655
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8900935
    Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Zhengwen Li, Kejia Wang, Zhen Zhang, Yu Zhu
  • Publication number: 20140346442
    Abstract: Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 27, 2014
    Applicant: THE UNIVERSITY OF CHICAGO
    Inventors: Angshuman Nag, Dmitri V. Talapin
  • Patent number: 8895371
    Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Publication number: 20140339507
    Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.
    Type: Application
    Filed: September 16, 2013
    Publication date: November 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 8890116
    Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Zhihong Chen, Aaron Daniel Franklin, Shu-Jen Han
  • Patent number: 8890261
    Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a field effect transistor device is provided. The field effect transistor device includes a source region; a drain region; a plurality of fins connecting the source region and the drain region, the fins having a pitch of between about 40 nanometers and about 200 nanometers and each fin having a width of between about ten nanometers and about 40 nanometers; and a gate stack over at least a portion of the fins, wherein the source region and the drain region are self-aligned with the gate stack.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Wilfried Haensch, Katherine Lynn Saenger
  • Publication number: 20140332753
    Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.
    Type: Application
    Filed: September 9, 2013
    Publication date: November 13, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: DEYUAN XIAO
  • Publication number: 20140306185
    Abstract: A thin film transistor is provided. The thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The insulating layer has a first surface and a second surface opposite to the first surface. The gate electrode is located on the first surface of the insulating layer. The source electrode, the drain electrode, and the semiconductor layer are located on the second surface of the insulating layer. The gate electrode, the source electrode, and the drain electrode include a first carbon nanotube layer. The semiconductor layer includes a second carbon nanotube layer. A first film resistor of the first carbon nanotube layer is smaller than or equal to 10 k? per square. A second film resistor of the second carbon nanotube layer is greater than or equal to 100 k? per square.
    Type: Application
    Filed: December 24, 2013
    Publication date: October 16, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., Tsinghua University
    Inventors: YUAN ZOU, QUN-QING LI, SHOU-SHAN FAN
  • Publication number: 20140306175
    Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, a first conductive layer, a second conductive layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The first conductive layer is sandwiched between the source electrode and the semiconductor layer. The second conductive layer is sandwiched between the drain electrode and the semiconductor layer. The gate electrode is insulated from the source electrode, the drain electrode, the first conductive layer, the second conductive layer, and the semiconductor layer by the insulating layer. A first work-function of a first material of the first conductive layer and the second conductive layer is same as a second work-function of a second material of the semiconductor layer.
    Type: Application
    Filed: August 7, 2013
    Publication date: October 16, 2014
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., TSINGHUA UNIVERSITY
    Inventors: QING-KAI QIAN, QUN-QING LI
  • Publication number: 20140264279
    Abstract: Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zhen Zhang, Yu Zhu
  • Publication number: 20140273361
    Abstract: Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Wisconsin Alumni Research Foundation
    Inventors: Michael S. Arnold, Padma Gopalan, Nathaniel S. Safron, Myungwoong Kim, Jonathan Woosun Choi
  • Publication number: 20140268444
    Abstract: Device structures and methods for providing carbon nanotube field effect transistor (CNTFET) devices with enhanced current carrying capability at lower densities are disclosed. Apparatuses and methods using CNTFET devices for providing protection from electrostatic discharge (ESD) voltages are also disclosed. According to some aspects of the present disclosure the electrostatic discharge protection circuits are configured with CNTFET diodes and provide protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit. According to some aspects of the present disclosure the methods for providing protection from electrostatic discharge voltages create conducting paths for providing protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventor: Claude L. Bertin
  • Patent number: 8835191
    Abstract: Methods for sensing a mechanical stress and methods of making stress sensor integrated circuits. The sensing methods include transferring the mechanical stress from the object to one or more nanowires in a stress sensor or stress sensor circuit and permitting the nanowires to change in length in response to the mechanical stress. An electrical characteristic of the stress sensor or stress sensor circuit, which has a variation correlated with changes in the magnitude of the mechanical stress, is measured and then assessed to determine the stress magnitude. The manufacture methods include electrically connecting nanowire field effect transistors having, as channel regions, one or more nanowires of either a different crystalline orientation or a different body width for the individual nanowires so that an offset output voltage results when mechanical strain is applied to the nanowires.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, Oki Gunawan, Shih-Hsien Lo, Jeffrey W. Sleight
  • Patent number: 8835231
    Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • Patent number: 8816326
    Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: August 26, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Jun Luo, Chao Zhao, Honggang Liu, Dapeng Chen
  • Patent number: 8816328
    Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Publication number: 20140231820
    Abstract: A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 21, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-ho LEE, Hyun-jong CHUNG, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Jin-seong HEO
  • Patent number: 8810009
    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semiconductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 19, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Seth A. Fortuna
  • Patent number: 8809834
    Abstract: Apparatuses capable of and techniques for detecting long wavelength radiation are provided.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: August 19, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8803131
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Patent number: 8803129
    Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Publication number: 20140217507
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20140217509
    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.
    Type: Application
    Filed: August 19, 2013
    Publication date: August 7, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8796668
    Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yu-Ming Lin, Jeng-Bang Yau
  • Publication number: 20140209997
    Abstract: A thin film transistor based on carbon nanotubes includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The work-functions of the source electrode and of the drain electrode are different from that of the semiconductor layer, enabling the creation of both p-type and n-type field-effect transistors.
    Type: Application
    Filed: June 26, 2013
    Publication date: July 31, 2014
    Inventors: QING-KAI QIAN, QUN-QING LI
  • Publication number: 20140203290
    Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.
    Type: Application
    Filed: August 15, 2013
    Publication date: July 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight, Amlan Majumdar
  • Patent number: 8785309
    Abstract: A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 22, 2014
    Assignee: Nano-Electronic And Photonic Devices And Circuits, LLC
    Inventor: Alexander Kastalsky