Field Effect Transistors (fets) With Nanowire- Or Nanotube-channel Region Patents (Class 977/938)
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Patent number: 7452759Abstract: A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube transistor starts with a substrate comprised of a bottom dielectric, a carbon nanotube layer, and a top dielectric. A pillar is formed on the top dielectric, and a sidewall gate is formed on a sidewall of the pillar. A source is formed proximate to an outer edge of the gate and in contact with the carbon nanotube layer. The pillar is then removed, the source area masked, and a drain is formed proximate to an inner edge of the gate and in contact with the carbon nanotube layer. The source and drain are self aligned to the gate as dictated by the placement of dielectric spacers on the inner and outer edges of the gate.Type: GrantFiled: November 29, 2005Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventor: Gurtej Sandhu
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Patent number: 7447055Abstract: Various embodiments of the present invention are directed to electronic means for reading the content of a nanowire-crossbar memory. In one embodiment of the present invention, a microscale or sub-microscale signal line is interconnected with one set of parallel nanowires emanating from a nanowire-crossbar memory by configurable, nanowire-junction switches. The microscale or sub-microscale signal line serves as a single-wire multiplexer, allowing the contents of any particular single-bit storage element within the nanowire-crossbar memory to be read in a three-cycle READ operation.Type: GrantFiled: April 22, 2005Date of Patent: November 4, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Philip J. Kuekes, R. Stanley Williams
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Patent number: 7446044Abstract: Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.Type: GrantFiled: September 19, 2006Date of Patent: November 4, 2008Assignee: California Institute of TechnologyInventors: Anupama B. Kaul, Eric W. Wong, Richard L. Baron, Larry Epp
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Publication number: 20080265293Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.Type: ApplicationFiled: December 27, 2007Publication date: October 30, 2008Inventors: Bo Hyun Lee, Tae Hyoung Moon, Jae Hyun Kim
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Patent number: 7439562Abstract: The present invention concerns a method for modyfing at least an electronic property of a carbon nanotube or nanowire comprising exposing said nanotube or nanowire to an acid having the formula (I) wherein R1, R2 and R3 are chosen in the group comprising (H, F, Cl, Br, I) with at least one of R1, R2 and R3 being different from H. At least part of the nanotube or nanowire may be a channel region of a field effect transistor.Type: GrantFiled: April 22, 2003Date of Patent: October 21, 2008Assignee: Commissariat a l'Energie AtomiqueInventors: Stéphane Auvray, Jean-Philippe Bourgoin, Vincent Derycke, Marcelo Goffman
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Patent number: 7436033Abstract: A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region. The effects of the gate voltage on electrons passing through the channel can be maximized, and a variation gain of current supplied between the source and drain electrodes relative to the gate voltage can be greatly increased. Thus, a molecular electronic circuit having high functionality and reliability can be obtained.Type: GrantFiled: May 24, 2005Date of Patent: October 14, 2008Assignee: Electronics and Telecommunications Research InstituteInventors: Chan Woo Park, Sung Yool Choi, Han Young Yu, Ung Hwan Pi
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Publication number: 20080237716Abstract: An integrated circuit structure comprising a boron etch-stop layer on a surface of the integrated circuit structure having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon. In one embodiment, the boron etch-stop layer has a FWHM thickness value less than 20 nanometers and may contain added germanium or carbon. Systems and devices containing same are also disclosed. Chemical vapor deposition (CVD) may be used to form the boron etch-stop layer.Type: ApplicationFiled: May 2, 2008Publication date: October 2, 2008Inventor: Darwin G. Enicks
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Publication number: 20080231361Abstract: Small-signal and other circuit design techniques realized by carbon nanotube field-effect transistors (CNFETs) to create analog electronics for analog signal handling, analog signal processing, and conversions between analog signals and digital signals. As the CNFETs exist and operate at nanoscale, they can be readily collocated or integrated into carbon nanotube sensing and transducing systems. Such collocation and integration is at, or adequately near, nanoscale.Type: ApplicationFiled: February 4, 2008Publication date: September 25, 2008Inventor: Lester F. LUDWIG
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Patent number: 7423285Abstract: The difficulty of miniaturization of large-scale integrated circuits in electric devices based on the conventional techniques involving three-dimensional device structures or the introduction of novel materials is solved. Wires 2 and 3 are disposed to intersect one another in midair in a matrix. The ends of the wires 2 and 3 in midair are designed to be in direct contact with the insides of a package which contains a semiconductor device so that electrical connection and/or physical support can be acquired. Cross point 1 where wires 2 and 3 are in contact with each other is a region which has current switching function similar to the function of a channel of a common MOSFET. Cross point 1 is a region where base wire 2 functioning as a substrate and gate electrode wire 3 functioning as a control electrode (gate electrode) intersect in contact with one another, or a region where base wire 2 and a lead wire 4 overlap.Type: GrantFiled: January 10, 2006Date of Patent: September 9, 2008Assignee: Sharp Kabushiki KaishaInventor: Hiroshi Ohki
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Patent number: 7410853Abstract: In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.Type: GrantFiled: May 10, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Joon Ahn, Choong-Ho Lee, Chul Lee
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Patent number: 7411241Abstract: A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.Type: GrantFiled: January 5, 2006Date of Patent: August 12, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Nam Kim, Yun-Gi Kim
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Publication number: 20080179586Abstract: An electronic device includes a primary nanowire of a first conductivity type, and a secondary nanowire of a second conductivity type extending outwardly from the primary nanowire. A doped region of the second conductivity type extends from the secondary nanowire into at least a portion of the primary nanowire.Type: ApplicationFiled: January 29, 2007Publication date: July 31, 2008Inventor: Theodore I. Kamins
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Patent number: 7405129Abstract: A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising a lead selenide nanowire or nanocrystal film and methods of forming these devices.Type: GrantFiled: May 26, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Cherie R. Kagan, Christopher B. Murray, Robert L. Sandstrom, Dmitri V. Talapin
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Patent number: 7402506Abstract: A thin film transistor comprises a zinc-oxide-containing semiconductor material. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating a thin film transistor device, wherein the substrate temperature is no more than 300° C. during fabrication.Type: GrantFiled: June 16, 2005Date of Patent: July 22, 2008Assignee: Eastman Kodak CompanyInventors: David H. Levy, Andrea C. Scuderi, Lyn M. Irving
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Publication number: 20080169503Abstract: A semiconductor structure is provided, which includes multiple sections arranged along a longitudinal axis. Preferably, the semiconductor structure comprises a middle section and two terminal sections located at opposite ends of the middle section. A semiconductor core having a first dopant concentration preferably extends along the longitudinal axis through the middle section and the two terminal sections. A semiconductor shell having a second, higher dopant concentration preferably encircles a portion of the terminal sections, but not at the middle section, of the semiconductor structure. It is particularly preferred that the semiconductor structure is a nanostructure having a cross-sectional dimension of not more than 100 nm.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Appenzeller, Supratik Guha, Emanuel Tutuc
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Patent number: 7394118Abstract: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized.Type: GrantFiled: March 9, 2005Date of Patent: July 1, 2008Assignee: University of Southern CaliforniaInventor: Chongwu Zhou
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Patent number: 7390947Abstract: A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.Type: GrantFiled: January 18, 2005Date of Patent: June 24, 2008Assignee: Intel CorporationInventors: Amlan Majumdar, Justin K. Brask, Marko Radosavljevic, Suman Datta, Brian S. Doyle, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Robert S. Chau, Uday Shah, James Blackwell
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Publication number: 20080142850Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.Type: ApplicationFiled: August 8, 2007Publication date: June 19, 2008Applicant: NANTERO, INC.Inventors: Claude L. BERTIN, X. M. H. HUANG, Thomas RUECKES, Ramesh SIVARAJAN
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Publication number: 20080135892Abstract: This invention relates to field effect transistors having carbon nanotube contacts and to a method of making these field effect transistors. The field effect transistors have better contacts as the source and drains as well as the bridge are made of carbon nanotubes. The fabrication of the proposed embodiment becomes possible by using a fabrication process which involves exposing the structure to two different temperatures.Type: ApplicationFiled: July 24, 2007Publication date: June 12, 2008Inventor: Paul Finnie
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Patent number: 7385231Abstract: A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate surface, depositing a thin film on the fine-particle-placed substrate, and then removing the fine particles to form fine pores in the thin film; further, a method of producing an electron emitting element, which has the steps of: adding a catalyst metal on a substrate, placing fine particles onto the catalyst-added substrate, depositing a thin film on the fine-particle-placed substrate, then removing the fine particles to form fine pores in the film, and growing needle-shaped conductors on the catalyst metal that is exposed on a bottom face of the fine pore.Type: GrantFiled: August 31, 2006Date of Patent: June 10, 2008Assignee: FujifilmCorporationInventors: Kiyoshi Fujimoto, Masakazu Nakamura
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Publication number: 20080121996Abstract: A transistor with a carbon nanotube channel and a method of manufacturing the same. At least two gate electrodes are formed on a gate insulating layer formed on a carbon nanotube channel and are insulated from each other. Thus, the minority carrier may be reduced or prevented from flowing into the carbon nanotube channel. Accordingly, it is possible to reduce or prevent a leakage current that is generated when both the majority carrier and the minority carrier flow into the carbon nanotube channel. Therefore, characteristics of the transistor may not be degraded due to the leakage current.Type: ApplicationFiled: September 13, 2005Publication date: May 29, 2008Inventors: Wan-jun Park, Byoung-ho Cheong, Eun-ju Bae, Hans Kosina, Mahdi Fourfath
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Publication number: 20080121987Abstract: Novel nanodot and nanowire based MOSFET device structures and their fabrication processes are invented. These devices can be fabricated with the processes that do not need the extremely high lithographic resolution. The MOSFET devices remain functional even the nanodots and nanowires with varying sizes are randomly distributed. The activated number of nanodots and its total effective channel length/width are affected by the polished thickness of the insulation material in the CMP process. Therefore it is important to have a highly accurate control of CMP polishing rate to ensure a reliable process.Type: ApplicationFiled: November 6, 2006Publication date: May 29, 2008Inventor: Yijian Chen
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Publication number: 20080099840Abstract: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width half-maximum (FWHM) thickness value of less than 100 nanometers. The boron layer is formed by a chemical vapor deposition (CVD) system.Type: ApplicationFiled: October 26, 2006Publication date: May 1, 2008Applicant: Atmel CorporationInventor: Darwin G. Enicks
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Patent number: 7359888Abstract: A method for configuring nanoscale neural network circuits using molecular-junction-nanowire crossbars, and nanoscale neural networks produced by this method. Summing of weighted inputs within a neural-network node is implemented using variable-resistance resistors selectively configured at molecular-junction-nanowire-crossbar junctions. Thresholding functions for neural network nodes are implemented using pFET and nFET components selectively configured at molecular-junction-nanowire-crossbar junctions to provide an inverter. The output of one level of neural network nodes is directed, through selectively configured connections, to the resistor elements of a second level of neural network nodes via circuits created in the molecular-junction-nanowire crossbar. An arbitrary number of inputs, outputs, neural network node levels, nodes, weighting functions, and thresholding functions for any desired neural network are readily obtained by the methods of the present invention.Type: GrantFiled: January 31, 2003Date of Patent: April 15, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventor: Greg Snider
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Publication number: 20080067495Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.Type: ApplicationFiled: June 20, 2007Publication date: March 20, 2008Applicant: Interuniversitair Microelektronica Centrum (IMEC)Inventor: Anne S. Verhulst
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Patent number: 7339184Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.Type: GrantFiled: April 29, 2005Date of Patent: March 4, 2008Assignee: Nanosys, IncInventors: Linda T. Romano, Jian Chen, Xiangfeng Duan, Robert S. Dubrow, Stephen A. Empedocles, Jay L. Goldman, James M. Hamilton, David L. Heald, Francesco Lemmi, Chunming Niu, Yaoling Pan, George Pontis, Vijendra Sahi, Erik C. Scher, David P. Stumbo, Jeffery A. Whiteford
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Patent number: 7330709Abstract: Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. First, second, third and fourth switching elements each have an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The receiver circuit can sense small voltage inputs and convert them to larger voltage swings.Type: GrantFiled: January 10, 2005Date of Patent: February 12, 2008Assignee: Nantero, Inc.Inventor: Claude L. Bertin
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Patent number: 7323730Abstract: The invention relates to a semiconductor device comprising at least two electrodes and at least one nanotube or nanowire, in particular a carbon nanotube or nanowire, the device including at least one semiconductive nanotube or nanowire having at least one region that is covered at least in part by at least one layer of molecules or nanocrystals of at least one photosensitive material, an electrical connection between said two electrodes being made by at least one nanotube, namely said semiconductive nanotube or nanowire and optionally by at least one other nanotube or nanowire.Type: GrantFiled: July 20, 2005Date of Patent: January 29, 2008Assignee: Commissariat a l'Energie AtomiqueInventors: Julien Borghetti, Jean-Philippe Bourgoin, Pascale Mordant, Vincent Derycke, Arianna Filoramo, Marcelo Goffman
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Publication number: 20080006883Abstract: A nanostructured integrated circuit including a nanostructured element and a thin film transistor (TFT) and capacitor formed along the nanostructured element. The nanostructured element includes: an inner semiconductor material; and an outer insulating layer. The TFT includes: the inner semiconductor material of the nanostructured element; a source electrode electrically coupled to a source portion of the inner semiconductor material; a drain electrode electrically coupled to a drain portion of the inner semiconductor material; a gate portion of the outer insulating layer located between the source electrode and the drain electrode; and a gate electrode formed on the gate portion. The capacitor includes: a capacitor portion of the outer insulating layer of the nanostructured element; and a capacitor electrode formed on the capacitor portion. The capacitor portion of the outer insulating layer is located between the gate portion of the outer insulating layer and either the drain or source electrode.Type: ApplicationFiled: June 26, 2006Publication date: January 10, 2008Inventor: Kiyotaka Mori
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Patent number: 7307271Abstract: A nano-colonnade structure-and methods of fabrication and interconnection thereof utilize a nanowire column grown nearly vertically from a (111) horizontal surface of a semiconductor layer to another horizontal surface of another layer to connect the layers. The nano-colonnade structure includes a first layer having the (111) horizontal surface; a second layer having the other horizontal surface; an insulator support between the first layer and the second layer that separates the first layer from the second layer. A portion of the second layer overhangs the insulator support, such that the horizontal surface of the overhanging portion is spaced from and faces the (111) horizontal surface of the first layer. The structure further includes a nanowire column extending nearly vertically from the (111) horizontal surface to the facing horizontal surface, such that the nanowire column connects the first layer to the second layer.Type: GrantFiled: November 5, 2004Date of Patent: December 11, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: M. Saif Islam, Philip J. Kuekes, Shih-Yuan Wang, Duncan R. Stewart, Shashank Sharma
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Patent number: 7307448Abstract: Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.Type: GrantFiled: May 24, 2005Date of Patent: December 11, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gregory S. Snider, Philip J. Kuekes
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Patent number: 7301199Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.Type: GrantFiled: July 16, 2002Date of Patent: November 27, 2007Assignee: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong
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Patent number: 7297615Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.Type: GrantFiled: January 30, 2006Date of Patent: November 20, 2007Assignee: Samsung Electronics, Co., Ltd.Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
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Patent number: 7294519Abstract: Provided are a semiconductor light-emitting device having nano-needles and a method of manufacturing the same. The provided semiconductor light-emitting device improves the extraction efficiency of photons, and includes a gallium nitride (GaN) group multi-layer and nano-needles grown on the GaN group multi-layer. The nano-needles improve the extraction efficiency of photons.Type: GrantFiled: June 17, 2005Date of Patent: November 13, 2007Assignee: Luxpia Co., Ltd.Inventors: Jong Soo Lee, Min Sang Lee, Young Ki Lee
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Patent number: 7276424Abstract: Methodologies associated with fabricating aligned nanowire lattices are described. One exemplary method embodiment includes providing a twist wafer bonded thin single crystal semiconductor film and a bulk single crystal substrate of the same material. Periodic non-uniform elastic strains present on the surface of the film control the positions where nanocrystals will form on the film. The strains may be removed via annealing and alloying after the formation of nanocrystal arrays.Type: GrantFiled: June 29, 2005Date of Patent: October 2, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Qingqiao Wei
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Publication number: 20070187729Abstract: Example embodiments relate to a unipolar carbon nanotube having a carrier-trapping material and a unipolar field effect transistor having the unipolar carbon nanotube. The carrier-trapping material, which is sealed in the carbon nanotube, may readily transform an ambipolar characteristic of the carbon nanotube into a unipolar characteristic by doping the carbon nanotube. Also, p-type and n-type carbon nanotubes and field effect transistors may be realized according to the carrier-trapping material.Type: ApplicationFiled: October 24, 2006Publication date: August 16, 2007Inventors: Wan-jun Park, Noe-jung Park
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Patent number: 7257022Abstract: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.Type: GrantFiled: December 14, 2006Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7253431Abstract: A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device.Type: GrantFiled: February 11, 2005Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Phaedon Avouris, Jia Chen, Christian Klinke, Paul M. Solomon
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Patent number: 7253065Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.Type: GrantFiled: October 1, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
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Patent number: 7245520Abstract: A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive nanotube, and a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between a channel electrode and an output node. Input nodes of the first and second inverters are coupled to the set electrodes and the output nodes of the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or in a shadow memory or store mode to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode to transfer the state of the nanotube switching elements to the electronic memory.Type: GrantFiled: September 20, 2005Date of Patent: July 17, 2007Assignee: Nantero, Inc.Inventors: Claude L. Bertin, Thomas Ruckes, Brent M. Segal
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Patent number: 7187201Abstract: Pullup and pulldown structures can be formed using nanoscale programmable junctions. These devices can be integrated into nanoscale circuit designs and can be programmably configured, e.g., desired resistance values set. Additionally, the pullup and pulldown devices allow for convenient integration of nanoscale devices with microscale devices.Type: GrantFiled: June 24, 2004Date of Patent: March 6, 2007Assignee: Xilinx, Inc.Inventor: Stephen M. Trimberger
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Patent number: 7180107Abstract: A method of fabricating a tunneling nanotube field effect transistor includes forming in a nanotube an n-doped region and a p-doped region which are separated by an undoped channel region of the transistor. Electrical contacts are provided for the doped regions and a gate electrode that is formed upon a gate dielectric layer deposited on at least a portion of the channel region of the transistor.Type: GrantFiled: May 25, 2004Date of Patent: February 20, 2007Assignee: International Business Machines CorporationInventors: Joerg Appenzeller, Joachim Knoch
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Patent number: 7176478Abstract: New, hybrid vacuum electron devices are proposed, in which the electrons are extracted from the nanotube into vacuum. Each nanotube is either placed on the cathode electrode individually or grown normally to the cathode plane. Arrays of the nanotubes are also considered to multiply the output current. Two- and three-terminal device configurations are discussed. In all the cases considered, the device designs are such that both input and output capacitances are extremely low, while the efficiency of the electron extraction into vacuum is very high, so that the estimated operational frequencies are expected to be in a tera-hertz range. New vacuum triode structure with ballistic electron propagation along the nanotube is also considered.Type: GrantFiled: January 26, 2004Date of Patent: February 13, 2007Inventors: Alexander Kastalsky, Sergey Shokhor
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Patent number: 7161168Abstract: Fabrication of metallic or non-metallic wires with nanometer widths and nanometer separation distances without the use of lithography. Wires are created in a two-step process involving forming the wires at the desired dimensions and transferring them to a planar substrate. The dimensions and separation of the wires are determined by the thicknesses of alternating layers of different materials that are in the form of a superlattice. Wires are created by evaporating the desired material onto the superlattice that has been selectively etched to provide height contrast between layers. The wires thus formed upon one set of superlattice layers are then transferred to a substrate.Type: GrantFiled: July 28, 2003Date of Patent: January 9, 2007Assignee: The Regents of the University of CaliforniaInventors: James R. Heath, Pierre M. Petroff, Nicholas A. Melosh
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Patent number: 7154778Abstract: Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions. A gate insulator is formed opposing the channel region. The gate insulator includes a number of high work function nanoparticles. A gate is formed on the gate insulator. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The MOSFET is a programmed MOSFET having a charge trapped in the number of high work function nanoparticles in the gate insulator adjacent to the first source/drain region.Type: GrantFiled: February 14, 2005Date of Patent: December 26, 2006Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7115916Abstract: A light emitting device comprises a gate electrode, a channel comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode, a source coupled to a first end of the channel injecting electrons into the channel, and a drain coupled to a second end of the channel injecting holes into the channel.Type: GrantFiled: September 26, 2002Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Guy Moshe Cohen, Richard Martel, James A. Misewich, James Chen-Hsiang Tsang
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Patent number: 7112816Abstract: A carbon nanotube sensor and a method of producing the carbon nanotube sensor are disclosed. The sensor detects small particles and molecules. The sensor includes a gate, a source and a drain positioned on the gate, and a carbon nanotube grown from a catalytic material and extending from one of the source and the drain. The method includes the step of functionalizing an end of the carbon nanotube with a receptor. As such, the carbon nanotube is receptive to the small particles and molecules. The carbon nanotube is driven at a resonance, and the resonance of the carbon nanotube is measured when the end of the carbon nanotube is free of the small particles and the molecules. The method includes monitoring for a change in the resonance to detect the association of the small particles and molecules with the end of the carbon nanotube.Type: GrantFiled: April 14, 2003Date of Patent: September 26, 2006Assignee: University of South FlordiaInventors: Rudiger Schlaf, Shekhar Bhansali
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Patent number: 7105874Abstract: A single electron transistor having a memory function and a fabrication method thereof are disclosed. In the single electron transistor, a first substrate and an insulation film are sequentially stacked, a second substrate is stacked on the insulation film and includes a source region, a channel region, and a drain region, a tunneling film is formed on the second substrate, at least two trap layers are formed on the tunneling film and are separated by an interval such that at least one quantum dot may be formed in a same interval in the channel region, and a gate electrode is formed to contact the at least two trap layers and the tunneling film between the at least two trap layers. Because the single electron transistor is simple and includes a single gate electrode, a fabricating process and an operational circuit thereof may be simplified, and power consumption may be reduced.Type: GrantFiled: February 9, 2004Date of Patent: September 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-doo Chae, Chung-woo Kim, Ju-hyung Kim
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Patent number: 7102157Abstract: New, hybrid vacuum electronic devices are proposed, in which the electrons are extracted from the nanotube into vacuum. Each nanotube is either placed on the cathode electrode individually or grown normally to the cathode plane. Arrays of the nanotubes are also considered to multiply the output current. Two- and three-terminal device configurations are discussed. In all the cases considered, the device designs are such that both input and output capacitances are extremely low, while the efficiency of the electron extraction into vacuum is very high, so that the estimated operational frequencies are expected to be in a tera-hertz range. New vacuum triode structure with ballistic electron propagation along the nanotube is also considered.Type: GrantFiled: May 23, 2005Date of Patent: September 5, 2006Inventors: Alexander Kastalsky, Sergey Shokhor
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Patent number: 7087920Abstract: A nanowire includes a single crystalline semiconductor material having an exterior surface and an interior region and at least one dopant atom. At least a portion of the nanowire thermally switches between two conductance states; a high conductance state, where a high fraction of the dopant atoms is in the interior region, and a low conductance state, where a lower fraction of the dopant atoms is at the interior region and a higher fraction of the atoms is at the exterior surface.Type: GrantFiled: January 21, 2005Date of Patent: August 8, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Theodore I. Kamins