Abstract: A method and system of translating addresses is disclosed that includes receiving an effective address for translation, providing a processor and a translation buffer where the translation buffer has a plurality of entries, wherein each entry contains a mapping of an effective address directly to a corresponding real address, and information on a corresponding intermediate virtual address. The method and system further include determining whether the translation buffer has an entry matching the effective address, and in response to the translation buffer having an entry with a matching effective address, providing the real address translation from the entry having the matching effective address.

Abstract: An information processing system that is capable of accurately predicting a lifetime of a semiconductor device that carries out communications related to reading and writing of data from and to a storage device. The information processing system has an image forming apparatus having a nonvolatile memory and a first controller that controls reading and writing of data from and to the nonvolatile memory. The information processing system also has a server that monitors a lifetime of the first controller. The server has a receiving I/F that receives information indicating a communication data size of reading and writing of data from and to the nonvolatile memory, and a second controller that predicts the lifetime of the first controller based on the received information indicating the communication data size.

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Abstract: Non-volatile memory (NVM) dies of a data storage device, wherein on-chip latches of the dies are made available to a host device for use as volatile memory. In some examples, a data storage controller dynamically determines when the latches of a particular NVM die of an NVM array are available for use as volatile memory and exports those particular latches to the host device for use as random access memory (RAM). In other examples, the data storage controller dynamically determines when particular dies of the NVM array of dies are available and exports all latches of those dies to the host device for use as RAM. The data storage controller may rotate NVM die usage so that, over time, different dies are used for latch-based volatile memory while other dies are used for NVM storage. Usage profiles are described that allow the host device to select particular latch usage configurations.

Abstract: Described is a system for synchronizing expiration times for incremental backup data stored on a cloud-based object storage. More particularly, the system may provide a layer of intelligence when updating the expiration times associated with backup data to ensure that a full recovery of the client data to a point-in-time of any incremental backup may be performed. To provide such a capability, the system may maintain specialized metadata identifying expiration times for objects and a list of objects required to perform a full recovery to a point-in-time for each of the performed backups (e.g. full or incremental). The system may access this metadata to identify which objects stored by a previous backup are still referenced by a subsequent backup. Based on the identified objects, the system may synchronize object expiration times to ensure objects are not prematurely deleted from the object storage.

Abstract: Embodiments of storage device architecture for processing data using machine learning are disclosed. In some embodiments, the storage device includes a separate I/O core and a neural network core. The storage device can create a copy of data streams in which the data is stored, and the neural network core can process the copy of the data streams in a neural network while the I/O core can perform read or write functions on the data streams.

Abstract: A computer-implemented method according to one embodiment includes receiving a request to withdraw a point-in-time snapshot copy operation being implemented by a data consistency application; in response to determining that the data consistency application is creating a current consistency group, maintaining the withdrawal request while allowing the creation of the current consistency group by the data consistency application; and in response to determining that the data consistency application is idle, preventing a formation of a new consistency group by the data consistency application during the withdrawal of the point-in-time snapshot copy operation.

Abstract: An information management system creates a modified representation of backup files in a backup copy on restore to overcome the difficulties and challenges imposed by the legal and administrative requirements on the handling of personally information without making changes to the backup copy. In an example, a restore modification component searches backup data files as they are restored from a backup copy but before the restored data files are written into the primary storage system. When the restore modification component identifies a backup data file with a record that matches search criteria defined in the modification repository, the restore modification component replaces one or more of the restored data field values in the record with replacement data values obtained from the modification repository according to respective replacement rules. In this way, the information management system can create a modified representation of the backup copy data without modifying the backup copy.

Abstract: Embodiments for balancing cloud resource capacity for cross-node movement of files in a scaled out backup system, and for dynamically allocating cloud storage resources in a multi-node network having a file system. A process determines a destination node with dedicated cloud storage capable of storing a file selected for long term retention. It transfers the file to the cloud storage of the destination node while maintaining metadata of the file in the cloud tier local storage of the destination node, such as by using remote procedure calls between the destination and source nodes. It then updates a global namespace of the file system with a handle indicating a current location of the file as the cloud storage of the destination file, thus allowing access to the file through the metadata stored in the local storage of the source node.

Abstract: The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a volatile memory, a non-volatile storage unit, and a controller. The data storage device further includes a plurality of virtual functions, where at least one of the virtual functions is only accessible by the data storage device and the remainder of the virtual functions are accessible by both the data storage and a host device. At least one of the virtual functions may be dedicated to completing data storage device storage management operations.

Abstract: A memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate is disclosed. The memory array alternates odd data bits of a first plurality of data words in consecutive columns a first sub-bank of first and second memory banks and even data bits of the first plurality of data words in consecutive columns of a second sub-bank of the first and second memory banks. For example, the lowest bits of each of N data words are stored in a first N consecutive columns of a first sub-bank. The second bits of the N data words are stored in the next N consecutive columns of a second sub-bank. The N data bits in each of the bit positions of the N data words are interleaved in corresponding column mux sets. Alternating odd and even bits between sub-banks reduces multi-bit soft errors.

Abstract: An apparatus and method for managing packet transfer between a memory fabric having a physical layer interface higher data rate than a data rate of a physical layer interface of another device, receives incoming packets from the memory fabric physical layer interface wherein at least some of the packets include different instruction types. The apparatus and method determine a packet type of the incoming packet received from the memory fabric physical layer interface and when the determined incoming packet type is of a type containing an atomic request, the method and apparatus prioritizes transfer of the incoming packet with the atomic request over other packet types of incoming packets, to memory access logic that accesses local memory within an apparatus.

Abstract: A storage system and method for improving utilization of a communication channel between a host and the storage system are provided. In one embodiment, a method is provided that is performed in a storage system in communication with a host via a communication channel. The method comprises determining utilization of the communication channel; and selecting a command for execution from a queue based at least in part on the determined utilization of the communication channel. The command can be selected also based on at least one other factor and based on a weighted priority-based function. Other embodiments are provided.

Abstract: A memory system identifies, in a logical to physical (L2P) journal associated with a memory device, a first journal entry reflecting a two pass programming operation, where the two pass programming operation includes a first pass to program data to a second memory location identified by a second physical address and a second pass to program a same data to a same second memory location identified by a same second physical address. The system determines whether the second pass of the two pass programming operation is complete. Responsive to determining that the second pass of the two pass programming operation is complete, the system causes a second journal entry of the L2P journal to reference from a first physical address to the second physical address. The system reconstructs the L2P table based on the second journal entry.

Abstract: According to one embodiment, a memory system includes a compressor configured to output second data obtained by compressing input first data and a non-volatile memory to which third data based on the second data output from the compressor is written. The compressor includes a dictionary coding unit configured to perform dictionary coding on the first data, an entropy coding unit configured to perform entropy coding on the result of the dictionary coding, a first calculation unit configured to calculate compression efficiencies of the dictionary coding and the entropy coding, and a first control unit configured to control an operation of at least one of the dictionary coding unit and the entropy coding unit based on the compression efficiencies and a power reduction level.

Abstract: In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

Abstract: Various embodiments enable versioning of data stored on a memory device, where the versioning allows the memory device to maintain different versions of data within a set of physical memory locations (e.g., a row) of the memory device. In particular, some embodiments provide for a memory device or a memory sub-system that uses versioning of stored data to facilitate a rollback operation/behavior, a checkpoint operation/behavior, or both. Additionally, some embodiments provide for a transactional memory device or a transactional memory sub-system that uses versioning of stored data to enable rollback of a memory transaction, commitment of a memory transaction, or handling of a read or write command associated with respect to a memory transaction.

Abstract: An algorithmic TCAM based ternary lookup method is provided. The method stores entries for ternary lookup into several sub-tables. All entries in each sub-table have a sub-table key that includes the same common portion of the entry. No two sub-tables are associated with the same sub-table key. The method stores the keys in a sub-table keys table in TCAM. Each key has a different priority. The method stores the entries for each sub-table in random access memory. Each entry in a sub-table has a different priority. The method receives a search request to perform a ternary lookup for an input data item. A ternary lookup into the ternary sub-table key table stored in TCAM is performed to retrieve a sub-table index. The method performs a ternary lookup across the entries of the sub-table associated with the retrieved index to identify the highest priority matched entry for the input data item.

Abstract: An apparatus comprises address translation circuitry (70) to perform a translation of a virtual address (80) comprising a virtual tag portion (88) and a virtual address portion (86) into a physical address (82) comprising a physical tag portion (92) and a physical address portion (90). The address translation circuitry comprises address tag translation circuitry (72) to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.

Abstract: Devices and techniques for arbitrating operation of memory devices in a managed NAND memory system to conform the operation to a power budget. In an example, a method can include initiating a first plurality of host-requested NAND memory operations of a first type at a first channel of a memory device for a first interval, and, at the completion of the first interval, performing a second plurality of homogeneous, host-requested NAND memory operations of a second type at the first multiple plane memory die for a second interval.