Patents Examined by Gautam Sain
  • Patent number: 11681464
    Abstract: Methods and apparatus for predicting a future estimated host read access rate for variable bit rate (VBR) data streams that include Program Clock Reference (PCR) indicators or other playback clock synchronization values. The VBR data stream may be encoded, for example, as a Motion Picture Experts Group (MPEG)-transport stream (TS). In some examples, a data storage device with a non-volatile memory (NVM) array parses an MPEG-TS VBR data stream retrieved from the NVM array to identify PCRs. Using the PCRs, the device estimates the future host data access rate for additional portions of MPEG-TS VBR data not yet requested by the host. The data storage device may then adaptively adjust background (e.g. overhead) management operations such as garbage collection based on the future host data access rate.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 20, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11681633
    Abstract: A memory system may include a memory device suitable for storing data and a controller suitable for generating and managing map data comprising a logical address of an external device and a physical address of the memory device corresponding to the logical address. The controller uploads at least some of the map data to the external device and uploading a latest version of the uploaded map data to the external device again based on dirty information or access information. The dirty information indicates whether a physical address corresponding to a logical address included in the uploaded map data has been changed. The access information indicates whether an access request for the logical address included in the uploaded map data from the external device has been made.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: June 20, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 11681621
    Abstract: Systems, devices and methods are provided for operating a skewed-associative cache in a data processing system and, in particular, for changing address-to-row mappings in a skewed-associative cache.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Arm Limited
    Inventor: Alexander Klimov
  • Patent number: 11663136
    Abstract: A non-volatile memory device includes a volatile memory, a non-volatile memory, and a controller. The controller is configured to map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory. The controller is configured to perform a storage capacity recovery operation for a region of the non-volatile memory that is selected based at least partially on a number of mappings for the region likely to be stored in the volatile memory for the storage capacity recovery operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 30, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Hongmei Xie, Dhanunjaya Rao Gorrle, Aajna Karki
  • Patent number: 11656782
    Abstract: A method is provided for use in a storage system, the method comprising: receiving an I/O request at an R-node; generating a deadline for the I/O request; generating a C-node command based on the I/O request; transmitting the C-node command and the I/O request to a C-node; calculating, by the C-node, a first remaining time based on the deadline; detecting, by the C-node, whether the first remaining time meets a first threshold; when the first remaining time meets the first threshold, executing the I/O request and transmitting, from the C-node to the R-node, synchronous replication request that is associated with the C-node command; and when the first remaining time does not meet the first threshold, causing the storage system to stop performing synchronous replication and executing the C-node command.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 23, 2023
    Assignee: Dell Products L.P.
    Inventors: Svetlana Kronrod, Xiangping Chen
  • Patent number: 11656999
    Abstract: An electronic device may include a processor, a first volatile memory, and a storage including a nonvolatile memory and a second volatile memory. The processor may be configured to: identify information of a specific file and a kind of a request for data included in the specific file in response to a creation of the request for the data, set a flag in the request based on the identified information of the specific file, identify whether mapping information of a specific region including a logical address of the data among mapping information in which logical addresses and physical addresses for the nonvolatile memory are mapped onto each other is stored in the first volatile memory, determine whether to manage the mapping information of the specific region using the first volatile memory, and determine whether to update the mapping information of the specific region in the first volatile memory.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 23, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Manjong Lee, Hyeongjun Kim, Changheun Lee, Jintae Jang
  • Patent number: 11656777
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may repeatedly execute, when entering a low power mode, iterations of a target operation according to a temperature of the memory system until a stop condition is satisfied. In this case, the target operation may be a garbage collection operation for the plurality of memory blocks or a migration operation of moving data stored in a first area including at least one of the plurality of memory blocks to a second area including at least one of the plurality of memory blocks. The operation speed of the memory block included in the first area may be higher than the operation speed of the memory block included in the second area.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventors: Young Mi Yoon, Hyoung Suk Jang
  • Patent number: 11620226
    Abstract: A method to prevent starvation of non-favored volumes in cache is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. A cache demotion algorithm is used to retain the favored storage elements in the cache longer than the non-favored storage elements. The method designates a maximum amount of storage space that the favored storage elements are permitted to consume in the cache. In preparation to free storage space in the cache, the method determines whether an amount of storage space consumed by the favored storage elements in the cache has reached the maximum amount. If so, the method frees storage space in the cache by demoting favored storage elements. If not, the method frees storage space in the cache in accordance with the cache demotion algorithm. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11614886
    Abstract: A memory system may write, when operating in a force unit access mode, first write data requested by the host to a buffer for temporarily storing data to be written the memory device and a first memory block among the plurality of memory blocks, and may write, when the size of the data accumulatively stored in the buffer is greater than or equal to A which is a unit of a size in which data is written to a second memory block among the plurality of memory blocks, second write data of size A among the data stored in the buffer to the second memory block. The operation speed of the first memory block may be set faster than the operation speed of the second memory block and the storage capacity of the first memory block may be set smaller than the storage capacity of the second memory block.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: March 28, 2023
    Assignee: SK hynix Inc.
    Inventor: Jae Il Lee
  • Patent number: 11614890
    Abstract: One or more requests are received from a host system while a media management scan is in progress on a memory component in a memory sub-system. The media management scan in progress is suspended. The request received from the host system are serviced. Once the host system is serviced, the media management scan is resumed on the memory component.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Marc S. Hamilton, Suresh Rajgopal
  • Patent number: 11609706
    Abstract: The present disclosure is directed to placement of samples of a read sample offset operation in a memory sub-system. A processing device determines a shape of a valley to be subject to a read sample offset operation, where the valley corresponds to at least one programming distribution of a memory sub-system. The processing device selects a sampling rule from a set of sampling rules based on the shape of the valley. The processing device executes the read sample offset operation in accordance with the sampling rule.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen, Larry Koudele
  • Patent number: 11579795
    Abstract: A control method for a solid state drive is provided. The solid state drive includes a non-volatile memory with plural blocks. In a step (a1), a block is opened. In a step (a2), a program action is performed to store a valid write data into the open block. Then, a step (a3) is performed to judge whether an amount of the valid write data in the open block reaches a predetermined capacity. In a step (a4), if the amount of the valid write data in the open block does not reach the predetermined capacity, the step (a2) is performed again. In a step (a5), if the amount of the valid write data in the open block reaches the predetermined capacity, the open block is closed and the step (a1) is performed again. The predetermined capacity is lower than a capacity of one block.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: February 14, 2023
    Assignee: SOLID STATE STORAGE TECHNOLOGY CORPORATION
    Inventors: Shih-Hung Hsieh, Hsuan-Yi Chiang, Shi-Xuan Chen, Tzu-Chieh Lin
  • Patent number: 11580059
    Abstract: A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 14, 2023
    Assignee: Marvell Asia Pte. Ltd.
    Inventors: Venkatraghavan Bringivijayaraghavan, Aravindan J. Busi, Deepak I. Hanagandi, Igor Arsovski
  • Patent number: 11561834
    Abstract: Described are self-learning systems and methods for adaptive management of memory resources within a memory hierarchy. Memory allocations associated with different active functions are organized into blocks for placement in alternative levels in a memory hierarchy optimized for different metrics of e.g. cost and performance. A host processor monitors a performance metric of the active functions, such as the number of instructions per clock cycle, and reorganizes the function-specific blocks among the levels of the hierarchy. Over time, this process tends toward block organizations that improve the performance metric.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: January 24, 2023
    Assignee: Rambus Inc.
    Inventors: Joseph James Tringali, Jianbing Chen, Evan Lawrence Erickson, Keith Lowrey
  • Patent number: 11550501
    Abstract: A method for execution by a storage unit in a dispersed storage network (DSN) includes selecting a storage zone of a memory device of the storage unit based on zone allocation parameters, and designating the selected storage zone as open for writes. A data slice is received via a network for storage. The data slice is written sequentially at a memory location of the one of storage zone based on determining that the storage zone is designated as open for writes. A pointer corresponding to the data slice that indicates the storage zone and the memory location is generated. A read request is received via the network from a requesting entity that indicates the data slice. The data slice is retrieved from the memory device based on the pointer, and is transmitted to the requesting entity.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 10, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Manish Motwani, Praveen Viraraghavan, Ilya Volvovski
  • Patent number: 11531468
    Abstract: Disclosed herein is a technique for managing storage space in a user device. Users are provided with options to manage storage space usage in an organized and efficient manner. The options can include recommendations to the user regarding automatically and/or manually purging data from the user device to free up a particular amount of storage space that is needed to carry out a particular task.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 20, 2022
    Assignee: Apple Inc.
    Inventors: Steve S. Ko, Jean-Pierre Ciudad, Kazuhisa Yanagihara
  • Patent number: 11531614
    Abstract: Virtual memory space may be saved in a clone environment by leveraging the similarity of the data signatures in swap files when a chain of virtual machines (VMs) includes clones spawned from a common parent and executing common applications. Deduplication is performed across the chain, rather than merely within each VM. Examples include generating a common deduplication identifier (ID) for the chain; generating a logical addressing table linked to the deduplication ID, for each of the VMs in the chain; and generating a hash table for the chain. Examples further include, based at least on a swap out request, generating a hash value for a block of memory to be written to a storage medium; and based at least on finding the hash value within the hash table, updating the logical addressing table to indicate a location of a prior-existing duplicate of the block on the storage medium.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: December 20, 2022
    Assignee: VMware, Inc.
    Inventors: Tanay Ganguly, Zubraj Singha, Goresh Musalay, Kashish Bhatia
  • Patent number: 11520505
    Abstract: It is desired to provide a technique capable of reducing the time and the power consumption required for computation. Provided is an information processing apparatus including a storage control unit that writes data read from a read target area of an external memory having multiple dimensions to a storage area having the multiple dimensions and a processing unit that executes processing based on the data of the storage area, in which the storage control unit moves the read target area in a first dimension direction in the external memory and performs first overwrite of a back end area of the storage area in a direction corresponding to the first dimension direction with data of a front end area of the read target area after movement in the first dimension direction.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 6, 2022
    Assignee: SONY CORPORATION
    Inventor: Yuji Takahashi
  • Patent number: 11507288
    Abstract: Detecting and reconfiguring of boot parameters of a NVMe subsystem, including identifying a mapping between local boot parameters of a NVMe subsystem and a GUID that corresponds to the NVMe subsystem; determining that the NVMe subsystem has been reset; in response to determining that the NVMe subsystem has been reset: transmitting a discovery request to the NVMe subsystem for remote boot parameters of the NVMe subsystem; comparing the local boot parameters for the GUID with the remote boot parameters for the NVMe subsystem; determining, based on the comparing, that the remote boot parameters for the NVMe subsystem do not match with the local boot parameters for the GUID, and in response, updating values of the local boot parameters for the GUID based on the remote boot parameters of the NVMe subsystem.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: November 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Deepaganesh Paulraj, Chandrasekhar Puthillathe, Manjunath A M
  • Patent number: 11500735
    Abstract: Embodiments of the present disclosure provide a method of backup management, an electronic device and a computer program product. The method comprises: determining a plurality of candidate backup policies for a plurality of clients of a data backup system, determining an expected load balance degree with respect to time for the data backup system to perform data backups for the plurality of clients using the plurality of candidate backup policies, determining an actual load balance degree with respect to time for the data backup system while the data backup system is performing the data backups for the plurality of clients using a plurality of current backup policies, and selecting a plurality of backup policies to be used for the plurality of clients respectively, based on a comparison of the expected load balance degree and the actual load balance degree.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 15, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Wei Wang, Boda Lei