Abstract: A memory system may include a memory device and a memory controller. The memory device may include input/output pads. The memory controller may control an operation of the memory device through the input/output pads. The memory controller may generate an offset adjustment command and transmit the offset adjustment command to the memory device. The memory device may store an offset of a signal received to the input/output pads, in response to the offset adjustment command.

Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

Abstract: A method for storing data includes obtaining data, applying an erasure coding procedure to the data to obtain a plurality of data chunks and a parity chunk, deduplicating the plurality of data chunks to obtain a plurality of deduplicated data chunks, storing, across a plurality of nodes, the plurality of deduplicated data chunks and the parity chunk, and tracking location information for each of the plurality of deduplicated data chunks and the parity chunk.

Abstract: Apparatus, media, methods, and systems for data storage systems and methods for optimized scheduling of background management operations. A data storage system may comprise a controller. The controller is configured to determine a timeout value of an adaptive timeout parameter of the data storage system. The controller is configured to determine whether a first host operation is received. The controller is configured to, when the first host operation is not received, determine whether the timeout value satisfies a threshold value. The controller is configured to, when the timeout value satisfies the threshold value, cause one or more background management operations to be executed at the data storage system.

Abstract: According to one embodiment, when it is determined that a first storage device of a plurality of storage devices is to be removed and an additional storage device is connected to a storage controller, the storage controller writes update data portions corresponding to data portions already written to the first storage device to any storage device selected from remaining one or more storage devices of the plurality of storage devices except for the first storage device and the additional storage device. Further, the storage controller writes update data portions corresponding to data portions already written to the remaining one or more storage devices to any storage device selected from the remaining one or more storage devices and the additional storage device.

Abstract: Embodiments of the present disclosure provide a method and device for storing data. The method comprises: generating a data block corresponding to data to be stored; aligning the data block to a boundary of a tracking unit of a predefined size for validating the data; and storing the aligned data block in at least one storage unit of a storage space, the at least one storage unit having an identical size. The method according to embodiments of the present disclosure can align the data block so as to minimize the waste of storage space and avoid the situation where the rest data cannot be validated due to disappearance of partial data.

Abstract: A RAID storage-device-assisted RMW system includes a RAID primary data drive that retrieves second primary data via a DMA operation from a host system, and XOR's it with its first primary data to produce first interim parity data that it writes via a DMA operation to a RAID parity data drive. The RAID parity data drive XOR's its first parity data and the first interim parity data to produce second parity data that overwrites the first parity data. The RAID parity data drive also performs GF operations on the first interim parity data and its second interim parity data and XOR's the results to produce interim Q data that it writes via a DMA operation to a RAID Q data drive. The RAID Q data drive XOR's its first Q data and the interim Q data to produce second Q data that overwrites the first Q data.

Abstract: A method for use in a storage system disclosed, comprising: transitioning the storage system into a first state, the first state including a state in which a source system performs synchronous replication to a target system; detecting a first event while the source system is in the first state; in response to the first event, transitioning the storage system from the first state into a second state, the second state being a state in which the source system performs asynchronous replication; detecting a second event while the storage system is in the second state, transitioning the source system from the second state into a third state, the third state including a state in which the source system performs both synchronous replication and asynchronous replication.

Abstract: A modification-frequency-based tiered data storage garbage collection system includes a storage device coupled to a host engine. The storage device includes a data storage and garbage collection engine and storage subsystems. The data storage and garbage collection engine receives first modified data from the host engine that provides a modification to first current data stored in a first data storage element provided by one of the storage subsystems and grouped in a first superblock associated with a first data modification frequency range. The data storage and garbage collection engine then determines a first frequency of modification of the first current data and, based on that, writes the first modified data to a second data storage element provided by one of the storage subsystems and grouped in a second superblock associated with a second data modification frequency range that is different than the first data modification frequency range.

Abstract: An ALUA path distribution system includes host devices coupled to storage subsystems by aggregated networking devices. A first aggregated networking device snoops communications between the host devices and the storage subsystems to identify first snooped information, receives second snooped information identified by a second aggregated networking device, and uses the snooped information to build a path distribution table identifying each active-optimized path provided by the aggregated networking devices between the host devices and respective LUNs on the storage subsystems.

Abstract: A method and system for intelligent control of read-ahead cache for a client application is provided. The method receives an application profile of the client application, the application profile indicating thresholds for determining a plurality of access patterns of the client application. The method also determines a current access pattern of the client application based on the thresholds and a historical access pattern of the client application. The current access pattern and the historical access pattern are one of the plurality of access patterns. The method further dynamically enables and disables read-ahead cache for the client application based on a transition between the historical access pattern and the current access pattern.

Abstract: Memory transactions can be tagged with a partition identifier selected depending on which software execution environment caused the memory transaction to be issued. A memory system component can control allocation of resources for handling the memory transaction or manage contention for said resources depending on a selected set of memory system component parameters selected depending on the partition identifier specified by the memory transaction, or can control, depending on the partition identifier specified by the memory transaction, whether performance monitoring data is updated in response to the memory transaction. Page table walk memory transactions may be assigned a different partition identifier to the partition identifier assigned to the corresponding data/instruction access memory transaction.

Abstract: In one example, a method can be performed that involves receiving a backup request specifying: one or more files to be backed up; a group of one or more categories, each of which corresponds to a respective range of file sizes; and, one or more storage destinations, categorizing each of the files by assigning a respective category to each file, initiating a respective backup datastream corresponding to each category that has been assigned, and requesting that each backup datastream be backed up at the respective storage destination that corresponds to the assigned category associated with that backup datastream.

Abstract: A memory controller includes a random data generator configured to generate first random data based on write data and a first seed, the write data for storing in a selected page in a memory device; and a bit pattern determiner configured to generate data distribution information indicating whether the random data is a first type or a second type. The random data generator generates second random data when the data distribution information indicates the second type, the second random data being different from the first random data.

Abstract: Embodiments of this disclosure allow non-position-independent-code to be shared between a closed application and a subsequent application without converting the non-position-independent-code into position-independent-code. In particular, embodiment techniques store live data of a closed application during runtime of the closed application, and thereafter page a portion of the live data that is common to both the closed application and a subsequent application back into volatile memory at the same virtual memory address in which the portion of live data was stored during runtime of the closed application so that the paged lived data may be re-used to execute the subsequent application in the managed runtime environment. Because the paged live data is stored at the same virtual memory address during the runtimes of both applications, non-position-independent-code can be shared between the applications.

Abstract: Embodiments of the present invention relate to a memory system, a memory device, a memory controller and an operating method thereof. A partial mapping table including some of plural pieces of mapping information between physical addresses and logical addresses, which are included in a mapping table stored in the memory device, is cached, a piece of mapping information corresponding to data indicated by a command is referred to in the partial mapping table, and whether to perform an update for a reference-related parameter of the piece of mapping information is controlled depending on a size of the data, thereby improving cache efficiency for mapping informations for processing a request from a host and through this, increasing the success rate of a cache hit.

Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.

Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.

Abstract: A method, computer program product, and computer system for requesting, by a computing device, information about whether a source and a destination belong to one of a same storage array and storage cluster. Information may be requested about whether the source and the destination support direct data transfer mechanisms between the source and the destination. A copy process may be offloaded from a host computing device to the source and the destination to copy data from the source to the destination when the source and the destination belong to one of a different storage array and storage cluster and when the source and the destination support the direct data transfer mechanisms, and the copy process may be executed on the host device to copy data from the source to the destination when one of the source and the destination does not support the direct data transfer mechanisms.

Abstract: Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.