Abstract: A battery pack including a first charging contactor and a second charging contactor; a first measurement resistor, a second measurement resistor and a third measurement resistor electrically connected to at least two of one ends and the other ends of the first charging contactor and the second charging contactor; a first measurement contactor, a second measurement contactor and a third measurement contactor electrically connected to at least one of the first measurement resistor, the second measurement resistor and the third measurement resistor; and a control unit configured to control an operation state of at least one of the first measurement contactor, the second measurement contactor and the third measurement contactor based on whether at least one of a charging start request signal and a charging end request signal is received.

Abstract: The present invention is a process by which an engineer can provide as input the design, functional verification goals, and other abstract design details, and receive as output an agent which can be integrated into traditional test benches and will generate stimuli to automatically hit the functional coverage goals for the design. The present invention may employ a system which includes a learning configurator, a pre-trained learning test generator, and a test bench. The pre-trained learning test generator is communicatively coupled to the generator and notably comprises a learning algorithm.

Abstract: Charging equipment of a vehicle charging system comprises an information indicator configured to indicate authentication information, and an authentication device configured to perform authentication using the authentication information. A vehicle of the vehicle charging system comprises an imaging device, and a communication device configured to send the authentication information acquired by the imaging device to the authentication device. The authentication device of the charging equipment is configured to perform the authentication using the authentication information received from the communication device, and is configured to, if the authentication has succeeded, permit the vehicle to use a wireless LAN.

Abstract: A power management circuit includes an electrical power input for receiving electrical power, a controller, a finite state machine circuit in communication with the controller and a first voltage regulator in communication with the controller and the electrical power input and having a first output connected to a first capacitor for storing electrical power and to first electrical circuitry. The controller is configured to cyclically enable the first voltage regulator to supply current to charge the first capacitor. The finite state machine circuit is configured to interact with the controller to control the duration of a first time period of a cycle over which the first voltage regulator supplies current to charge the first capacitor and to control the duration of a second time period of the cycle over which the first voltage regulator does not supply current to charge the first capacitor and during which electrical current is receivable by said first electrical circuitry from said first capacitor.

Abstract: A charging apparatus includes a plurality of batteries, a changeover relay that can be changed over between a first state where the plurality of the batteries are connected in series to one another and a second state where the plurality of the batteries are connected in parallel to one another, an electric storage device, a main relay that is provided between the electric storage device and an electric load of a vehicle, and a control device that controls the opening/closing of the changeover relay. The control device renders the changeover relay in the first state when the main relay is in an open state.

Abstract: A control unit for a battery system includes a plurality of battery cells is provided. The control unit includes: an input node configured to receive a sensor signal indicative of a state of at least one of the plurality of battery cells; a microcontroller connected to the input node and configured to generate a first control signal based on the sensor signal; and a switch control circuit configured to control a power switch of the battery system by: receiving the sensor signal, the first control signal, and a fault signal indicative of an operational state of the microcontroller; generating a second control signal based on the sensor signal; and transmitting one of the first control signal and the second control signal to an output node of the control unit based on the received fault signal.

Abstract: A method of manufacturing a lithographic mask includes performing optical proximity correction (OPC) for correcting an optical proximity effect (OPE) on a design layout, and forming a lithographic mask based on the design layout corrected by performing the OPC, wherein performing the OPC includes generating a plurality of segments. and adjusting a bias of the plurality of segments, and the plurality of dissection positions include global uniform dissection positions defined for each third length based on a global coordinate system that is a coordinate system of the whole design layout.

Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.

Abstract: A battery discharge controller configured to control a hybrid system having first and second batteries includes a charged electric charge amount calculating section and a discharge controlling section. The discharge controlling section controls the DC/DC converter such that the first battery and the second battery are both discharged when a first reserve electric charge amount, which is a value obtained by subtracting a predetermined first lower limit electric charge amount from the charged electric charge amount of the first battery, has a positive value, a second reserve electric charge amount, which is a value obtained by subtracting a predetermined second lower limit electric charge amount from the charged electric charge amount of the second battery, has a positive value, and an absolute value of a difference between the first reserve electric charge amount and the second reserve electric charge amount is less than a predetermined threshold.

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

Abstract: Implementations described herein generally relate to improving silicon wafer manufacturing. In one implementation, a method includes receiving data from one or more manufacturing tools about a manufacturing process of a silicon wafer. The method further includes determining, based on the data, predictive information about a quality of the silicon wafer. The method further includes providing the predictive information to a manufacturing system, wherein the predictive information is used to determine whether to take corrective action.

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

Abstract: A carrier, such as a battery, that queries a memory of a charger or charging circuit, or the memory of equipment or discharging circuit powered by the battery, to determine the relative date or version of data, operating parameters and/or software on both the battery and the equipment, and either provides updated data, operating parameters and/or software to the equipment, or retrieves later dated data, operating parameters and/or software from the equipment to update the memory of the battery and/or further distribute the updated data, operating parameter sand/or software to other batteries or equipment.

Abstract: An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.

Abstract: Embodiments of the present invention describe a hierarchical cortical emulation using a scratchpad memory device and a storage class memory device. The scratchpad memory device is partitioned into a first subset of memory locations and a second subset of memory locations. A processor from a neural network device is assigned a first memory portion from the first subset, a second memory portion from the second subset, and a third memory portion from the storage class memory device. Further the neural network device and a memory controller perform a compute cycle for a hierarchical level k, 1?k?n, n being total number of levels. A compute cycle includes performing, by the processor, computations from the level k using neuron data stored in the first memory portion, and in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.

Abstract: A field programmable gate array (FPGA) having at least first and second processing circuits implemented thereon. Each of the first and second processing circuits comprises a numerical core and associated peripheral components. The numerical core in the first processing circuit is dissimilar to the numerical core in the second processing circuit. The first and second processing circuits are segregated from each other in floorplan view.

Abstract: A power control circuit and a power control method are provided. The power control circuit includes a battery unit, a power controller and a switch circuit. The power controller is configured to provide a control signal. The switch circuit is coupled between the battery unit and the power controller. The switch circuit includes a diode component. The diode component is configured to receive the control signal. The switch circuit is configured to cut off a power transmission path of the battery unit in response to a voltage difference between a first terminal and a second terminal of the diode component.

Abstract: Provided are a circuit device, a control device, a power receiving device, an electronic device, and the like that realize measurement of a remaining battery amount and excessive discharge detection with low power consumption, and can reduce power consumption from a battery. The circuit device includes a measurement circuit that measures a battery voltage, an interface circuit that outputs battery voltage information to a processing device, and a control circuit. The measurement circuit has a counter, a resistance circuit that divides the battery voltage by a voltage division ratio set by a count value of the counter, and a comparator that compares an output voltage of the resistance circuit with a reference voltage. When power supply to the processing device is off, the counter sets the count value to a fixed value, and the control circuit performs battery protection control processing based on the comparison result of the comparator.

Abstract: A method includes generating on a host machine a validated verification test scenario comprising a graph defining a scheduled performance order of a plurality of actions to be performed on a DUT and a corresponding verification environment; obtaining a subset of one or more actions to be added to the validated scenario while maintaining the plurality of actions of the validated scenario and the scheduled performance order, forming an amended verification test scenario; and applying a runtime solver in a target language of the DUT and the corresponding verification environment on the amended verification test scenario to generate a test in a target code and to apply the test on the DUT and the corresponding verification environment wherein inclusion of any of said one or more actions or an order of performance of said one or more actions of the subset in the test is determined at runtime.

Abstract: A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.