Patents Examined by Kathleen Duda
  • Patent number: 10768526
    Abstract: A substrate having a target material layer is provided. A first hard mask layer, a second hard mask layer, and a photoresist layer are formed on the target material layer. The photoresist layer is transferred into first patterns on the second hard mask layer. Regions of the second hard mask layer not protected by the first patterns are etched away, thereby forming second patterns. The first patterns are trimmed to form trimmed features. A conformal spacer material layer is deposited on the trimmed features, the second patterns, and the first hard mask. The spacer material layer is etched to form first spacers on sidewalls of the trimmed features, and second spacers on sidewalls of the second patterns. The trimmed features are removed. Regions of the second patterns not protected by the first spacers are removed, thereby forming patterns with a reduced, fine pitch.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kuo-Yao Chou
  • Patent number: 10747114
    Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a material layer on a substrate; forming a blocking layer on the material layer, wherein a bottom portion of the blocking layer reacts with the material layer, resulting in a capping layer that seals the material layer from an upper portion of the blocking layer. The method further includes forming a photoresist layer on the blocking layer; exposing the photoresist layer; and developing the photoresist layer, resulting in a patterned photoresist layer.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Siao-Shan Wang, Chen-Yu Liu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10732506
    Abstract: Provided is a method of fabricating an integrated circuit device, the method including: forming, on a substrate, a developable bottom anti-reflective coating (DBARC) layer including a chemically amplified polymer; forming, on the DBARC layer, a photoresist layer including a non-chemically amplified resin and a photoacid generator (PAG); generating an acid from the PAG in a first region selected from the photoresist layer, by exposing the first region; diffusing the acid in the exposed first region into a first DBARC region of the DBARC layer, the first DBARC region facing the first region; and removing the first region and the first DBARC region by developing the photoresist layer and the DBARC layer.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-koo Hong, Jeong-ho Mun, Jin-joo Kim, Gum-hye Jeon
  • Patent number: 10734436
    Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
  • Patent number: 10712664
    Abstract: The present invention provides a process and a structure of forming conductive vias using a light guide. In an exemplary embodiment, the process includes providing a via in a base material in a direction perpendicular to a plane of the base material, applying a photoresist layer to an interior surface of the via, inserting a light guide into the via, exposing, by the light guide, a portion of the photoresist layer to light, thereby resulting in an exposed portion of the photoresist layer and an unexposed portion of the photoresist layer, removing a portion of the photoresist layer, and plating an area of the via, where the photoresist has been removed, with a metal, thereby resulting in a portion of the via plated with metal and a portion of the via not plated with metal.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Gerald Bartley, Matthew Doyle, Darryl Becker, Mark Jeanson
  • Patent number: 10691013
    Abstract: An EUV lithography system and method of manufacturing thereof includes: an EUV light source; a chuck being thermally conducting and smooth having a surface with a predetermined chuck flatness; and a reflective lens system for directing EUV light from the EUV light source over the surface of the chuck.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 23, 2020
    Assignee: Applied Materials, Inc.
    Inventor: Majeed A. Foad
  • Patent number: 10691023
    Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hui Weng, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10684549
    Abstract: Pattern-formation methods comprise: (a) providing a substrate; (b) forming a photoresist pattern over the substrate; (c) applying a pattern treatment composition to the photoresist pattern, the pattern treatment composition comprising a solvent mixture comprising a first organic solvent and a second organic solvent, wherein the first organic solvent has a boiling point that is greater than a boiling point of the second organic solvent, and wherein the first organic solvent has a boiling point of 210° C. or more; and (d) thereafter heating the photoresist pattern. The methods find particular applicability in the manufacture of semiconductor devices.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 16, 2020
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Kevin Rowell, Cong Liu, Cheng Bai Xu, Irvinder Kaur, Xisen Hou, Mingqi Li
  • Patent number: 10678135
    Abstract: A surface treatment composition and methods for improving adhesion of an organic layer on a titanium-containing hardmask includes forming a self-assembled monolayer on a surface of the titanium-containing hardmask prior to depositing the organic layer. The self-assembled monolayer is formed from a blend of alkyl phosphonic acids of formula (I): X(CH2)nPOOH2 (I), wherein n is 6 to 16 and X is either CH3 or COOH, wherein a ratio of the methyl terminated (CH3) alkyl phosphonic acid to the carboxyl terminated (COOH) alkyl phosphonic acid ranges from 25:75 to 75:25.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Dario Goldfarb, Indira Seshadri
  • Patent number: 10670967
    Abstract: A resist patterning method according to the present invention includes: a resist layer forming step S101 of forming a resist layer (12) on a substrate (11); an activating step S103 of activating the resist layer by irradiation with an activating energy beam; a decay inhibiting step S105 of inhibiting decay of the activity of the resist layer; a latent pattern image forming step S107 of forming a latent pattern image in the activated resist layer by irradiation with a latent image forming energy beam; and a developing step S110 of developing the resist layer.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: June 2, 2020
    Assignee: OSAKA UNIVERSITY
    Inventors: Seiichi Tagawa, Akihiro Oshima
  • Patent number: 10663859
    Abstract: A method of forming a photonic device structure comprises forming a photoresist over a photonic material over a substrate. The photoresist is exposed to radiation through a gray-tone mask to form at least one photoexposed region and at least one non-photoexposed region of the photoresist. The at least one photoexposed region of the photoresist or the at least one non-photoexposed region of the photoresist is removed to form photoresist features. The photoresist features and unprotected portions of the photonic material are removed to form photonic features. Other methods of forming a photonic device structure, and a method of forming an electronic device are also described.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Meade, Gurtej S. Sandhu
  • Patent number: 10656527
    Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Indira Seshadri, Jing Guo, Ashim Dutta, Nelson Felix
  • Patent number: 10653011
    Abstract: A method for manufacturing the circuit board comprises following steps of providing an insulating substrate, and defining at least one through-hole on the insulating substrate to extending through two opposite surfaces of the insulating substrate; forming a silver layer on each of the two opposite surfaces, and forming a silver conductive structure in each through-hole connecting the silver layers; forming a copper wiring layer on the silver layers to cover each silver conductive structure and a portion region of the silver layers; and etching the silver layers to form a silver wiring layer corresponding to the copper wiring layer, wherein a first etching liquid, which does not etch the copper wiring layer, is used for etching the silver layers.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 12, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Xian-Qin Hu, Mei Yang, Jun Dai
  • Patent number: 10613438
    Abstract: Lithographic patterning methods are provided which implement directed self-assembly (DSA) of block copolymers to enable self-aligned cutting of features. A first layer and second layer of material are formed on a substrate. The second layer of material is lithographically patterning to form a guiding pattern. A DSA process is performed to form a block copolymer pattern around the guiding pattern, which comprises a repeating block chain that includes at least a first block material and a second block material, which have etch selectivity with respect to each other. A selective etch process is performed to selectively etching one of the first block material and the second block material to form self-aligned openings in the block copolymer pattern which expose portions of the first layer of material. The first layer of material is patterned by etching the exposed portions of the first layer of material.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Burns, Sivananda K Kanakasabapathy, Kafai Lai, Chi-Chun Liu, Kristin Schmidt, Ankit Vora
  • Patent number: 10606167
    Abstract: A photolithography mask plate, the photolithography mask plate including: a substrate; a carbon nanotube composite structure on a surface of the substrate, wherein the carbon nanotube composite structure comprises a carbon nanotube layer and a chrome layer coated on the carbon nanotube layer; a cover layer on the carbon nanotube composite structure.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 31, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Mo Chen, Qun-Qing Li, Li-Hui Zhang, Yuan-Hao Jin, Dong An, Shou-Shan Fan
  • Patent number: 10606176
    Abstract: Techniques disclosed herein provide a method for continued patterning of substrates having sub-resolution features. Techniques include using novel deposition and removal techniques. This results in a substrate with inter-digitated photoresist in which photoresist is positioned between structures on a given substrate. Combined with using extreme ultraviolet lithographic exposure, patterning techniques herein can make desired cuts and blocks at specified locations on the substrate.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 31, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 10606175
    Abstract: The present specification relates to a manufacturing method of a circuit board. More particularly, the present specification relates to a circuit board and a manufacturing method of an electronic device including the same.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: March 31, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Yong Goo Son, Seung Heon Lee, Han Min Seo, Chang Yoon Lim, Ji Eun Myung, Kiseok Lee
  • Patent number: 10578960
    Abstract: A mask blank with resist film, including a substrate having a thin film; and a negative resist film formed on a main surface of the thin film, wherein in the resist film, a photoacid generator-rich region in which concentration of a photoacid generator is high compared to other region of the resist film, is formed at a portion where the resist film is in contact with the thin film.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: March 3, 2020
    Assignee: HOYA CORPORATION
    Inventor: Toru Fukui
  • Patent number: 10578968
    Abstract: The present invention has an object to provide a pattern forming method capable of providing good DOF and EL, a resist pattern formed by the pattern forming method, and a method for manufacturing an electronic device, including the pattern forming method. The pattern forming method of the present invention includes a step a of coating an active-light-sensitive or radiation-sensitive resin composition onto a substrate to form a resist film, a step b of coating a composition for forming an upper layer film onto the resist film to form an upper layer film on the resist film, a step c of exposing the resist film having the upper layer film formed thereon, and a step d of developing the exposed resist film using a developer to form a pattern, in which the active-light-sensitive or radiation-sensitive resin composition contains a hydrophobic resin.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: March 3, 2020
    Assignee: FUJIFILM Corporation
    Inventors: Kei Yamamoto, Naohiro Tango, Naoki Inoue, Michihiro Shirakawa, Akiyoshi Goto
  • Patent number: 10571798
    Abstract: A photolithography mask plate, the photolithography mask plate including: a substrate; a carbon nanotube layer located on the substrate; a patterned chrome layer located on the carbon nanotube layer, wherein the patterned chrome layer and the carbon nanotube layer have the same pattern; a cover layer located on the patterned chrome layer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 25, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Mo Chen, Qun-Qing Li, Li-Hui Zhang, Yuan-Hao Jin, Dong An, Shou-Shan Fan