Abstract: A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. In one embodiment the method includes the step of: estimating a test escape rate for a set of fault tests to be performed on an IC under design based on an estimated yield and a combined coverage of the set of fault tests; the combined coverage accounting for overlapping coverage among the set of fault tests.

Abstract: A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block.

Abstract: A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.

Abstract: A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value.

Abstract: A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples.

Abstract: Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base functions that include two-input threshold OR functions and two-input threshold AND functions with hysteresis, and complex base functions generated during the decomposing; partitioning the network of base functions into at least one subject graph, each portion of the at least one subject graph having a function; determining matches between the at least one subject graph and one or more pattern graphs; and selecting at least one of the one or more pattern graphs to be used in the bound network for the function of each of different portions of the at least one subject graph.

Abstract: An integrated circuit implementation methodology uses mutable cells, e.g. cells that are capable of being personalized for use as one of a plurality of resource types. For example, a mutable cell is designed to have a component layout and a set of lower-layer internal connections compatible with both a design of a flip-flop, and a design of a pair of multiplexers. Independent customizations of the mutable cell, using higher layers of interconnect, efficiently use the cell as a flip-flop or as a pair of multiplexers. Use of mutable cells in an integrated circuit advantageously enables a set of predefined lower-layer photomask, such as for a predefined base array, to be efficiently shared among different applications. In some embodiments, a Simultaneous Dynamical Integration (SDI) Electronic Design Automation (EDA) flow advantageously uses mutable cells, such as to balance demand for resources against supply thereof.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: Disclosed is a method including a step for selecting a component, a step for preparing a timing database including terminal information, input/output attribute and AC specifications of the component selected, a step for creating a circuit diagram from circuit design information, a step for extracting connection information and performing timing verification, when component connection has been determined, a step for performing layout design including the placement and routing of the components, a step for extracting wiring lengths of a data line and a clock line for the components from a net list and the layout information to derive the wiring delay time of the data and clock lines, a step for checking, from the wiring delay time derived, whether or not a timing constraint for the component is met.

Abstract: An apparatus, method, and program for designing a semiconductor device having a storage unit configured to a differential signal library for use in generation of a design data of a differential signal cell that receives or outputs differential signals. The apparatus includes a logic synthesis unit performing logic synthesis based on the differential signal library configured to the storage unit. The apparatus generates a netlist design data of the differential signal cell that receives or outputs the differential signals.

Abstract: A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

Abstract: An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block selectable by a designer to include in the block based schematic to represent a component in the design that filters data. The EDA tool includes a design adjustment unit to automatically modify previously programmed and selected components and wires in the block based schematic without input from the designer upon determining a change made to the parameterizable filter block by the designer.

Abstract: A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served.

Abstract: Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of memory units; and a reset information propagation logic coupled to the resettable memory cells and the memory units. The reset information propagation logic is to write reset information into a portion of the memory units when one of the resettable memory cells has a reset value and one of the memory units is written into. Alternatively, a resettable memory may include: a memory unit; a resettable finite state machine to change state in response to write request to the memory unit; and a selector coupled to the finite state machine and the memory unit to select one from a reset value and an output from the memory unit based on at least a state of the finite state machine.

Abstract: Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams for a circuit design is disclosed. The method comprises analyzing a plurality of implementations for the circuit design; determining minimum timing constraints based upon all of the implementations for the circuit design; generating a representative implementation, based upon the plurality of implementations, which meets the determined minimum timing constraints for all of the implementations of the circuit design; and outputting the representative implementation.

Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.

Abstract: A method and apparatus for executing multithreaded algorithm to provide static timing analysis of a chip design includes analyzing a chip design to identify various components and nodes associated with the components. A node tree is built with a plurality of nodes. The node tree identifies groups of nodes that are available in different levels. A size of node grouping for a current level is determined by looking up the node tree. Testing data for parallel processing of different size of node groupings using varied thread counts is compiled. An optimum thread count for the current level based on the size of node grouping in the node tree is identified from compiled testing data. Dynamic parallel processing of nodes in the current level is performed using the number of threads identified by the optimum thread count. An acceptable design of the chip is determined by the dynamic parallel processing.

Abstract: A hardware accelerator factors functions during the compilation of a user design. The hardware accelerator includes cofactor units, each adapted to determine a cofactor of a function in response to a specified factorization and a set of input values. The factorization specifies the constant function inputs and varying function inputs. Each cofactor unit determines the cofactor of the function in response to a different constant value. The hardware accelerator operates all of the cofactor units simultaneously to determine some or all of the cofactors of a function for a factorization in parallel. Signature generators determine attributes of the cofactors. A signature analyzer uses these attributes to identify identical cofactors, constant cofactors, and inverse cofactors. The signature analyzer returns potentially optimal factorizations to compilation software applications for possible incorporation into user designs.

Abstract: A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the referenc

Abstract: Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (var,zt) using a mask transmittance function, a plurality of illumination system modes, and a plurality of preselected basis spatial functions independent of (var,zt). Subsequently, for each of many different (var,zt) combinations, expansion coefficients are computed for which the preselected basis spatial functions, when weighted by those expansion coefficients, characterize a point response of a projection-processing system determined for that (var,zt) combination. The resultant intensity for that (var,zt) combination is then computed as a sum of the partial intensity functions weighted according to corresponding products of those expansion coefficients.