Abstract: The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization.

Abstract: A method for modifying an integrated circuit design layout is presented and can include placing a plurality of target points in the proximity of a polygon representing a portion of the integrated circuit design; modifying the target point placement for some or all of the placed target points; fitting a curve to the target points; and redefining the portion of the integrated circuit as a contour defined by the fitted curve to modify the design layout. In some applications the modified design layout can be used as a target for an optical proximity correction algorithm or for other purposes.

Abstract: A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.

Abstract: The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity effects in a proximity correction process. A second set of data is accessed comprising information about second device features, wherein at least a portion of the second set of data is relevant to the proximity correction process. The second set of data is manipulated so as to improve the proximity correction process, as compared with the same proximity correction process in which the second set of data was included in the mask pattern database without being manipulated. At least a portion of the mask pattern data and at least a portion of the manipulated second set of data is included in the mask pattern database.

Abstract: A method of more efficiently, easily and cost-effectively analyzing the performance of a device model is disclosed. Embodiments enable automated generation of theoretical performance analysis for a device model based upon a workload associated with rendering graphical data and a configuration of the device model. The workload may be independent of design configuration, thereby enabling determination of the workload without simulating the device model. Additionally, the design configuration may be updated or changed without re-determining the workload. Accordingly, the graphical data may comprise a general or random test which is relatively large in size and covers a relatively large operational scope of the design. Additionally, the workload may comprise graphical information determined based upon the graphical data. Further, the theoretical performance analysis may indicate a graphics pipeline unit of the device model causing a bottleneck in a graphics pipeline of the device model.

Abstract: System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.

Abstract: A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a large library, but are applicable for the targeted brick libraries which typically contain a small number of complex cells, along with a much smaller number of simple cells. This invention is modular such that it can be applied in the context of incremental netlist optimization as well as optimization during physical synthesis.

Abstract: Shielded clock wiring used in an integrated circuit is designed by storing a table of identifiers of shielded clock wiring usable in the integrated circuit, storing dividing rule information in correspondence with each identifier, describing a way of dividing the shielded clock wiring indicated by the each identifier; inputting a wiring layer of a shielded clock wiring of a wiring request, inputting an identifier of the shielded clock wiring of the wiring request and inputting a starting point and an end point of the shielded clock wiring of the wiring request; specifying a dividing rule of the shielded clock wiring indicated by the identifier; and judging whether to permit the shielded clock wiring of the wiring request, by judging whether shielded clock wiring resulting from division based on the dividing rule is spatially permissible.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A method for checking a length of a wire path between a capacitor and a via of the PCB design obtains length criteria and information on capacitors from a database, selects one or more capacitors and pins of the selected capacitors from the obtained information on capacitors and selects one of the length criteria, and obtains positions of selected capacitors and positions of vias corresponding to the positions of selected capacitors from the database. The method further calculates each length of a wire path between a selected capacitor and a corresponding via according to the position of the capacitor and the position of the via, determines whether each calculated length of a wire path between a selected capacitor and a corresponding via is acceptable according to a comparison with the selected length criterion, and outputs check results of the determining step.

Abstract: Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.

Abstract: Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert signal transition features into an effective fanout to provide estimates of gate delay dependencies on input slope and gate logic topology.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.

Abstract: A lithographic mask is illuminated with light from different directions such that intensities of a plurality of incident beams of light provide a largest possible integrated process window defined in terms of an allowed range for defining shapes. Constrained sets of intensity parameters are imposed. A first set of intensity parameters represents maximum possible intensities that can be permitted for overexposed tolerance positions. A second set of intensity parameters represents minimum possible intensities that can be permitted for underexposed tolerance positions. Optimum source intensities of incident beams are defined using a linear program and constraints. The optimum source intensities maximize an integrated range of dose and focal variations without causing printed shapes to depart from the allowed range. Apparatus are detailed and variations are described.

Abstract: Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found.

Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.

Abstract: The present invention relates to a method for finding design weakness and potential field failure of a PCB assembly which includes components, comprising the steps of: (a) creating a model of the PCB assembly by which natural frequencies and mode shapes of the PCB assembly can be determined; (b) performing a natural frequencies simulation for determining natural frequencies and mode shapes of the PCB assembly; and (c) analyzing said determined natural frequencies and mode shapes and identifying local dominant oscillations of components, components identified as having a local dominant oscillation in at least one of said determined mode shapes are identified as components having a relatively high potential of field failure.

Abstract: Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.