Abstract: A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor circuits, logic diagrams, or any combination thereof, and generating the planar double gate transistor layout at least in part from the single gate transistor layout. The method is highly flexible regarding the generation and adjusting of gate shapes and gate contact shapes to ensure the proper connection of the gates to voltage or signal lines, and when such generation, adjusting, or any combination thereof is performed. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Abstract: Multiple users simultaneously edit at least a portion of a printed circuit board (PCB) design. The PCB design portion is transmitted to first and second clients for graphical display at each of the clients. A first protection boundary is associated with an area of the PCB design being edited at the first client. A second protection boundary is associated with an area of the PCB design being edited at the second client. The first and second protection boundaries are displayed at each of the first and second clients. A request from one of the clients to edit an object within a region bounded by a protection boundary associated with the other client is rejected. The protection boundary may surround a user's cursor. The size of the boundary may increase based on editing activity by a user in an area of a PCB design.

Abstract: A symmetrical circuit layout structure includes a number of signal wires, a ground wire and a dielectric layer. The signal wires include a first portion placed on a first plane and a second portion placed on a second plane. The ground wire includes a first portion placed above the first portion of the signal wires and adjacent to the second portion of the signal wires, and a second portion placed below the second portion of the signal wires and adjacent to the first portion of the signal wires. The dielectric layer is placed between the first plane and the second plane.

Abstract: There is provided an integrated circuit layout design method capable of performing LVS verification in an early stage of layout design. Placement and routing means provides wiring and outputs a layout in which short circuits are possibly left uncorrected. Short-circuit correcting means performs rewiring by using a newly defined tentative wiring layer in which short-circuit wiring portions are removed and outputs an inter-layer method for interconnecting the tentative wiring layer and the original wiring layer to an inter-layer connection information file. Layout verification means uses the corrected layout and an LVS rule file in which the inter-layer connection method is reflected to perform LVS on the layout in which the short circuit portions are modified to correct connections through use of the tentative wiring layer.

Abstract: A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of logic blocks each of which is constituted by a first logic circuit and a second logic circuit. Such semiconductor integrated circuit is designed in at least two steps: a first design step in which designing layout and timing verification are performed for a logic circuit including signal lines between the logic blocks and the first logic circuit; and a second design step in which layout and timing verification are performed for the second logic circuit in each logic block independently.

Abstract: An improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and improve the layout productivity is disclosed. In some disclosed approaches, automated interactive aids and batch tools are provided which can assist in optimizing the final layouts for yield at the initial placement and/or routing stages for optimizing yield. Provided in some disclosed approaches are automated capability to layout designers at the mos devices level to configure mos devices as per different DFY recommendations from the foundry without negative effects on the overall chip area (or cell size). The design rules may be relaxed selectively on an instance basis and wherever possible or desirable.

Abstract: A system for accelerating circuit measurements includes a circuit. A signal is applied to the circuit. A set of measurements is taken of a response of the circuit to the applied signal. The system includes a circuit model. The circuit model is a representation of the circuit. A final value of the response of the circuit is determined utilizing the circuit model in accordance with the set of measurements. A stimulus signal is generated in accordance with the final value for driving the circuit model to the final value. The system includes a stimulus generator in communication with the circuit. The stimulus generator is configured to apply the stimulus signal to the circuit. The stimulus signal is configured to accelerate the response of the circuit to reach the final value.

Abstract: In one embodiment, a method for constructing an application includes presenting to a user a list of possible elements for a logic expression. The possible elements may include one or more names of variables. The method further includes receiving a user selection of one or more elements from the list of possible elements, presenting the selected elements as part of the logic expression, and allowing the user to complete the logic expression using the selected elements and at least one logical operator.

Abstract: A method and system is proposed for determining the required quantity of testing points on a circuit layout diagram generated by a computer-aided circuit layout design program on a computer platform. The proposed method and system is characterized by the use of a graphic file scanning method for finding and totaling the number of all the electrical connecting points associated with each electronic component in the circuit layout diagram, whereby the required quantity of testing points is determined based on the total of the electrical connecting points. The determined quantity of testing points is then informed to the user by displaying it in a human-readable form on the computer platform. This feature allows circuit layout design to be less laborious and time-consuming and thus more efficient than prior art.

Abstract: This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (M1s) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.

Abstract: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.

Abstract: Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising the design points, determining a representative design point from the clusters comprising the design points, running a statistical simulation to determine a yield of the design using the representative design point and a statistical model of manufacturing process variations, generating statistical corners in accordance with results of the statistical simulation, and optimizing the design in accordance with the statistical corners using an iterative process.

Abstract: A method of decomposing a target pattern having features to be imaged on a substrate so as to allow said features to be imaged in a multi-exposure process. The method includes the steps of: (a) segmenting a plurality of the features into a plurality of polygons; (b) determining the image log slope (ILS) value for each of the plurality of polygons; (c) determining the polygon having the minimum ILS value, and defining a mask containing the polygon; (d) convolving the mask defined in step (c) with an eigen function of a transmission cross coefficient so as to generate an interference map, where the transmission cross coefficient defines the illumination system to be utilized to image the target pattern; and (e) assigning a phase to the polygon based on the value of the interference map at a location corresponding to the polygon, where the phase defines which exposure in said multi-exposure process the polygon is assigned.

Abstract: Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.

Abstract: A method and system are provided for optimizing physical implementation of an electronic circuit responsive to simulation analysis thereof. The method and system include schematically defining the electronic circuit to include a plurality of circuit elements interconnected at respective nodes by a plurality of nets, and acquiring parametric values for a plurality of predetermined operational parameters from simulated operation of the electronic circuit. The parametric values are automatically processed to generate a plurality of parametric constraints corresponding thereto for optimizing physical implementation of the electronic circuit. A circuit layout at least partially representing a physical implementation of the schematic definition is then generated. The circuit layout, which includes a plurality of devices interconnected by a plurality of tracks, is adaptively configured in accordance with the parametric constraints.

Abstract: A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation data from a prior implementation flow for the circuit design can be associated with corresponding partitions. Selected portions of the implementation data from the prior implementation flow for at least one partition can be re-used during an incremental flow of the circuit design.

Abstract: Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.

Abstract: A method of designing an integrated circuit for an application having standards having a plurality of primitives, each of the primitives having a corresponding response. The method includes generating a macros description of each of the primitives and the response corresponding to each of the primitives, wherein the macros description includes information relating to a number of first fields for each of the primitives and a number of second fields for the response corresponding to each of the primitives. The method further includes receiving a specification of the behavior of the integrated circuit in response to the primitives that has one or more values specified for each of the second fields, and generating a hardware description language representation for the integrated circuit based on the macros description and the specification. Also, a software tool which implements the method.

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and the first and third rectangular regions have the same first pattern configuration having a first pattern element, a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, and the second and fourth rectangular regions have the same second pattern configuration having a second pattern element, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein, the first pattern element is different from the second pattern element for allowing the second pattern configuration be chosen to align when the first pattern configurat