Abstract: A chip testing apparatus including a chip testing machine, a temperature testing device, and a lid is provided. The chip testing machine includes a substrate and a plurality of chip testing sockets. Each of the chip testing sockets is disposed on the substrate and configured to carry a chip under test. The temperature adjusting device is disposed on the chip testing machine, and the lid covers the temperature adjusting device and the chip testing sockets. The temperature adjusting device includes a main body and a plurality of pressing components. The main body includes a plurality of fluid channels, and each of the pressing components can press one side of one of the chips under test. A fluid can flow into one of the fluid channels and flow through the pressing components, so that the chips under test are in an environment having a predetermined temperature.

Abstract: A temperature adjusting device including a main body and a pressing component is provided. The main body includes a first main body thru-hole and a second main body thru-hole. The main body has a first fluid channel and a second fluid channel therein, the first fluid channel is in spatial communication with the first main body thru-hole, and the second fluid channel is in spatial communication with the second main body thru-hole. The pressing component partially protrudes from one side of the main body, the pressing component has a fluid accommodating slot therein that is in spatial communication with the first fluid channel and the second fluid channel. A fluid having a predetermined temperature can enter into the main body from the first main body thru-hole, enter into the fluid accommodating slot through the first fluid channel, and exit the main body through the second main body thru-hole.

Abstract: A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

Abstract: A measurement apparatus includes external terminals configured for connection to a device-under-test (DUT), the external terminals including first and second force terminals and first and second sense terminals. The measurement apparatus further includes a controller and a feedback loop configured in a current feedback mode to sense a current flowing from the first force terminal to the second force terminal, and in a voltage feedback mode to sense a voltage across the first and second sense terminals. The measurement apparatus further includes a measurement path configured to measure a least one of a voltage and current across a pair of the external terminals and to supply the measured at least one of the voltage and current to the controller.

Abstract: A test and measurement instrument for measuring a current in a device under test, comprising an input configured to receive signals from a magnetic field probe; and one or more processors configured to measure, from a signal from the magnetic field probe, a magnetic field generated by a current-carrying conductor of the device under test based on a known current, determine a calibration factor based on the known current and the magnetic field, and generate a calibrated measurement of an unknown current in the current-carrying conductor using a magnetic field generated by the current-carrying conductor based on the unknown current and the calibration factor.

Abstract: In some examples, a circuit may be configured to perform a method that includes performing a circuit function via a circuit function unit of a circuit, receiving sensor data from one or more sensors associated with the circuit function unit, and estimating a remaining life of the circuit based on an accelerated reliability model and the sensor data, wherein the sensor data comprises input to the accelerated reliability model. The circuit itself may include a dedicated circuit unit that estimates the remaining life of the circuit based on an accelerated reliability model and the sensor data, and the circuit may output one or more predictive alerts or predictive faults when the remaining life is below a threshold, which may prompt the system for predictive maintenance on the circuit.

Abstract: Provided is an immunity evaluation system that enables design feedback in consideration of a subject wiring and an improvement amount for improving an electromagnetic noise resistance of a circuit board. An immunity evaluation device includes: a storage unit configured to store characteristic data including probe-circuit board wiring coupling characteristics which are determined by a combination of a near-field probe and circuit board characteristics, and a test result; and an IC reaching signal level estimation unit configured to estimate a signal level reaching a terminal of an evaluation target IC. The immunity evaluation device receives board design information, information of the near-field probe, and test waveform instruction information of a signal applied to the near-field probe.

Abstract: A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns.

Abstract: An LCR meter with a fast balancing method, with only one necessary measurement of voltages. The LCR meter uses to speed up balancing, separation in time measurement of a device under test (DUT), and other parasitic impedances, including a leakage impedance. The leakage impedance and the other parasitic impedances of a fixture and the LCR meter itself are measured during open/short calibration and saved to memory. The DUT is measured during measurement using already known parasitic impedances. This allows calculating balancing conditions using only one measurement of voltages.

Abstract: A stand-alone active thermal interposer device for use in testing a system-in-package device under test (DUT), the active thermal interposer device includes a body layer having a first surface and a second surface, wherein the first surface is operable to be disposed adjacent to a cold plate, and a plurality of heating zones defined across a second surface of the body layer, the plurality of heating zones operable to be controlled by a thermal controller to selectively heat and maintain respective temperatures thereof, the plurality of heating zones operable to heat a plurality of areas of the DUT when the second surface of the body layer is disposed adjacent to an interface surface of the DUT during testing of the DUT.

Abstract: Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

Abstract: System and method for compensating for power loss due to a radio frequency (RF) signal probe mismatch in conductive RF signal testing of a RF data signal transceiver device under test (DUT). Sourcing the RF test signal with the RF vector signal transceiver at multiple test frequencies enables isolation of and compensation for power loss due to a mismatch between the RF signal probe and RF DUT connection based on predetermined losses of the RF signal path.

Abstract: An LCR meter to increase accuracy of balancing uses sub-balancing method, additional to analog balancing by trans-impedance amplifier (TIA). For this, the LCR meter, based on TIA, to correct analog auto-balancing, applies the inverted voltage equal to unbalanced voltage to noninverting input of the TIA. And only one measurement of voltages is needed for.

Abstract: A test handler comprising a primary rotary turret comprising pick heads for transporting electronic components, and a secondary rotary turret arranged and configured to receive electronic components directly or indirectly from the primary rotary turret, the secondary rotary turret including multiple separate test sectors having component carriers for carrying the electronic components received from the primary rotary turret, wherein the multiple test sectors are rotatably movable relative to one another. The test handler also comprises at least one testing device positioned along a periphery of the secondary rotary turret, wherein the component carriers of the respective test sectors are operative to convey the electronic components to a position of the at least one testing device for testing.

Abstract: A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.

Abstract: A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.

Abstract: A semiconductor device test apparatus for improving a loss rate of a test signal in testing a device under test is provided. The semiconductor device test apparatus includes a probe interface board, a pogo block disposed on the probe interface board and electrically connected to a device under test, an equipment board disposed under the probe interface board, an alternating current (AC) controller, transferring and receiving an AC signal for performing an AC test on at least one of the device under test and the pogo block, being mounted on the equipment board, and a physical layer equalizing (PLE) board disposed between the probe interface board and the equipment board, a first equalizing circuit, decreasing loss of the AC signal, being mounted on the PLE board.

Abstract: The present invention provides a multi ground line disconnection inspection device as a device for inspecting whether a plurality of ground lines that are connected to a ground node of an electronic control device are disconnected, including a plurality of test lines having one end connected to a plurality of ground lines, respectively, a plurality of connection switches connected to the ground node and the other end of a plurality of test lines, respectively, a plurality of test power supplies for applying test voltages to a plurality of test nodes respectively positioned on a plurality of test lines, respectively, and a determination unit for determining whether a plurality of ground lines are disconnected by detecting voltages of a plurality of test nodes.

Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Abstract: A system includes a platform and a contactor. The platform has a side configured to support a frame with a carrier structure and electronic devices each having first and second sides and a terminal, the first side positioned on the carrier structure, and the terminal exposed in a first portion of the second side. The contactor has first and second sides, a contact and a heater. The contact is exposed on the first side of the contactor to contact the terminal in a first portion of the second side of a selected one of the electronic devices, and the heater is exposed on the first side of the contactor to apply heat to a second portion of the second side of the selected one of the electronic devices.