Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.

Abstract: In the cull pipe, positions of the vertices of a triangle have already been computed and these coordinates may be exploited by taking and sorting triangle groups based on these coordinates. As one example, all the triangles in a tile may constitute a group. The triangle groups are sorted into bins. Within each bin the triangles are sorted based on their depths.

Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle lies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.

Abstract: Techniques related to coding data including techniques for coding data using a universal codec are generally described. In some examples, such techniques may provide a universal (or unified) codec parameterized using a small set of parameters, which may be used to adapt the codec to different types of data to be compressed.

Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.

Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.

Abstract: It is presented a method for improving performance of generation of digitally represented graphics. Said method comprises the steps of: selecting (440) a tile comprising fragments to process; executing (452) a culling program for the tile, the culling program being replaceable; and executing a set of instructions, selected from a plurality of sets of instructions based on an output value of the culling program, for each of a plurality of subsets of the fragments. A corresponding display adapter and computer program product are also presented.

Abstract: An analysis of the cost of processing tiles may be used to decide how to process the tiles. In one case two tiles may be merged. In another case a culling algorithm may be selected based on tile processing cost.

Abstract: Color values may be compressed using a palette based encoder. Clusters of color values may be identified and encoded color values within the cluster with respect to a color value having a predefined characteristic. Clusters that have pixels or samples with constant color value may also be encoded.

Abstract: An apparatus and method for load balancing in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: an intersection unit engine to test a plurality of rays against a plurality of primitives to identify a closest primitive that each ray intersects; an intersection unit queue to store work to be performed by the intersection unit engine; and an intersection unit offload engine to monitor the intersection unit queue to determine a pressure level on the intersection unit engine, the intersection unit offload engine to responsively offload some of the work in the intersection unit queue to intersection program code executed on one or more execution units of the graphics processor.

Abstract: A mechanism is described for facilitating ray compression for efficient graphics data processing at computing devices. A method of embodiments, as described herein, includes forwarding a set of rays to a ray compression unit hosted by a graphics processor at a computing device, and facilitating the ray compression unit to compress the set of rays, wherein the set of rays are compressed into a compressed representation.

Abstract: An architecture for pixel shading, enables flexible control of shading rates and automatic shading reuse between triangles in tessellated primitives in some embodiments. The cost of pixel shading may then be decoupled from the geometric complexity. Wider use of tessellation and fine geometry may be made more feasible, even at very limited power budgets. Shading may be done over small local grids in parametric patch space, with reusing of shading for nearby samples. The decomposition of shaders into multiple parts is supported, which parts are shaded at different frequencies. Shading rates can be locally and adaptively controlled, in order to direct the computations to visually important areas and to provide performance scaling with a graceful degradation of quality. Another important benefit, in some embodiments, of shading in patch space is that it allows efficient rendering of distribution effects, which further closes the gap between real-time and offline rendering.

Abstract: An importance map indicates, for each of a plurality of pixels, whether the pixel is considered important enough to be rendered. A hierarchical tree for pixels is created to generate a hierarchical importance map. The hierarchical importance map may be used to stop traversal of a primitive that does not overlap a pixel indicated to be important.

Abstract: First, the colors are partitioned within a tile into distinct groups, such that the variation of color within each group is lowered. Second, each group can be encoded in an efficient manner. The algorithm described herein may give a higher compression ratio than previous algorithms, and therefore may further reduce memory bandwidth at a very low increase in computational cost in some embodiments. The algorithm may be added to a system with existing buffer compression algorithms, handling additional tiles that the existing algorithm fails to compress, thereby increasing the overall compression rate.

Abstract: Briefly, in accordance with one or more embodiments, an architecture to load balance tessellation distribution apparatus comprises a memory to store one or more patches representing an object in an image, and a processor, coupled to the memory, to perform one or more tessellation operations on the one or more patches. The one or more tessellation operations including splitting one or more of the patches into one or more subpatches, and load balancing the one or more patches and the one or more subpatches among two or more geometry and setup fixed-function pipelines (GSPs).

Abstract: Methods and apparatus relating to techniques for varying image quality rendering in a sort middle architecture. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to divide a display into a plurality of sections, assign a plurality of image quality parameters to the plurality of sections, and render images in each of the plurality of sections at a quality level determined at least in part by the image quality parameter assigned to each of the plurality of sections, wherein the plurality of image quality parameters assigned to the plurality of sections vary. Other embodiments are also disclosed and claimed.

Abstract: A mechanism is described for facilitating ray compression for efficient graphics data processing at computing devices. A method of embodiments, as described herein, includes forwarding a set of rays to a ray compression unit hosted by a graphics processor at a computing device, and facilitating the ray compression unit to compress the set of rays, wherein the set of rays are compressed into a compressed representation.

Abstract: A palette compressed representation may be stored in the index bits, when that is possible. The savings are considerable in some embodiments. In uncompressed mode, the data uses 2304 (2048+256) bits, and in compressed mode, the data uses 1280 bits. However, with this technique, the data only uses the index bits, (e.g. 256 bits) with a 5:1 compression improvement over the already compressed representation, and with respect to the uncompressed representation it is a 9:1 compression ratio.

Abstract: Cache thrashing or over-accessing of a cache can be reduced by reversing the order of traversal of a triangle on different granularities. In the case where triangles are not grouped, the traverse order may be reversed on each triangle. In cases where triangles are grouped, the traversal order may be reversed with each group change. However, when motion is excessive, for example beyond a threshold, then the traversal order reversal may be disabled.

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.