Abstract: A chip test system including a probe card, a chip tray and a cover plate fastened on the chip tray. The chip tray comprises a socket, a chip contact area, an extension contact area, and an alignment contact point. The socket loads the testing chip and is customized for the tested chip. The chip contact area has a plurality of chip contact points to electrically contact the chip. The extension contact area has a plurality of extension contact points corresponding to the chip contact points to direct test signals into the chip and direct feedback signals out of the chip. The alignment point provides an alignment location for the probe card during the chip test.

Abstract: An improved electronic component handler and associated improved test plate are shown. A guide on the test plate is used to intersect the testing apertures to eliminate misalignment of the component loading frame and the aperture to ensure easy insertion of components into the test apertures.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

Abstract: A method, system, and apparatus for a radio frequency identification (RFID) tag inlay tester and sorter system are described. A tag inlay is received. A characteristic of the tag inlay is tested. The tag inlay is disposed if the tag inlay is determined to fail the test of characteristic. The tag inlay is transported to a processing station if the tag inlay is determined to have passed the test of characteristic. The tag inlay is processed at the processing station. In an aspect, the tag inlay testing and tag inlay processing is performed in a single apparatus. In an alternative aspect, the tag inlay testing is performed by a first apparatus, and the tag inlay processing is performed by a second apparatus.

Abstract: A sorting system is provided for electronic components such as LED devices which includes a testing station for testing and determining a characteristic of each electronic component. A first tray has a plurality of receptacles for receiving tested electronic components and a second tray has more receptacles than the first tray for receiving tested electronic components. Electronic components comprising tested characteristics that occur with greater frequency are loaded into the receptacles of the first tray and electronic components comprising tested characteristics that occur with lower frequency are loaded into the receptacles of the second tray.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

Abstract: At least one venturi generator is provided for use with an electrical circuit component handler. The handler includes a stationary vacuum plate and a test plate. The vacuum plate includes vacuum channels, and the test plate includes test seats. The venturi generator is operative to create a vacuum pressure passed to the vacuum channels on the stationary vacuum plate and is used to draw electronic components into test seats on the test plate. The venturi generator may be the exclusive source of vacuum pressure or may supplement another vacuum source.

Abstract: A gap set device for an electronic component handler is provided. The electronic component handler includes a linear bearing having a test accessory mounted to it. The test accessory is movable between a first position away from a tool and a second position closer to the tool. A setting post is extendable from the test accessory such that when the test accessory moves from the first position to the second position the setting post can fix a gap between the test accessory and the tool.

Abstract: A handling device for electronic chip components includes an indexing table having a plurality of cavities for holding electronic chip components therein and a circulatory feeder for supplying the electronic chip components to the indexing table. One or more cavities are simultaneously disposed at a location which comes close to the circulatory feeder and, by performing a suction operation in the cavities, the electronic chip components are directly put into the cavities, without moving the electronic chip components along the main surface of the indexing table.

Abstract: Provided is a carrier module for use in a handler for handling a packaged chip for a test, the carrier module including a body provided, a base plate where the packaged chips are placed, provided to the body, and at least one latch which holds the packaged chips in position in the base plate.

Abstract: A multifunctional handler system for electrical testing of semiconductor devices is provided. The multifunctional handler system comprises: (1) a semiconductor device processing section comprising a loading unit including a buffer, a sorting unit including a separate marking machine, and a unloading unit; (2) a semiconductor device testing section, separate from the semiconductor device processing section, comprises a test chamber, the test chamber is separated into two or more test spaces, and the test spaces of the test chamber include a second chamber positioned at a lower position, a first chamber positioned above the second chamber, and pipelines for connecting the first and second chambers to each other; and (3) a host computer which is independently connected to the semiconductor device processing section and the semiconductor device testing section and controls tray information, test results, marking information, and test program information.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

Abstract: An apparatus for automatically displaying a grade of a liquid crystal display device and operating method thereof, includes a grade determining unit of a liquid crystal display panel; a grade inputting unit for inputting the grade of the liquid crystal display panel whose grade has been determined in the grade determining unit; a grade discriminating unit for transferring the grade of a corresponding liquid crystal display panel based upon receiving data input to the grade inputting unit; a storing unit having a grade displaying unit for classifying the graded liquid crystal display panels according to grades and storing the grades; and a robot driving unit for transferring the liquid crystal display panel to the storing unit according to instructions from the grade discriminating unit.

Abstract: A handling unit includes a frame, at least one arrangement module, and at least one chip carrier. The frame has at least one recess for the interchangeable mounting of at least one of the arrangement modules. The arrangement module has at least one receptacle for the mounting of at least one chip carrier. The chip carrier has at least one chip seat for holding a chip.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

Abstract: A manufacturing cell for inspecting workpieces such as magnetic disk substrates comprises an input conveyor for providing workpieces to be tested, one or more testers for inspecting the workpieces, and three or more output receptacles for receiving tested workpieces. One or more robotic arms move the workpieces from the input conveyor to the tester and from the tester to one of the output receptacles depending upon the results of the test performed by the tester. The output receptacles include a pass receptacle, a reject receptacle, and at least an additional receptacle for workpieces that are to be re-worked or studied further. If the additional receptacle is full, workpieces that would otherwise be provided to the additional bin are placed in the reject receptacle. The reject receptacle is very large, so that it is rarely filled to capacity.

Abstract: A test device includes first and second testers each having at least one testing contact for making contact with at least one external contact of an electronic component; and a conveying device that conveys electronic components to the first and second testers in a synchronized manner such that the external contacts of the electronic components form an electrical connection to the testing contacts. Via the testing contacts, it is possible to apply input voltages and input currents to the electronic components and it is possible to measure the voltages, currents and resistances prevailing in the electronic components. The testers check the electronic components on the basis of a predetermined overall set of test criteria or on the basis of subsets of the overall set of test criteria.

Abstract: A method and apparatus for a thermal stratification test providing cyclical and steady-state stratified environments. In order to test an electronic device, for example one having one or more levels of ball-grid-array interconnections, e.g., connecting a chip to a flip-chip substrate and connecting the flip-chip substrate to a printed circuit board of a device, an apparatus and method are provided to heat one side of the device while cooling the second side. In some embodiments, the process is then reversed to cool the first side and heat the second. Some embodiments repeat the cycle of heat-cool-heat-cool several times, and then perform functional tests of the electronic circuitry. In some embodiments, the functional tests are performed in one or more thermal-stratification configurations after cycling at more extreme thermal stratification setups. In some embodiments, a test that emphasizes solder creep is employed.

Abstract: Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include picking and removing all of the bad parts from a wafer before picking the good parts and picking all of the good parts first without picking any part necessary to align the wafer. The equipment includes several embodiments of a transfer machine that accommodates the efficient transfer of semiconductor parts between tacky film, waffle packs and tape and reel containment systems. Residual good parts are stored in waffle packs and can be subsequently reused in the packaging process.

Abstract: Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.

Abstract: A component handler includes an improved test seat having a shape that ensures that an electronic component seated in the test seat is in an appropriate orientation for parametric testing. The test seat has a base surface and first and second opposed seat side surfaces separated by generally increasing distances from a narrower notch end to a wider notch end. There is an opening at the narrower notch end. An electronic component is seated within this test seat such that the first and second side surfaces of the electronic component rest against the first and second seat side surfaces. A side surface side margin on which is formed a wraparound electrode is exposed by an opening at the narrower notch end and a second side surface side margin on which is formed a second wraparound electrode is exposed by an opening at the wider notch end.

Abstract: A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.

Abstract: A work inspection system 2 includes: a conveyor table 7 vertically positioned, and conveying works W stored in work-storing pockets 9; a work inspection apparatus for inspecting the works stored in the work-storing pockets 9 of the conveyor table 7; and a sorting and ejecting apparatus 12 for sorting the inspected works stored in the work-storing pockets of the conveyor table in accordance with a property of the works and ejecting the same. The work-storing pockets 9 of the conveyor table 7 are positioned inside the periphery 7a of the conveyor table 7 to surround the works W. The work-storing pockets 9 are disposed along two concentric circles on the conveyor table 7.

Abstract: An apparatus for measuring the electrical characteristic of a chip-shaped electronic component having first and second external terminal electrodes at first and second opposing ends thereof includes a holder that holds an electronic component with the first and second external terminal electrodes pointing toward first and second open ends of a receiving cavity. The holder is provided with a shield layer extending between first and second measuring terminals, and the shield layer is electrically connected to a measurement reference potential. The shield layer reduces the stray parasitic capacitance adjacent to the electronic component, and reduces measurement errors resulting from size variations of the electronic component.

Abstract: An electronic-component conveying device includes a conveying plate which moves in one conveying direction and has a plurality of component-holders arranged at a predetermined pitch along the conveying direction. This conveying device further includes component-containers each containing a plurality of electronic components for supplying the components to the holders. The electronic components are held by the holders while being conveyed by the conveying plate. Cameras, i.e. a component-detecting unit, are provided for detecting the presence of the electronic components in the holders. A controller, i.e. a component-feeding unit, is provided for feeding additional electronic components to each of the containers based on the detection of the presence of the electronic components.

Abstract: Circuit modules comprise a carrier surface with components mounted thereon. A testing apparatus for these modules comprises a magazine for hosting a row of circuit modules. The row is pushed into a gripper of a pickup mechanism by means of a press-on member. As a consequence, the orientation of the magazine can be horizontal. The gripper removes the gripped modules in a direction in line with the row. The press-on member preferably comprises a rotatable press-on plate which rotates along with the row of modules if it starts to fan out, but at the same time pushes the row back so that significant fanning is prevented.

Abstract: A method of manufacturing disk drives that are subject to disk pack imbalance includes steps of measuring the disk pack imbalance of each drive and assigning each of the drives to one of a predetermined plurality of categories, depending upon the measured disk pack imbalance. The measured imbalance of the disk drives assigned to fewer than the predetermined plurality of categories may then be reduced. Each category may be associated with one or more customers and the drives assigned to each category may be shipped to the associated customer(s).

Abstract: An apparatus for handling, storing and reloading carriers for disk-shaped items, such as semiconductor wafers or CDs, has at least one cleaning unit and at least one storage unit for the carriers containing the disk-shaped items. The apparatus further has at least one sorting unit for the disk-shaped items. The cleaning unit, the storage unit and the sorting apparatus are integral component parts of the apparatus and are operated by a common automatic control.

Abstract: Various preferred processes and equipment are described herein that more efficiently handle residual semiconductor parts during packaging. The processes include picking and removing all of the bad parts from a wafer before picking the good parts and picking all of the good parts first without picking any part necessary to align the wafer. The equipment includes several embodiments of a transfer machine that accommodates the efficient transfer of semiconductor parts between tacky film, waffle packs and tape and reel containment systems. Residual good parts are stored in waffle packs and can be subsequently reused in the packaging process.

Abstract: A method and apparatus performs testing, sorting, and packaging of partially defective semiconductor memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: The invention can be easily applied to various contacts irrespective of the length of time needed for replacing ICs with other ICs relative to the contact. An IC handler comprises contact cleaning chips made of a material including polishing particles in the same shape as an ICs wherein a transfer attachment is removed from the contacts when contact cleaning chips are conveyed to the contacts so as to contact the contacts, then the contacts are taken out.

Abstract: The invention describes a method for measuring and classifying resistors (2), in which in a measuring station (3) the resistance value of the resistor (2) supplied by a feed and transport device (12) of the measuring station (3) is measured. The measured resistance value is transmitted to an evaluation unit (40) of a control device (20). The resistor (2) is delivered sorted according to predetermined measurement ranges into an output device (25) arranged after the measuring station (3). The resistor (2) is heated to a predefined nominal temperature by a temperature regulating device (7), in particular by a medium (9). After reaching this nominal temperature the resistor (2) is contacted in the medium (9). Afterwards the measurement of the resistor (2) is carried out.

Abstract: A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Abstract: A new method and system of testing and classifying semiconductor devices is provided. User requirements are collected for this purpose, test specifications and test functions are defined for the to be tested DRAM devices. The Automatic Classification Shipping (ACS) data base is updated with test related data, the testing is performed whereby DRAM devices are assigned categories from with DRAM classes are derived. These identified classes are used to sort the tested DRAM devices in accordance with their tested functional performance characteristics.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: The invention provides methods for marking packaged ICs. In a first embodiment, only the minimum performance information is first marked on the package, regardless of the actual performance of the IC. This method avoids a second marking step for all ICs sold as low-performance ICs. In another embodiment, only one inking and curing step is required for all ICs. According to this method, all specified performances are marked on the packaged IC at the first marking. The IC is then tested to determine the actual performance, and all performance markings not applicable to the IC are removed, preferably with a laser. Alternatively, all applicable performance markings are identified (e.g., underlined or enclosed with a laser marking).

Abstract: A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Abstract: A method and apparatus which enables fast testing of light sensing integrated circuits is disclosed. The integrated circuit is positioned in a test head which includes a light source output providing a flat field light to shine on the light sensing portion of the integrated circuit under test. The light is provided to the light source output through an optical fiber from a light box which includes electronic filtering and shutter operations. Light is provided to the light box through another optical fiber from a precision light source. The operation of the light box, including adjusting filtering characteristics and shutter timing is controlled from a tester which also controls the integrated circuit under test in the test head. A high speed data link couples output signals from the test head to dedicated signal processing circuitry which analyzes the output signals to determine whether the integrated circuit passes or fails testing.

Abstract: In a part-mounting system formed by linking plural part-mounting devices which carry out respective process steps of part-mounting, when a production tact-time of one of the devices varies beyond a given variation range, a tact-time change signal is sent to other devices located at upstream and/or downstream of the device via a communicating section. The other devices receive the tact-time change signal and changes their own work tact-times from the ones corresponding to a productivity-oriented mode to a slower tact-pattern corresponding to a quality-oriented mode. Thus every device constituting the system can accommodate a tact-time variation due to a tact-time delay of any part-mounting device. As a result, the quality appropriate to the tact-time can be secured.

Abstract: The invention relates to a card assembly apparatus for assembling PC cards and the like, and it is an object of the invention to provide a card assembly apparatus which makes it possible to reduce costs required for card assembly and to improve the throughput of card assembly. It has a top side processing portion 1 for performing predetermined assembly processes on a top side of a card and a bottom side processing portion 2 for performing predetermined assembly processes on a bottom side of a card.

Abstract: A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Abstract: The present invention discloses a test handler comprising a main body, a stocker including a user tray supplier and a user tray deliver for loading plurality of user trays carrying the semiconductor device during devices tests, a plurality of test trays, a device loading means for transferring the devices in the user tray of the user tray supplier to the test tray, a first tray inverter changing the horizontal posture of the test tray, a soak chamber preparing a desired test temperature condition, a test chamber accomplishing tests, a de-soak chamber restoring the devices temperature, a second tray inverter inverting to the test tray of a horizontal posture, a device unloading means transferring the semiconductor devices on the test tray. The present invention can double the lot size in unit operation to improve equipment operation ratio. In more, the device loading time and unloading can be reduced so that the number of the devices treated in unit operation can be increased.

Abstract: A method and apparatus is provided for sorting semiconductor devices for processing where the semiconductor devices have been singulated from a strip containing a plurality of semiconductor devices and where an electronic strip map has been created corresponding to the strip of semiconductor devices and the electronic strip map contains address and quality information related to each individual singulated semiconductor device. The method includes the steps of moving a pickup device to a location adjacent the singulated semiconductor devices and selectively picking up a first plurality of singulated semiconductor devices based on the electronic strip map information related to the singulated semiconductor devices and moving the semiconductor devices that have been picked up to a predetermined location based on the electronic strip map information related to the specific semiconductor devices that have been picked up and unloading the first plurality of semiconductor devices at the predetermined location.

Abstract: An automatic ROM burning device, comprising a support plate that is erected almost vertically. On the surface of the support plate is at least one feeder chute, inside which is inserted an IC rod, enabling the ROM component inside the IC rod waiting to be burned with data to lower in sequential order by gravity, while a moving mechanism moves it under the control of a control unit into a burner unit. The burner unit serves to conduct data burning and test operation on the components under the control of a control unit, and categorize the components according to the results obtained from the burning and testing operation. After data burning is completed, a moving mechanism delivers the components to a moving unit, moving the categorized components to separate discharge troughs; those of the same category are guided into empty IC rods for discharge.

Abstract: Disclosed herein is a semiconductor device loading apparatus for test handlers. The semiconductor device loading apparatus includes a body. The apparatus body includes a plurality of pickup cylinders provided with a plurality of vacuum adsorbers for vacuum-sucking and transferring semiconductor devices to be tested, a space adjusting plate for adjusting the pitches of the vacuum adsorbers, and an elevation guiding means for guiding the lifting and lowering of the space adjusting plate. A guide block fixing plate is formed to be separate from the body for guiding the semiconductor devices to be accurately positioned in the pockets of a test tray, respectively.

Abstract: A method and apparatus is provided for sorting semiconductor devices for processing where the semiconductor devices have been singulated from a strip containing a plurality of semiconductor devices and where an electronic strip map has been created corresponding to the strip of semiconductor devices and the electronic strip map contains address and quality information related to each individual singulated semiconductor device. The method includes the steps of moving a pickup device to a location adjacent the singulated semiconductor devices and selectively picking up a first plurality of singulated semiconductor devices based on the electronic strip map information related to the singulated semiconductor devices and moving the semiconductor devices that have been picked up to a predetermined location based on the electronic strip map information related to the specific semiconductor devices that have been picked up and unloading the first plurality of semiconductor devices at the predetermined location.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: The present invention relates to a system of IC transporting process for IC test device and the method thereof, and in particular, an IC transporting system having a plurality of buffering regions provided at the front end and rear end of the test region of the IC chip. The system comprises an empty tray treating region, feeding region, main buffering region, test region, and distribution region. The present invention makes use of time-differential of transporting IC chip loading trays between the distribution region and the main buffering region to maintain the testing process of IC chips. Thus, the present invention provides a high and efficient productivity.

Abstract: There is an IC (integrated circuit) testing device 11 that receives singulated ICs from a singulation station's bottom table 44, where an IC 15 has slid down onto loading ramp or track 16. The IC will slide into test station 18, where stop pin 22 has been inserted to stop the IC in DUT (device under test) station 20. In the DUT station, the IC is securely held in position by an extractor bar 26, insertion bar 28, and a part guide 24. Thereby, test cite station 18 will move downward and insert IC 15 into testing socket 30. After testing the IC, testing station 18 returns upward with IC in the same secured position. Pin 22 will be removed to allow the IC to slide into part holding station 31. If the IC was not defective, pin 32 will be removed to allow the IC to slide onto track 36 of the IC separator station 34. While the test cite station 18 is in the up position a second IC is slid along track 16 and loaded into DUT cite 20 being readied for the next test cycle.