Abstract: A semiconductor device is disclosed. The semiconductor device comprises, a first region of a first conductivity type, a second region of a second conductivity type disposed adjacent to the first region to form a p-n junction structure, a resistance modification region of the second conductivity type, and a field response modification region of the second conductivity type disposed between the resistance modification region and the second region, wherein the field response modification region comprises a varying dopant concentration distribution along a thickness direction of the field response modification region.

Abstract: The invention relates to semiconductor components, in particular solar cells made of III-V compound semiconductors, as are used in terrestrial PV concentrator systems or for electrical energy supply in satellites. However it is also used in other optoelectronic components, such as lasers and light diodes, where either high tunnel current densities are necessary or special materials are used and where stress in the entire structure is not desired.

Abstract: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.

Abstract: A type-II tunnel junction is disclosed that includes a p-doped AlGaInAs tunnel layer and a n-doped InP tunnel layer. Solar cells are further disclosed that incorporate the high bandgap type-II tunnel junction between photovoltaic subcells.

Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.

Abstract: In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n? type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n? type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed.

Abstract: In some embodiments of the invention, a device includes a substrate and a semiconductor structure. The substrate includes a wavelength converting element comprising a wavelength converting material disposed in a transparent material, a seed layer comprising a material on which III-nitride material will nucleate, and a bonding layer disposed between the wavelength converting element and the seed layer. The semiconductor structure includes a III-nitride light emitting layer disposed between an n-type region and a p-type region, and is grown on the seed layer.

Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive coupled plasma reactive ion etching. A first support structure is attached to the semiconductor layers. The hard substrate is then removed, beneficially by laser lift off. A second supporting structure, preferably conductive, is substituted for the hard substrate and the first supporting structure is removed. Individual devices are then diced, beneficially by etching through the second supporting structure. A protective photo-resist layer can protect the semiconductor layers from the attachment of the first support structure.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.

Abstract: Provided is a variable resistive element which performs high speed and low power consumption operation. The variable resistive element comprises a metal oxide layer between first and second electrodes wherein electrical resistance between the first and second electrodes reversibly changes in accordance with application of electrical stress across the first and second electrodes. The metal oxide layer has a filament, which is a current path where the density of a current flowing between the first and second electrodes locally increases. A portion including at least the vicinity of an interface between the certain electrode, which is one or both of the first and second electrodes, and the filament, on an interface between the certain electrode and the metal oxide layer is provided with an interface oxide which is an oxide of at least one element included in the certain electrode and different from the oxide of the metal oxide layer.

Abstract: A semiconductor device made of a group-III nitride semiconductor having excellent properties is provided. The semiconductor device has a horizontal diode structure of Schottky type or P-N junction type, or combined type thereof having a main conduction pathway in the horizontal direction in a conductive layer with unit anode portions and unit cathode electrodes being integrated adjacently to each other in the horizontal direction. The conductive layer is preferably formed by depositing a group-III nitride layer and generating a two-dimensional electron gas layer on the interface. Forming the conductive layer of the group-III nitride having high breakdown field allows the breakdown voltage to be kept high while the gap between electrodes is narrow, which achieves a semiconductor device having high output current per chip area.

Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A high-frequency metal-insulator-metal (MIM) type diode is constructed as a bridge suspended above a substrate to significantly reduce parasitic capacitances affecting the operation frequency of the diode thereby permitting improved high-frequency rectification, demodulation, or the like.

Abstract: The present invention provides a semiconductor light emitting element with excellent color rendering properties, a method for manufacturing the semiconductor light emitting element, and a light emitting device. The semiconductor light emitting element includes: a semiconductor substrate that has a convex portion having a tilted surface as an upper face, and a concave portion formed on either side of the convex portion, the concave portion having a smaller width than the convex portion, a bottom face of the concave portion being located in a deeper position than the upper face of the convex portion; and a light emitting layer that is made of a nitride-based semiconductor and is formed on the semiconductor substrate so as to cover at least the convex portion.

Abstract: A semiconductor device including polysilicon (poly-Si) and method of manufacturing the same are provided. The semiconductor device includes a TaNx material layer and a poly-Si layer formed on the TaNx material layer. The semiconductor device including poly-Si may be manufactured by forming a TaNx material layer and forming a poly-Si layer by depositing silicon formed on the TaNx material layer and annealing silicon.

Abstract: A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.

Abstract: A surface plasmon polaritron activated semiconductor device uses a surface plasmon wire that functions as an optical waveguide for fast communication of a signal and functions as a energy translator using a wire tip for translating the optical signal passing through the waveguide into plasmon-polaritron energy at a connection of the semiconductor device, such as a transistor, to activate the transistor for improved speed of communications and switching for preferred use in digital systems.

Abstract: An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.

Abstract: In one embodiment the present invention includes a semiconductor rectifier device comprising a first, second, and third semiconductor regions and a gate. The first semiconductor region is of a first conductivity type. The second semiconductor region is adjacent to the first semiconductor region which has a second conductivity type. The third semiconductor region is adjacent to the second semiconductor region which has the second conductivity type. The gate is proximate to but insulated from the second semiconductor region and electrically coupled to the third semiconductor region. When the first semiconductor region is biased in a first direction, an inversion region forms in the second semiconductor region. The inversion region forms a forward-biased tunnel diode junction with the third semiconductor region. When the first semiconductor region is biased a second direction, the semiconductor rectifier device functions as a reverse-biased PIN diode.

Abstract: A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.

Abstract: A semiconductor body includes an n-conductive semiconductor layer and a p-conductive semiconductor layer. The p-conductive semiconductor layer contains a p-dopant and the n-conductive semiconductor layer an n-dopant and a further dopant.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.

Abstract: Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers is tensile strained. Some disclosed resonant interband tunneling diodes comprise a plurality of substantially coherently strained layers including layers selected from a group consisting of silicon, germanium, and alloys of silicon and germanium, wherein at least one of said substantially coherently strained layers defines a barrier to non-resonant tunnel current. Some disclosed interband tunneling diodes comprise a plurality of substantially coherently strained layers, wherein at least one of said substantially coherently strained layers is tensile strained.

Abstract: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotataing element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.

Abstract: An inclined surface having an inclination angle ? is formed in an edge portion which forms an opening portion of an inter-layer insulating film, thereby reducing a stress by the inclined surface.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: A compound semiconductor device includes: a conductive SiC substrate; an AlN buffer layer formed on said conductive SiC substrate and containing Cl; a compound semiconductor buffer layer formed on said AlN layer which contains Cl, said compound semiconductor buffer layer not containing Cl; and a device constituent layer or layers formed above said compound semiconductor buffer layer not containing Cl.

Abstract: The present invention provides a semiconductor light emitting element with excellent color rendering properties, a method for manufacturing the semiconductor light emitting element, and a light emitting device. The semiconductor light emitting element includes: a semiconductor substrate that has a convex portion having a tilted surface as an upper face, and a concave portion formed on either side of the convex portion, the concave portion having a smaller width than the convex portion, a bottom face of the concave portion being located in a deeper position than the upper face of the convex portion; and a light emitting layer that is made of a nitride-based semiconductor and is formed on the semiconductor substrate so as to cover at least the convex portion.

Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.

Abstract: A semiconductor substrate has a second conductivity type cathode layer formed thereon. The cathode layer has a first conductivity type base layer formed thereon. A first anode region of the second conductivity type is formed in the surface of the base layer. A second anode region of the first conductivity type is formed in the first anode region. A first semiconductor region of the first conductivity type is formed in contact with the semiconductor substrate. A second semiconductor region of the second conductivity type is formed adjacent to the first semiconductor region and in contact with the cathode layer. An intermediate electrode is formed on the surfaces of the first semiconductor region and the contact region.

Abstract: A surface emitting semiconductor component (1) with an emission direction which comprises a semiconductor body (2). The semiconductor body comprises a plurality of active regions (4a, 4b) which are suitable for the generation of radiation and are arranged in a manner spaced apart from one another, a frequency-selective element (6) being formed in the semiconductor body.

Abstract: A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. The power supply device includes a first power supply; a voltage step-up unit that steps up an output voltage of the first power supply; a voltage step-down unit that steps down an output voltage of the voltage step-up unit; and a load that is driven to operate by an output voltage of the voltage step-down unit. The voltage step-up unit steps up the output voltage of the first power supply to a lower limit of an operating voltage of the voltage step-down unit.

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract: A semiconductor device includes a p-type semiconductor layer and an n-type semiconductor layer that are joined by sandwiching a depletion layer with a thickness that allows transmission of a plurality of electrons and holes by direct-tunneling.

Abstract: A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved.

Abstract: This invention relates to a tunnel device which can generate tunneling effect with multi-band waveforms. The tunnel device can also be interacted with the field which includes thermal field, optical field, electric field, magnetic field, pressure field, acoustic field, or any combination of them. This tunnel device can be a power conversion device for driving high speed loading such as p-n junction device.

Abstract: A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

Abstract: A nitride semiconductor light emitting device has high internal quantum efficiency but low operating voltage. The nitride semiconductor light emitting device includes an n-nitride semiconductor layer; an active layer of multi-quantum well structure formed on the n-nitride semiconductor layer, and having a plurality of quantum well layers and a plurality of quantum barrier layers; and a p-nitride semiconductor layer formed on the active layer. One of the quantum well layers adjacent to the n-nitride semiconductor layer has an energy band gap greater than that of another one of the quantum well layers adjacent to the p-nitride semiconductor layer.

Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.

Abstract: The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

Abstract: A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate placed against the stack with an interposed insulating layer.

Abstract: A thermionic or thermotunneling gap diode device consisting of two silicon electrodes maintained at a desired distance from one another by means of spacers. These spacers are formed by oxidizing one electrode, protecting certain oxidized areas and removing the remainder of the oxidized layer. The protected oxidized areas remain as spacers. These spacers have the effect of maintaining the electrodes at a desired distance without the need for active elements, thus greatly reducing costs.

Abstract: A semiconductor sensing device for sensing presence, absence or level of species-of-interest in the environment is disclosed. The semiconductor sensing device comprises at least one layer of molecules deposited thereon. The molecules are electrically-responsive to the species-of-interest in a manner such that when the molecules interact with the species-of-interest, a reverse breakdown voltage characterizing the semiconductor sensing device is modified.

Abstract: A power semiconductor device includes a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side. A second layer of a second conductivity type is arranged in a central region of the first main side and a fourth electrically conductive layer is arranged on the second layer. On the second main side a third layer with a first zone of the first conductivity type with a higher doping than the first layer is arranged followed by a fifth electrically conductive layer. The area between the second layer and the first zone defines an active area. The third layer includes at least one second zone of the second conductivity type, which is arranged in the same plane as the first zone. A sixth layer of the first conductivity type with a doping, which is lower than that of the first zone and higher that that of the first layer, is arranged between the at least one second zone and the first layer.

Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract: A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm2 to 10/cm2 c-axis gross core regions (F) containing at least one crystal having a c-axis parallel to the c-axis of the low dislocation single crystal regions (Z) and an a-axis different from the a-axis of the low dislocation single crystal regions (Z).

Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.