Abstract: A novel tunnel structure is described that enables tunnel diode behavior to be exhibited even in material systems in which extremely heavy doping is impossible and only moderate or light doping levels may be achieved. In one aspect, the tunnel heterostructure includes a first semiconductor layer, a second semiconductor layer, and an intermediate semiconductor layer that is sandwiched between the first and second semiconductor layers and forms first and second heterointerfaces respectively therewith. The first and second heterointerfaces are characterized by respective polarization charge regions that produce a polarization field across the intermediate semiconductor layer that promotes charge carrier tunneling through the intermediate semiconductor layer. In another aspect, the invention features a semiconductor structure having a p-type region, and the above-described heterostructure disposed as a tunnel contact between the p-type region of the semiconductor structure and an adjacent n-type region.

Abstract: A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Abstract: An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge2Se8 or Ge25Se75). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element.

Abstract: The present invention relates to a microwave electronic device (1) comprising a metal enclosure (2) having a bottom (21) and a lid (23) and containing an electronic circuit board (3) disposed substantially parallel to said bottom and to said lid, said circuit board having: conductive bottom and top grounding layers (41, 42) respectively disposed on bottom and top faces (31, 32) of the circuit board, and perforations (7a) transverse to said faces of the circuit board and delimited by conductive walls (71) for electrically interconnecting said layers (41, 42). At least some of said walls (71) are electrically connected to the lid of the enclosure by conductive grounding members (8a). Each conductive member (8a) has a metal blade covered with a material (13, 13?) for absorbing microwaves.

Abstract: The invention is a magnetic device, i.e., a magnetoresistive sensor or a magnetic tunnel junction device, that has a ferromagnetic structure of two ferromagnetic layers antiferromagnetically coupled together with an improved antiferromagnetically coupling (AFC) film. The AFC film is an alloy of Ru100-xFex where x is between approximately 10 and 60 atomic percent. This AFC film increases the exchange coupling by up to a factor or two and has an hcp crystalline structure making it compatible with Co alloy ferromagnetic layers.

Abstract: A semiconductor diode structure is provided which includes a substrate; a fin formed of a semiconducting material positioned vertically on the substrate, the fin includes a first heavily-doped region of a first doping type on one side and a second heavily-doped region of a second doping type on an opposite side; and a first conductor contacting the first heavily-doped region and a second conductor contacting the second heavily-doped region.

Abstract: A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Abstract: Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.

Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.

Abstract: A tunneling junction element comprises: a substrate; a lower conductive layer formed on the substrate; a first oxide layer formed on the lower conductive layer and having a non-stoichiometric composition;a second oxide layer formed on the first oxide layer and having a stoichiometric composition; and an upper conductive layer formed on the second oxide layer, wherein the first oxide layer is oxidized during a process of forming the second oxide layer and has an oxygen concentration which is lower than an oxygen concentration of the second oxide layer and lowers with a depth in the first oxide layer, and the first and second oxide layers form a tunneling barrier.

Abstract: The quantum circuit device comprises: an asymmetrical coupled quantum dot of a main quantum dot 3a and an operational quantum dot 3b of a smaller size than the main quantum dot 3c; an asymmetrical coupled quantum dot of a main quantum dot 3c arranged at a distance which does not permit to substantially tunnel from the main quantum dot 3a, and an operation quantum dot 3d having a smaller size than the main quantum dot 3c and arranged at a distance which permits tunneling from the operational quantum dot 3b; and a laser device for applying to the asymmetrical coupled quantum dots a laser beam of a wavelength which resonates an inter-level energy the asymmetrical coupled quantum dots. In the sleep state, electron is present at the ground state of the main quantum dot, where no exchange interaction takes place, and in an operation, the electron is transited to an excited state of the operational quantum dot, whereby the operation is made by the exchange interactions between the adjacent operational quantum dots.

Abstract: A high-voltage diode and a method for producing the high-voltage diode involve only three masking steps. Only three masking steps are required due to the use of adjustment structures and of a chipping stopper with an edge passivation containing a-C:H or a-Si. In this manner, the high-voltage diode is inexpensive to manufacture. The diode has a rating for reverse voltages of, in particular, above about 400 V and preferably above about 500 V, and can be fabricated with the least possible process complexity and thus a small number of photo technologies and, in the edge region, can readily be equipped with a channel stopper for avoiding leakage currents and a chipping stopper for limiting the extent of saving defects.

Abstract: The invention relates to technology improving the withstand voltage of a Schottky diode. With a diode of the present invention, the distance a between the long sides of the narrow groove withstand voltage portions and the inner ring circumference of the intermediate withstand voltage portion is set to twice the distance b between the short sides of the narrow groove withstand voltage portions and the inner ring circumference of the intermediate withstand voltage portion. Furthermore, the distance c between the inner ring circumference of the innermost outer withstand voltage portions and the outer ring circumference of the intermediate withstand voltage portion, the distance u between the adjacent outer withstand voltage portions, and the distance d between the adjacent narrow groove withstand voltage portions are all equal to the distance a.

Abstract: The tunnel junction structure comprises a p-type tunnel junction layer of a first semiconductor material, an n-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. At least one of the semiconductor materials includes gallium (Ga), arsenic (As) and either nitrogen (N) or antimony (Sb). The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer.

Abstract: A vertical cavity apparatus includes first and second mirrors, a substrate and at least first and second active regions positioned between the first and second mirrors. At least one of the first and second mirrors is a fiber with a grating. At least a first tunnel junction is positioned between the first and second mirrors.

Abstract: A GaN-based compound semiconductor epi-wafer includes: a substrate 11 made of a first nitride semiconductor belonging to a hexagonal system; and an element layer 12 for forming a semiconductor element, which is made of a second nitride semiconductor belonging to the hexagonal system and which is grown on a principal surface of the substrate 11. An orientation of the principal surface of the substrate 11 has an off-angle in a predetermined direction with respect to a (0001) plane, and the element layer 12 has a surface morphology of a stripe pattern extending substantially in parallel to the predetermined direction.

Abstract: A method for producing laterally varying multiple diodes and their device embodiment are presented herein. As demonstrated, multiple resonant tunneling diodes are fabricated together utilizing a single epitaxial structure. Shallow, ion-implanted regions having varying depths, dx, define the collector contacts. Each diode is isolated electrically from the others by methods such as conventional mesa etching into the emitter layer. The varying depths, dx, provide means for varying the peak voltage of each individual diode. The peak voltage strongly depends on the depths, dx, because it comprises a space charge region where the electric field is high, and therefore the voltage drop is high. The invention disclosed herein is useful in applications such as high-speed circuits such as comparators, analog to digital converters, sample and hold circuits, logic devices, and frequency multipliers.

Abstract: There is disclosed a p-n junction diode structure whose electrical characteristics can be affected by the application of pressure or other mechanical stresses that will control sensitivity. The p-n junction consists of two different semiconductor materials, one being of p-type and the other of n-type, both having predetermined crystallographic axes which are fusion bonded together to form a p-n junction. Because of the ability to control the position of the crystallographic axes with respect to one another, one can affect the electrical characteristics of the p-n junction and thereby produce devices with improved operating capabilities such as Zener diodes, tunnel diodes as well as other diodes.

Abstract: A diamond pn junction diode includes a p-type diamond thin-film layer formed on a substrate and an n-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer, or alternatively includes an n-type diamond thin-film layer formed on a substrate and a p-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer.

Abstract: One aspect of the present invention is a to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness beneath and adjacent to the pn junction interface.

Abstract: The tunnel junction structure comprises a p-type tunnel junction layer of a first semiconductor material, an n-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. At least one of the semiconductor materials includes gallium (Ga), arsenic (As) and either nitrogen (N) or antimony (Sb). The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer.

Abstract: The invention relates to an integrated chip diode manufactured by forming two different typed semiconductors on the top and bottom of a wafer respectively and forming a plurality of diodes thereon, each diode comprises glass insulator encapsulated on sides thereof, two conductive metal layers formed on the surfaces of the semiconductors respectively, an insulation material coated on a portion of the surface of one conductive metal layer and a third conductive metal layer sintered on the glass insulator, such that the other conductive metal layer can be electrically connected to the insulation material on the one conductive metal layer via the third conductive metal layer. Thus, two independent soldered conductive terminals are formed at the same sides of the diodes and electrically connected to each of different typed semiconductors.

Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.

Abstract: An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor (12) is connected in parallel to a diode (11) made of silicon carbide. Although a resistive component of the diode (11) varies widely with turn-on and turn-off of the diode (11), connecting the resistor (12) in parallel to the diode (11) allows suppression of variations in a resistive component of an LCR circuit formed by the diode (11) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Abstract: A mask ROM and a method for manufacturing such a mask ROM are provided. Here, the mask ROM can be effective to obtain a product that corresponds to each user's specification, where the same aluminum reticle is used even though each user uses different specification. For manufacturing the mask ROM, one of a first route and a second route is selected. The first route is for providing a second NAND circuit 26 with an input of a pulse obtained by passing a standard pulse 93 from an address transition detecting circuit through a first delay circuit 23 and an input of a fixed potential.

Abstract: A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load.

Abstract: A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.

Abstract: An LDMOS field effect transistor (80) provides protection against the inadvertent reversal of polarity of voltage applied across the device. To protect an N-channel device, a floating P-type blocking region (82) is provided surrounding the drain region (32). The blocking region (82) is spaced apart from a body region (28) that forms the diffused channel (34) of the transistor (80). A first gate electrode (36) controls the conductivity of the diffused channel (34) and a second gate electrode (84) controls the conductivity of the surface (35) of the blocking region (82).

Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.

Abstract: A light-emitting device includes: a semiconductor structure formed on one side of a substrate, the semiconductor structure having a plurality of semiconductor layers and an active region within the layers; and first and second conductive electrodes contacting respectively different semiconductor layers of the structure; the substrate comprising a material having a refractive index n>2.0 and light absorption coefficient &agr;, at the emission wavelength of the active region, of &agr;>3 cm−1. In a preferred embodiment, the substrate material has a refractive index n>2.3, and the light absorption coefficient, &agr;, of the substrate material is &agr;<1 cm−1.

Abstract: An optic semiconductor package includes a plate shaped substrate having an insulation layer through which two spaced apart layer apertures are formed. The substrate further includes a plurality of electrically conductive patterns formed on the wall surfaces of the layer apertures and a lower surface of the insulation layer. One of a laser diode and a photo detector are disposed in a different one of the two layer apertures and are each electrically connected to the electrically conductive patterns through conductive bumps formed on the laser diode and the photo detector. An insulation plate, having a plurality of plate apertures formed through portions of the insulation plate adjacent to the electrically conductive patterns, is coupled to the lower surface of the substrate. One of a plurality of conductive pins electrically connected with the electrically conductive patterns is fitted in each of the plate apertures of the insulation plate and extends downward from the insulation plate.

Abstract: A unipolar spin diode and a unipolar spin transistor. In one embodiment, the unipolar spin diode includes a first semiconductor region having a conductivity type and a spin polarization, and a second semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor and a spin polarization that is different from the spin polarization of the first semiconductor region. The first semiconductor region and the second semiconductor region are adjacent to each other so as to form a spin depletion layer therebetween, the spin depletion layer having a first side and an opposing second side. When a majority carrier in the first semiconductor region moves across the spin depletion layer from the first side of the spin depletion layer to the second side of the spin depletion layer, the majority carrier in the first semiconductor region becomes a minority carrier in the second semiconductor region.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: One aspect of the present invention is a to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness beneath and adjacent to the pn junction interface.

Abstract: A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode.

Abstract: Provided is a diode circuit with small power consumption. A first voltage comparator (4) compares a voltage at a cathode terminal (101) with a sum of a voltage at an anode terminal (102) and a voltage across a first voltage source (10) to output a reset signal, and a second voltage comparator (5) compares a voltage at the anode terminal (102) with a sum of a voltage at the cathode terminal (101) and a voltage across the second voltage source (11) to output a set signal. A first latch circuit (20) outputs an L signal when the reset signal from the first voltage comparator (4) is inputted, and outputs an H signal when the set signal from the second voltage comparator (5) is inputted. An n-channel MOS transistor (2) turns off upon receiving the L signal, and turns on upon receiving the H signal, to thereby limit an output current.

Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.

Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p-type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.

Abstract: Implemented is a diode which controls an energy loss produced during a reverse recovery operation and generates an oscillation of an applied voltage with difficulty even if a reverse bias voltage has a great value. An N layer 101 and a P layer 102 are formed in a semiconductor substrate such as silicon. Furthermore, a cathode side P layer 103 is also formed facing a cathode electrode 105 in a position on the N layer 101 that a depletion layer extended during application of a reverse bias voltage does not reach. By providing the cathode side P layer 103, a current density of a reverse current obtained during a reverse recovery operation can be increased, the sudden change of a resistance component of a diode can be prevented and the generation of a voltage oscillation can be suppressed. The cathode side P layer 103 has a diameter W of approximately 400 &mgr;m or less and a rate of an area of the cathode side P layer 103 occupying a cathode surface is kept at approximately ⅖ or less.

Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p- type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.

Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyamide passivation and planerization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 706 that serves as a foundation for bottom contact layers 708 and a polyamide 700 coating. An ohmic metal contact 702 and emitter metal contact 704 protrude above the polyamide 700 coating exposing the ohmic metal contact 702 and emitter metal contact 704. The contacts are capped with an etch resistant coating 710 thus allowing for the polyamide etch, and other etching processes without adversely affecting the contacts.

Abstract: In an electrode structure for a nitride III-V compound semiconductor device, a metallic nitride is used as an electrode material. A metallic material of the metallic nitride has a negative nitride formation free energy, and comprises at least one metal selected from a group consisting of IVa-group metals such as titanium and zirconium, Va-group metals such as vanadium, niobium, and tantalum, and VIa-group metals such as chromium, molybdenum, and tungsten.

Abstract: A p-n tunnel junction between a p-type semiconductor layer and a n-type semiconductor layer provides current injection for an nitride based vertical cavity surface emitting laser or light emitting diode structure. The p-n tunnel junction reduces the number of p-type semiconductor layers in the nitride based semiconductor VCSEL or LED structure which reduces the distributed loss, reduces the threshold current densities, reduces the overall series resistance and improves the structural quality of the laser by allowing higher growth temperatures.

Abstract: A method of epitaxially growing backward diodes as well as apparatus grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Abstract: Disclosed is an inventive diode which can reduce a stray capacity to improve various characteristics thereof, in which a dielectric layer, a conductive layer and a second dielectric layer are respectively formed by deposition in this order on an upper face of a semiconductor substrate excluding a central portion of an exposed surface of a P-type region. Then, an anode side electrode is formed extending from the exposed surface of the P-type region to the upper face of the second dielectric layer, and is electrically connected with the P-type region. Herein, the conductive layer is formed such that it is isolated from the electrode by the second dielectric layer, is connected with the semiconductor substrate upper face in a location where the dielectric layer has not been formed, and partially resides in a location sandwiched between the electrode and the semiconductor substrate.

Abstract: An LED and a method of fabricating the LED which utilize controlled oxygen (O) doping to form at least one layer of the LED having an O dopant concentration which is correlated to the dominant emission wavelength of the LED. The O dopant concentration is regulated to be higher when the LED has been configured to have a longer dominant emission wavelength. Since the dominant emission wavelength is dependent on the composition of the active layer(s) of the LED, the O dopant concentration in the layer is related to the composition of the active layer(s). The controlled O doping improves the reliability while minimizing any light output penalty due to the introduction of O dopants. In an exemplary embodiment, the LED is an AlGaInP LED that includes a substrate, an optional distributed Bragg reflector layer, an n-type confining layer, an optional n-type set-back layer, an active region, an optional p-type set-back layer, a p-type confining layer and an optional window layer.

Abstract: The present invention provides a semiconductor device capable of improving a withstand voltage for a wire placed in the neighborhood of a contact. When the direction in which a wiring layer extends in the direction of a plane as viewed from the top of a substrate, is defined as a first direction, the direction orthogonal to the first direction on the plane is defined as a second direction, a radius of curvature of a conductive material layer closest to the opening is defined as R, a point where the conductive material layer and an end of the wiring layer intersect, is defined as X, a point where a straight line extending along the second direction from the point X intersects a straight line extending along the first direction through the center of the radius R of curvature of the conductive material layer, is defined as Y, and the distance between the points X and Y as viewed in the second direction is defined as A, the relations in COS−1(A/R)>46 are established.