Abstract: A surface plasmon polaritron activated semiconductor device uses a surface plasmon wire that functions as an optical waveguide for fast communication of a signal and functions as a energy translator using a wire tip for translating the optical signal passing through the waveguide into plasmon-polaritron energy at a connection of the semiconductor device, such as a transistor, to activate the transistor for improved speed of communications and switching for preferred use in digital systems.

Abstract: A p-type semiconductor carbon nanotube and a method of manufacturing the same are provided. The p-type semiconductor carbon nanotube includes a carbon nanotube; and a halogen element that is attached to an inner wall of the carbon nanotube and accepts electrons from the carbon nanotube to achieve p-type doping of the carbon nanotube. The p-type semiconductor carbon nanotube is stable at high temperatures and can maintain intrinsic good electrical conductivity of the carbon nanotube. The p-type semiconductor carbon nanotube can be relatively easily obtained using a conventional method of manufacturing a carbon nanotube, thereby significantly broadening the range of application of the carbon nanotube to electronic devices.

Abstract: In one embodiment the present invention includes a semiconductor rectifier device comprising a first, second, and third semiconductor regions and a gate. The first semiconductor region is of a first conductivity type. The second semiconductor region is adjacent to the first semiconductor region which has a second conductivity type. The third semiconductor region is adjacent to the second semiconductor region which has the second conductivity type. The gate is proximate to but insulated from the second semiconductor region and electrically coupled to the third semiconductor region. When the first semiconductor region is biased in a first direction, an inversion region forms in the second semiconductor region. The inversion region forms a forward-biased tunnel diode junction with the third semiconductor region. When the first semiconductor region is biased a second direction, the semiconductor rectifier device functions as a reverse-biased PIN diode.

Abstract: A semiconductor sensing device for sensing presence, absence or level of species-of-interest in the environment is disclosed. The semiconductor sensing device comprises at least one layer of molecules deposited thereon. The molecules are electrically-responsive to the species-of-interest in a manner such that when the molecules interact with the species-of-interest, a reverse breakdown voltage characterizing the semiconductor sensing device is modified.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A light-emitting device comprises an active region configured to generate light in response to injected charge, and an n-type material layer and a p-type material layer, wherein at least one of the n-type material layer and the p-type material layer is doped with at least two dopants, at least one of the dopants having an ionization energy higher than the ionization energy level of the other dopant.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A reference element comprising a tunnel-junction device may be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

Abstract: A Si-based diode (10, 10?, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16?, 18, 18?, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially smaller than the backward tunneling current at comparable voltage levels. In some embodiments, the Si-based pn junction includes at least one non-silicon or silicon alloy layer such as at least one SiGe layer (16, 16?, 160, 161). In some embodiments, at least one delta doping (30, 32) is disposed on the silicon substrate in or near the pn junction, that together with the Si-based pn junction define an electrical junction having the backward diode current-voltage characteristic. A large area detector array may include a plurality of such Si-based diodes (10, 10?, 100).

Abstract: Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.

Abstract: The present invention provides a method and apparatus for using light emitting diodes for curing and various solid state lighting applications. The method includes a novel method for cooling the light emitting diodes and mounting the same on heat pipe in a manner which delivers ultra high power in UV, visible and IR regions. Furthermore, the unique LED packaging technology of the present invention utilizes heat pipes that perform very efficiently in very compact space. Much more closely spaced LEDs operating at higher power levels and brightness are possible because the thermal energy is transported in an axial direction down the heat pipe and away from the light-emitting direction rather than a radial direction in nearly the same plane as the “p-n” junction.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: An electronic heat pump device has an emitter and a collector, stems supporting these components, a spacing retention member for keeping a spacing between the stems constant, and a sealing member for maintaining a vacuum between the stems. The emitter has a first semiconductor substrate and an emitter electrode, while the collector has a second semiconductor substrate and a collector electrode. The emitter electrode and the collector electrode are disposed so as to be opposed to each other with a space interposed therebetween. At least one of the first and second semiconductor substrates is integrally formed with electrically and thermally insulative spacers that keep the space between the emitter electrode and the collector electrode constant.

Abstract: The present invention comprises a tunneling device in which the collector electrode is modified so that tunneling of higher energy electrons from the emitter electrode to the collector electrode is enhanced. In one embodiment, the collector electrode is contacted with an insulator layer, preferably aluminum oxide, disposed between the collector and emitter electrodes. The present invention additionally comprises a method for enhancing tunneling of higher energy electrons from an emitter electrode to a collector electrode, the method comprising the step of contacting the collector electrode with an insulator, preferably aluminum oxide, and placing the insulator between the collector electrode and the emitter electrode.

Abstract: A silicon-based interband tunneling diode (10, 110) includes a degenerate p-type doping (22, 130) of acceptors, a degenerate n-type doping (32, 118) of donors disposed on a first side of the degenerate p-type doping (22, 130), and a barrier silicon-germanium layer (20, 136) disposed on a second side of the degenerate p-type doping (22, 130) opposite the first side. The barrier silicon-germanium layer (20, 136) suppresses diffusion of acceptors away from a p/n junction defined by the degenerate p-type and n-type dopings (22, 32, 118, 130).

Abstract: Super lattice structures in conjunction with a tunnel junction to provide an improved contact for multiple components. The tunnel junctions can include a first semiconductor material having a resistance parameter for conducting a current and a second semiconductor material having a resistance parameter that is more restrictive to conduction of a current than the resistance parameter of the first semiconductor material. The first semiconductor material can have a critical thickness at which lattice matching of the first semiconductor material causes dislocation. The second semiconductor material can have a critical thickness at which lattice matching of the second semiconductor material causes dislocation that is thicker than the critical thickness of the first semiconductor material. The tunnel junction can be used in a monolithically manufactured photo transmitter and receiver design.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.

Abstract: In a semiconductor module, twenty five semiconductor devices having light receiving properties, for example, are arranged in five by five matrices using a conductor mechanism formed from six lead frames Each column of semiconductor devices is connected in series and each row of semiconductor devices is connected in parallel. These are embedded in a light transmitting member formed from a transparent synthetic resin, and a positive electrode terminal and a negative electrode terminal are disposed. The semiconductor devices are formed with first and second flat surfaces, and negative electrodes and positive electrodes are disposed.

Abstract: The present invention provides a semiconductor device embracing (a) a first semiconductor region defined by a first end surface, a second end surface opposing to the first end surface and a side boundary surface connecting the first and second end surfaces; (b) a second semiconductor region connected with the first semiconductor region at the second end surface; (c) a third semiconductor region connected with the first semiconductor region at the first end surface; and (d) a fourth semiconductor region having inner surface in contact with the side boundary surface and an impurity concentration lower than the first semiconductor region. The fourth semiconductor region surrounds the first semiconductor region, and is disposed between the second and third semiconductor regions. The first, second and fourth semiconductor regions are first conductivity-type, but the third semiconductor region is a second conductivity type.

Abstract: An overvoltage-proof light-emitting diode has a lamination of light-generating semiconductor layers on a first major surface of a silicon substrate. A front electrode in the form of a bonding pad is mounted centrally atop the light-generating semiconductor layers whereas a back electrode covers a second major surface of the substrate. An overvoltage protector, of which several different forms are disclosed, is disposed between the bonding pad and the second major surface of the substrate. The bonding pad and back electrode serves as electrodes for both LED and overvoltage protector. As seen from above the device, or in a direction normal to the first major surface of the substrate, the overvoltage protector lies substantially wholly beneath the bonding pad.

Abstract: A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element.

Abstract: A tunnel junction structure comprises an n-type tunnel junction layer of a first semiconductor material, a p-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. The first semiconductor material includes gallium (Ga), nitrogen (N), arsenic (As) and is doped with a Group VI dopant. The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer. Doping the first semiconductor material n-type with a Group VI dopant maximizes the doping concentration in the first semiconductor material, thus further improving the probability of tunneling.

Abstract: A flip chip light emitting diode die (10, 10?, 10?) includes a light-transmissive substrate (12, 12?, 12?) and semiconductor layers (14, 14?, 14?) that are selectively patterned to define a device mesa (30, 30?, 30?). A reflective electrode (34, 34?, 34?) is disposed on the device mesa (30, 30?, 30?). The reflective electrode (34, 34?, 34?) includes a light-transmissive insulating grid (42, 42?, 60, 80) disposed over the device mesa (30, 30?, 30?), an ohmic material (44, 44?, 44?, 62) disposed at openings of the insulating grid (42, 42?, 60, 80) and making ohmic contact with the device mesa (30, 30?, 30?), and an electrically conductive reflective film (46, 46?, 46?) disposed over the insulating grid (42, 42?, 60, 80) and the ohmic material (44, 44?, 44?, 62). The electrically conductive reflective film (46, 46?, 46?) electrically communicates with the ohmic material (44, 44?, 44?, 62).

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: With a solar ball 10 serving as a light-receiving semiconductor apparatus, the outer surface of a spherical solar cell 1 is covered with a light-transmitting outer shell member 11, and electrode members 14, 15 are connected to electrodes 6, 7 of the solar cell 1. The outer shell member 11 comprises a capsule 12 produced by bonding together two halves, and a filler 13 that is packed inside this capsule and cured. A solar panel can be configured such that a plurality of the solar balls 10 are arrayed in a matrix and connected in parallel and in series, or a solar panel can be configured such that a multiplicity of spherical solar cells 1 are arrayed in a matrix and covered with a transparent outer shell member. A solar string in the form of a rod or cord can be configured such that a plurality of the solar cells 1 are arrayed in columns and connected in parallel, and then covered with a transparent outer shell member.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a sting of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.

Abstract: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

Abstract: Provided is an MRAM memory cell structure capable of preventing generation of parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diode, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrate.

Abstract: A tunneling junction element comprises: a substrate; a lower conductive layer formed on the substrate; a first oxide layer formed on the lower conductive layer and having a non-stoichiometric composition;a second oxide layer formed on the first oxide layer and having a stoichiometric composition; and an upper conductive layer formed on the second oxide layer, wherein the first oxide layer is oxidized during a process of forming the second oxide layer and has an oxygen concentration which is lower than an oxygen concentration of the second oxide layer and lowers with a depth in the first oxide layer, and the first and second oxide layers form a tunneling barrier.

Abstract: A semiconductor component in which the active junctions extend along at least one cylinder perpendicular to the main surfaces of a semiconductor chip substantially across the entire thickness thereof, said cylinder(s) having a cross-section with an undulated closed curve shape.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: The tunnel junction structure comprises a p-type tunnel junction layer of a first semiconductor material, an n-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. At least one of the semiconductor materials includes gallium (Ga), arsenic (As) and either nitrogen (N) or antimony (Sb). The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer.

Abstract: A small semiconductor package having two electrodes, which can be produced at reduced cost and which features high reliability. The package has a structure in which an anode and a cathode are arranged on one surface of a semiconductor chip, each electrode having a bump electrode for connecting the electrode to an external substrate. An insulating resin is provided on the surface of the semiconductor chip and on the surfaces of the bump electrodes, except at least for the connection portions to the external substrate.

Abstract: In a nitride-system semiconductor, being different from GaAs and Si, Schottky barrier heights ?B change significantly against work functions ?M of metals. Then, for example, on an HEMT in which a buffer layer and a barrier layer constituted by nitride-system semiconductors are sequentially formed on a substrate, and a gate electrode is formed on the barrier layer, when a metal having a relatively large work function ?M is selected as a metal constituting the gate electrode, and the thickness of the barrier layer is adjusted so that the Schottky barrier height ?B becomes larger as compared to a semiconductor surface potential ?S on both sides of the gate electrode, a two-dimensional electron gas cannot exist below the gate electrode even when no recess is formed on a portion immediately beneath the gate electrode on the barrier layer, so that the enhancement operation becomes possible.

Abstract: The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also includes a semiconductor construction comprising a substrate, and a first layer over the substrate. The first layer comprises Ge and one or more of S, Te and Se. A second layer is over the first layer. The second layer comprises M and A, where M is a transition metal and A is one or more of O, S, Te and Se. A third layer is over the second layer, and comprises Ge and one or more of S, Te and Se. The first, second and third layers are together incorporated into an assembly displaying differential negative resistance. Additionally, the invention includes methodology for forming assemblies displaying differential negative resistance, such as tunnel diode assemblies.

Abstract: According to an aspect of the present invention, a nitride semiconductor light emitting device includes a light emitting layer (106) having a quantum well structure with quantum well layers and barrier layers laminated alternately. The well layer is formed of a nitride semiconductor containing In, and the barrier layer is formed of a nitride semiconductor layer containing As, P or Sb. According to another aspect of the present invention, a nitride semiconductor light emitting device includes a light emitting layer having a quantum well structure with quantum well layers and barrier layers laminated alternately. The well layer is formed of GaN1?x?y?zAsxPySbz (0<x+y+z?0.3), and the barrier layer is formed of a nitride semiconductor containing In.

Abstract: A tunnel junction device (102) with minimal hydrogen passivation of acceptors includes a p-type tunnel junction layer (106) of a first semiconductor material doped with carbon. The first semiconductor material includes aluminum, gallium, arsenic and antimony. An n-type tunnel junction layer (104) of a second semiconductor material includes indium, gallium, arsenic and one of aluminum and phosphorous. The junction between the p-type and an-type tunnel junction layers forms a tunnel junction (110).

Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf), and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.

Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

Abstract: An LED includes an insulating substrate; a buffer layer positioned on the insulating substrate; an n+-type contact layer positioned on the buffer layer, the contact layer having a first surface and a second surface; an n-type cladding layer positioned on the first surface of the n+-type contact layer; a light-emitting layer positioned on the n-type cladding layer; a p-type cladding layer positioned on the light-emitting layer; a p-type contact layer positioned on the p-type cladding layer; an n+-type reverse-tunneling layer positioned on the p-type contact layer; a p-type transparent ohmic contact electrode positioned on the n+-type reverse-tunneling layer; and an n-type transparent ohmic contact electrode positioned on the second surface of the n+-type contact layer. The p-type transparent ohmic contact electrode and the n-type transparent ohmic contact electrode are made of the same materials.

Abstract: A tunnel junction device (102) with minimal hydrogen passivation of acceptors includes a p-type tunnel junction layer (106) of a first semiconductor material doped with carbon. The first semiconductor material includes aluminum, gallium, arsenic and antimony. An n-type tunnel junction layer (104) of a second semiconductor material includes indium, gallium, arsenic and one of aluminum and phosphorous. The junction between the p-type and an-type tunnel junction layers forms a tunnel junction (110).

Abstract: A semiconductor device which can suppress an electronic breakdown. In the semiconductor device, a base electrode is connected to a base region in a base contact region defined on a surface of the base region. An N-type region having the same conductivity type as an emitter region is provided beneath a boundary portion of the base contact region to surround the base contact region. In other words, a PN-type diode constituted by the P-type base region and the N-type region is provided beneath the boundary portion of the base contact region.

Abstract: A resonant-cavity light-emitting diode includes a semiconductor light-emitting layer sandwiched between an under and an upper semiconductor distributed Bragg reflector mirror layer, which are formed on the substrate, a light extracting section formed on the upper semiconductor distributed Bragg reflector mirror layer and having an opening to extract light from the semiconductor light-emitting layer, and a groove formed by removing portions of the semiconductor light-emitting layer, under and upper semiconductor distributed Bragg reflector mirror layers which lie in a peripheral portion of the opening of the light extraction section and reach the under semiconductor distributed Bragg reflector mirror layer, the inner wall of the groove being formed to reflect part of light emitted from the semiconductor light-emitting layer into the groove.